Jon Loeliger
commit
504b5cd0e2
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@ -24,9 +24,35 @@
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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extern void ft_cpu_setup(void *blob, bd_t *bd);
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#endif
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#include "cadmus.h"
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extern void ft_cpu_setup(void *blob, bd_t *bd);
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static void cds_pci_fixup(void *blob)
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{
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int len;
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u32 *map;
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int slot;
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int i;
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map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
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len /= sizeof(u32);
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slot = get_pci_slot();
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for (i=0;i<len;i+=7) {
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/* We rotate the interrupt pins so that the mapping
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* changes depending on the slot the carrier card is in.
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*/
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int j;
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map[3] = ((map[3] + slot - 2) % 4) + 1;
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map+=7;
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}
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}
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#endif
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#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
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void
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@ -45,5 +71,7 @@ ft_board_setup(void *blob, bd_t *bd)
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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cds_pci_fixup(blob);
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}
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#endif
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@ -27,6 +27,7 @@
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <spd.h>
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#include <miiphy.h>
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#include "../common/cadmus.h"
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#include "../common/eeprom.h"
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@ -327,3 +328,34 @@ pci_init_board(void)
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pci_mpc85xx_init(&hose);
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#endif
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}
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int last_stage_init(void)
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{
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unsigned int temp;
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/* Change the resistors for the PHY */
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/* This is needed to get the RGMII working for the 1.3+
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* CDS cards */
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if (get_board_version() == 0x13) {
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miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
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TSEC1_PHY_ADDR, 29, 18);
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miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
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TSEC1_PHY_ADDR, 30, &temp);
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temp = (temp & 0xf03f);
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temp |= 2 << 9; /* 36 ohm */
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temp |= 2 << 6; /* 39 ohm */
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miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
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TSEC1_PHY_ADDR, 30, temp);
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miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
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TSEC1_PHY_ADDR, 29, 3);
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miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
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TSEC1_PHY_ADDR, 30, 0x8000);
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}
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return 0;
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}
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@ -45,9 +45,7 @@ struct tsec_info_struct {
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/* The tsec_info structure contains 3 values which the
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* driver uses to determine how to operate a given ethernet
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* device. For now, the structure is initialized with the
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* knowledge that all current implementations have 2 TSEC
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* devices, and one FEC. The information needed is:
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* device. The information needed is:
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* phyaddr - The address of the PHY which is attached to
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* the given device.
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*
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@ -57,18 +55,16 @@ struct tsec_info_struct {
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*
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* phyregidx - This variable specifies which ethernet device
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* controls the MII Management registers which are connected
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* to the PHY. For 8540/8560, only TSEC1 (index 0) has
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* to the PHY. For now, only TSEC1 (index 0) has
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* access to the PHYs, so all of the entries have "0".
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*
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* The values specified in the table are taken from the board's
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* config file in include/configs/. When implementing a new
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* board with ethernet capability, it is necessary to define:
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* TSEC1_PHY_ADDR
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* TSEC1_PHYIDX
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* TSEC2_PHY_ADDR
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* TSEC2_PHYIDX
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* TSECn_PHY_ADDR
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* TSECn_PHYIDX
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*
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* and for 8560:
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* for n = 1,2,3, etc. And for FEC:
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* FEC_PHY_ADDR
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* FEC_PHYIDX
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*/
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@ -95,10 +91,8 @@ static struct tsec_info_struct tsec_info[] = {
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#else
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{ 0, 0, 0},
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#endif
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#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
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{TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
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#elif defined(CONFIG_MPC86XX_TSEC4)
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{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
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#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
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{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
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#else
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{ 0, 0, 0},
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#endif
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@ -838,6 +832,58 @@ struct phy_info phy_info_M88E1111S = {
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},
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};
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static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
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{
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unsigned int temp;
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uint mii_data = read_phy_reg(priv, mii_reg);
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/* Setting MIIM_88E1145_PHY_EXT_CR */
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if (priv->flags & TSEC_REDUCED)
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return mii_data |
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MIIM_M88E1145_RGMII_RX_DELAY |
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MIIM_M88E1145_RGMII_TX_DELAY;
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else
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return mii_data;
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}
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static struct phy_info phy_info_M88E1145 = {
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0x01410cd,
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"Marvell 88E1145",
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4,
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(struct phy_cmd[]) { /* config */
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/* Errata E0, E1 */
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{29, 0x001b, NULL},
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{30, 0x418f, NULL},
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{29, 0x0016, NULL},
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{30, 0xa2da, NULL},
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/* Reset and configure the PHY */
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{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
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{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
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{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
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{MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
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{MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
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{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
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{MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
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{miim_end,}
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},
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(struct phy_cmd[]) { /* startup */
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/* Status is read once to clear old link state */
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{MIIM_STATUS, miim_read, NULL},
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/* Auto-negotiate */
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{MIIM_STATUS, miim_read, &mii_parse_sr},
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{MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
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/* Read the Status */
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{MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
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{miim_end,}
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},
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(struct phy_cmd[]) { /* shutdown */
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{miim_end,}
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},
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};
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struct phy_info phy_info_cis8204 = {
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0x3f11,
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"Cicada Cis8204",
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@ -1055,6 +1101,7 @@ struct phy_info *phy_info[] = {
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&phy_info_cis8204,
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&phy_info_M88E1011S,
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&phy_info_M88E1111S,
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&phy_info_M88E1145,
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&phy_info_dm9161,
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&phy_info_lxt971,
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&phy_info_VSC8244,
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@ -160,6 +160,23 @@
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#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
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#define MIIM_88E1011_PHYSTAT_LINK 0x0400
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#define MIIM_88E1011_PHY_SCR 0x10
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#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
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/* 88E1111 PHY LED Control Register */
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#define MIIM_88E1111_PHY_LED_CONTROL 24
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#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
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#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
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/* 88E1145 Extended PHY Specific Control Register */
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#define MIIM_88E1145_PHY_EXT_CR 20
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#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
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#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
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#define MIIM_88E1145_PHY_PAGE 29
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#define MIIM_88E1145_PHY_CAL_OV 30
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/* DM9161 Control register values */
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#define MIIM_DM9161_CR_STOP 0x0400
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#define MIIM_DM9161_CR_RSTAN 0x1200
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@ -517,8 +517,10 @@
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=400000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0"
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"ramdiskaddr=600000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0" \
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"fdtaddr=400000\0" \
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"fdtfile=your.fdt.dtb\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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@ -526,13 +528,15 @@
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"bootm $loadaddr"
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS1\0" \
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"ramdiskaddr=400000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0"
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"ramdiskaddr=600000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0" \
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"fdtaddr=400000\0" \
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"fdtfile=your.fdt.dtb\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void);
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"bootm $loadaddr"
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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@ -381,7 +381,7 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
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#define CONFIG_MPC85XX_TSEC3 1
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#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
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#undef CONFIG_MPC85XX_TSEC4
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#define CONFIG_MPC85XX_TSEC4 1
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#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
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#undef CONFIG_MPC85XX_FEC
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@ -389,13 +389,11 @@ extern unsigned long get_clock_freq(void);
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#define TSEC2_PHY_ADDR 1
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#define TSEC3_PHY_ADDR 2
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#define TSEC4_PHY_ADDR 3
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#define FEC_PHY_ADDR 3
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define TSEC4_PHYIDX 0
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#define FEC_PHYIDX 0
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/* Options are: eTSEC[0-3] */
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#define CONFIG_ETHPRIME "eTSEC0"
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@ -483,6 +481,8 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
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#define CONFIG_HAS_ETH2
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#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
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#define CONFIG_HAS_ETH3
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#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
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#endif
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#define CONFIG_IPADDR 192.168.1.253
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@ -505,8 +505,11 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS1\0" \
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"ramdiskaddr=400000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0"
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"ramdiskaddr=600000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0" \
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"fdtaddr=400000\0" \
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"fdtfile=your.fdt.dtb\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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@ -514,7 +517,9 @@ extern unsigned long get_clock_freq(void);
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"bootm $loadaddr"
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS1\0" \
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"ramdiskaddr=400000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0"
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"ramdiskaddr=600000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0" \
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"fdtaddr=400000\0" \
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"fdtfile=your.fdt.dtb\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void);
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"bootm $loadaddr"
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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Loading…
Reference in New Issue