ppc4xx: Add AMCC Glacier 406GT eval board support
This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
d8bd643141
commit
4c9e855734
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@ -322,6 +322,7 @@ Stefan Roese <sr@denx.de>
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bunbinga PPC405EP
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canyonlands PPC460EX
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ebony PPC440GP
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glacier PPC460GT
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haleakala PPC405EXr
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katmai PPC440SPe
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kilauea PPC405EX
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1
MAKEALL
1
MAKEALL
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@ -185,6 +185,7 @@ LIST_4xx=" \
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ERIC \
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EXBITGEN \
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G2000 \
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glacier \
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haleakala \
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haleakala_nand \
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hcu4 \
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9
Makefile
9
Makefile
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@ -1172,8 +1172,13 @@ bubinga_config: unconfig
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CANBT_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
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canyonlands_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc
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# Canyonlands & Glacier use different U-Boot images
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canyonlands_config \
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glacier_config: unconfig
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@mkdir -p $(obj)include
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@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
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tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
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@$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc
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canyonlands_nand_config: unconfig
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@mkdir -p $(obj)include $(obj)board/amcc/canyonlands
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@ -35,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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u32 sdr0_cust0;
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u32 pvr = get_pvr();
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/*------------------------------------------------------------------+
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* Setup the interrupt controller polarities, triggers, etc.
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@ -105,14 +106,16 @@ int board_early_init_f(void)
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mtdcr(AHB_TOP, 0x8000004B);
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mtdcr(AHB_BOT, 0x8000004B);
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/*
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* Configure USB-STP pins as alternate and not GPIO
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* It seems to be neccessary to configure the STP pins as GPIO
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* input at powerup (perhaps while USB reset is asserted). So
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* we configure those pins to their "real" function now.
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*/
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gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
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/*
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* Configure USB-STP pins as alternate and not GPIO
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* It seems to be neccessary to configure the STP pins as GPIO
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* input at powerup (perhaps while USB reset is asserted). So
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* we configure those pins to their "real" function now.
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*/
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gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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}
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return 0;
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}
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@ -369,6 +372,7 @@ int misc_init_r(void)
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{
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u32 sdr0_srst1 = 0;
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u32 eth_cfg;
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u32 pvr = get_pvr();
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/*
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* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
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@ -382,7 +386,10 @@ int misc_init_r(void)
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/* Set the for 2 RGMII mode */
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/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
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eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
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eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
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eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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else
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eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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mtsdr(SDR0_ETH_CFG, eth_cfg);
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/*
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@ -275,6 +275,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
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{
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EMAC_4XX_HW_PST hw_p = dev->priv;
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uint32_t failsafe = 10000;
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u32 eth_cfg = 0;
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out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
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@ -308,6 +309,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
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hw_p->print_speed = 1; /* print speed message again next time */
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#endif
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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/* don't bypass the TAHOE0/TAHOE1 cores for Linux */
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mfsdr(SDR0_ETH_CFG, eth_cfg);
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eth_cfg &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
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mtsdr(SDR0_ETH_CFG, eth_cfg);
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#endif
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return;
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}
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@ -494,11 +502,18 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
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u32 zmiifer; /* ZMII0_FER reg. */
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u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
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u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
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int mode;
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zmiifer = 0;
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rmiifer = 0;
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rmiifer1 = 0;
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#if defined(CONFIG_460EX)
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mode = 9;
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#else
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mode = 10;
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#endif
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/* TODO:
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* NOTE: 460GT has 2 RGMII bridge cores:
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* emac0 ------ RGMII0_BASE
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@ -520,7 +535,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
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* Right now only 2*RGMII is supported. Please extend when needed.
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* sr - 2008-02-19
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*/
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switch (9) {
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switch (mode) {
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case 1:
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/* 1 MII - 460EX */
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/* GMC0 EMAC4_0, ZMII Bridge */
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@ -836,10 +851,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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reg = CONFIG_PHY1_ADDR;
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break;
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#endif
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#if defined (CONFIG_440GX)
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#if defined (CONFIG_PHY2_ADDR)
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case 2:
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reg = CONFIG_PHY2_ADDR;
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break;
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#endif
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#if defined (CONFIG_PHY3_ADDR)
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case 3:
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reg = CONFIG_PHY3_ADDR;
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break;
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@ -1131,7 +1148,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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#endif
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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mtdcr (malrxctp8r, hw_p->rx);
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mtdcr (malrxctp8r, hw_p->rx_phys);
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/* set RX buffer size */
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mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
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#else
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@ -1160,6 +1177,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
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break;
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#endif /* CONFIG_440GX */
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#if defined (CONFIG_460GT)
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case 2:
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/* setup MAL tx & rx channel pointers */
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mtdcr (maltxbattr, 0x0);
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mtdcr (malrxbattr, 0x0);
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mtdcr (maltxctp2r, hw_p->tx_phys);
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mtdcr (malrxctp16r, hw_p->rx_phys);
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/* set RX buffer size */
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mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
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break;
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case 3:
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/* setup MAL tx & rx channel pointers */
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mtdcr (maltxbattr, 0x0);
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mtdcr (malrxbattr, 0x0);
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mtdcr (maltxctp3r, hw_p->tx_phys);
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mtdcr (malrxctp24r, hw_p->rx_phys);
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/* set RX buffer size */
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mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
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break;
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#endif /* CONFIG_460GT */
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case 0:
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default:
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/* setup MAL tx & rx channel pointers */
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@ -1866,14 +1903,22 @@ int ppc_4xx_eth_initialize (bd_t * bis)
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case 2:
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memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
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bis->bi_enet2addr, 6);
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#if defined(CONFIG_460GT)
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hw_addr[eth_num] = 0x300;
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#else
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hw_addr[eth_num] = 0x400;
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#endif
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break;
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#endif
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#ifdef CONFIG_HAS_ETH3
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case 3:
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memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
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bis->bi_enet3addr, 6);
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#if defined(CONFIG_460GT)
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hw_addr[eth_num] = 0x400;
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#else
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hw_addr[eth_num] = 0x600;
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#endif
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break;
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#endif
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}
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@ -27,10 +27,14 @@
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */
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/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
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#ifndef CONFIG_CANYONLANDS
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#define CONFIG_460GT 1 /* Specific PPC460GT */
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#else
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#define CONFIG_460EX 1 /* Specific PPC460EX */
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#endif
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#define CONFIG_440 1
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_460EX 1 /* Specific PPC460EX support */
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#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
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@ -262,8 +266,15 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
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#define CONFIG_PHY1_ADDR 1
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#define CONFIG_HAS_ETH0 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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/* Only Glacier (460GT) has 4 EMAC interfaces */
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#ifdef CONFIG_460GT
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#define CONFIG_PHY2_ADDR 2
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#define CONFIG_PHY3_ADDR 3
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#define CONFIG_HAS_ETH2
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#define CONFIG_HAS_ETH3
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#endif
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#define CONFIG_NET_MULTI 1
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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@ -275,6 +286,8 @@
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/*-----------------------------------------------------------------------
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* USB-OHCI
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*----------------------------------------------------------------------*/
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/* Only Canyonlands (460EX) has USB */
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#ifdef CONFIG_460EX
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_USB_STORAGE
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#undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
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@ -283,6 +296,7 @@
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#define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000)
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#define CFG_USB_OHCI_SLOT_NAME "ppc440"
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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#endif
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/*-----------------------------------------------------------------------
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* Default environment
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@ -293,9 +307,21 @@
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#undef CONFIG_BOOTARGS
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/* Setup some board specific values for the default environment variables */
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#ifdef CONFIG_CANYONLANDS
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#define CONFIG_HOSTNAME canyonlands
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#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0"
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#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0"
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#else
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#define CONFIG_HOSTNAME glacier
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#define CFG_BOOTFILE "bootfile=glacier/uImage\0"
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#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0"
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CFG_BOOTFILE \
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CFG_DTBFILE \
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"netdev=eth0\0" \
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"hostname=canyonlands\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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@ -315,18 +341,16 @@
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"rootpath=/opt/eldk/ppc_4xxFP\0" \
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"bootfile=canyonlands/uImage\0" \
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"fdt_file=canyonlands/canyonlands.dtb\0" \
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"fdt_addr=400000\0" \
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"kernel_addr=fc000000\0" \
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"ramdisk_addr=fc200000\0" \
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"initrd_high=30000000\0" \
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"load=tftp 200000 canyonlands/u-boot.bin\0" \
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"load=tftp 200000 ${hostname}/u-boot.bin\0" \
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"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
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"cp.b ${fileaddr} fffa0000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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"nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \
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"nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \
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"nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
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"setenv filesize;saveenv\0" \
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"nupd=run nload nupdate\0" \
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@ -361,8 +385,6 @@
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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@ -373,7 +395,11 @@
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#ifdef CONFIG_460EX
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_USB
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#endif
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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@ -487,6 +513,8 @@
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/*
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* PPC4xx GPIO Configuration
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*/
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#ifdef CONFIG_460EX
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/* 460EX: Use USB configuration */
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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@ -559,6 +587,81 @@
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
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} \
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}
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#else
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/* 460GT: Use EMAC2+3 configuration */
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
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{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
|
||||
}, \
|
||||
{ \
|
||||
/* GPIO Core 1 */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
|
||||
} \
|
||||
}
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
|
|
|
|||
|
|
@ -2023,9 +2023,13 @@
|
|||
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
|
||||
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
|
||||
#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
|
||||
#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
|
||||
#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
|
||||
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
|
||||
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
|
||||
#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
|
||||
#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
|
||||
#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
|
||||
#endif /* CONFIG_440GX */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -213,6 +213,10 @@ typedef struct emac_4xx_hw_st {
|
|||
#define RGMII_FER (RGMII_BASE + 0x00)
|
||||
#define RGMII_SSR (RGMII_BASE + 0x04)
|
||||
|
||||
#if defined(CONFIG_460GT)
|
||||
#define RGMII1_BASE_OFFSET 0x100
|
||||
#endif
|
||||
|
||||
/* RGMII Function Enable (FER) Register Bit Definitions */
|
||||
/* Note: for EMAC 2 and 3 only, 440GX only */
|
||||
#define RGMII_FER_DIS (0x00)
|
||||
|
|
|
|||
Loading…
Reference in New Issue