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Merge with rsync://git-user@source.denx.net/git/u-boot.git

This commit is contained in:
Jon Loeliger 2005-08-02 13:53:07 -05:00
parent de1d0a6995 095b8a3798
commit 4b1d95d96a
103 changed files with 10209 additions and 5130 deletions
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23
CHANGELOG
View File

@ -46,6 +46,29 @@ Changes for U-Boot 1.1.3:
Eliminates the CONFIG_MPC8560 option entirely. Distributes the
new CONFIG_CPM2 option to each 8260 board.
* Patch by Stefan Roese, 01 Aug 2005:
- Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
(former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
for details.
- Sycamore (PPC405GPr) eval board added (Walnut port is extended
to run on both 405GP and 405GPr eval boards).
* Patch by Steven Blakeslee, 27 Jul 2005:
- Add support for AMCC PPC440EP/GR.
- Add support for AMCC Yosemite PPC440EP eval board.
- Add support for AMCC Yellowstone PPC440GR eval board.
* Minor fixes for PPChameleon Board:
- fix alignment of NAND size
- make code do what the comment says
* Implement h/w sector protection status synchronization at boot.
The code is provided for, and was tested on, the Yukon/Alaska
and PM520 boards only.
A bug in flash_real_protect() for the Yukon board was fixed by
adding a function that tells if two banks are on one flash chip.
* Fix sysmon POST problem: check I2C error codes
This fixes a problem of displaying bogus voltages when the voltages
are so low that the I2C devices start failing while the rest of the

6
MAINTAINERS
View File

@ -210,6 +210,11 @@ Keith Outwater <Keith_Outwater@mvis.com>
GEN860T MPC860T
GEN860T_SC MPC860T
Stefan Roese <sr@denx.de>
sycamore PPC4xx
walnut PPC4xx
Frank Panno <fpanno@delphintech.com>
ep8260 MPC8260
@ -327,7 +332,6 @@ Unknown / orphaned boards:
CRAYL1 PPC4xx
ERIC PPC4xx
WALNUT405 PPC4xx
MOUSSE MPC824x

9
MAKEALL
View File

@ -60,16 +60,17 @@ LIST_8xx=" \
#########################################################################
LIST_4xx=" \
ADCIOP AR405 ASH405 BUBINGA405EP \
ADCIOP AR405 ASH405 bubinga \
CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \
EBONY ERIC EXBITGEN HUB405 \
ebony ERIC EXBITGEN HUB405 \
JSE MIP405 MIP405T ML2 \
ml300 OCOTEA OCRTC ORSG \
ml300 ocotea OCRTC ORSG \
PCI405 PIP405 PLU405 PMC405 \
PPChameleonEVB VOH405 W7OLMC W7OLMG \
WALNUT405 WUH405 XPEDITE1K \
walnut WUH405 XPEDITE1K yellowstone \
yosemite \
"
#########################################################################

29
Makefile
View File

@ -710,8 +710,11 @@ AR405_config: unconfig
ASH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ash405 esd
BUBINGA405EP_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx bubinga405ep
bamboo_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc
bubinga_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc
CANBT_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx canbt esd
@ -762,8 +765,8 @@ DP405_config: unconfig
DU405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
EBONY_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ebony
ebony_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ebony amcc
ERIC_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx eric
@ -797,8 +800,8 @@ ML2_config: unconfig
ml300_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
OCOTEA_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ocotea
ocotea_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc
OCRTC_config \
ORSG_config: unconfig
@ -849,6 +852,10 @@ PPChameleonEVB_HI_33_config: unconfig
sbc405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx sbc405
sycamore_config: unconfig
@echo "Configuring for sycamore board as subset of walnut..."
@./mkconfig -a walnut ppc ppc4xx walnut amcc
VOH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
@ -859,8 +866,8 @@ W7OLMC_config \
W7OLMG_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx w7o
WALNUT405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx walnut405
walnut_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx walnut amcc
WUH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd
@ -868,6 +875,12 @@ WUH405_config: unconfig
XPEDITE1K_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
yosemite_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc
yellowstone_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
#########################################################################
## MPC8220 Systems
#########################################################################

6
README
View File

@ -295,7 +295,7 @@ The following options need to be configured:
CONFIG_FADS823 CONFIG_NETTA CONFIG_V37
CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMC
CONFIG_FADS860T CONFIG_NX823 CONFIG_W7OLMG
CONFIG_FLAGADM CONFIG_OCRTC CONFIG_WALNUT405
CONFIG_FLAGADM CONFIG_OCRTC CONFIG_WALNUT
CONFIG_FPS850L CONFIG_ORSG CONFIG_ZPC1900
CONFIG_FPS860L CONFIG_OXC CONFIG_ZUMA
@ -2192,7 +2192,7 @@ configurations; the following names are supported:
FADS850SAR_config omap1510inn_config TQM850L_config
FADS860T_config omap1610h2_config TQM855L_config
FPS850L_config omap1610inn_config TQM860L_config
omap5912osk_config WALNUT405_config
omap5912osk_config walnut_config
omap2420h4_config Yukon8220_config
ZPC1900_config
@ -3135,7 +3135,7 @@ locked as (mis-) used as memory, etc.
CFG_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
Walnut405.h should work for you. I'd set it to a value larger
walnut.h should work for you. I'd set it to a value larger
than your SDRAM module. If you have a 64MB SDRAM module, set
it above 400_0000. Just make sure your board has no resources
that are supposed to respond to that address! That code in

161
board/alaska/flash.c
View File

@ -64,7 +64,6 @@ typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FLASH_CYCLE2 0x02aa
#define WR_BLOCK 0x20
/*-----------------------------------------------------------------------
* Functions
*/
@ -74,6 +73,9 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest);
static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t * info);
void inline spin_wheel (void);
static void flash_sync_real_protect (flash_info_t * info);
static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
static unsigned char same_chip_banks (int bank1, int bank2);
/*-----------------------------------------------------------------------
*/
@ -115,6 +117,9 @@ unsigned long flash_init (void)
break;
}
size += flash_info[i].size;
/* get the h/w and s/w protection status in sync */
flash_sync_real_protect(&flash_info[i]);
}
/* Protect monitor and environment sectors
@ -167,7 +172,6 @@ static void flash_get_offsets (ulong base, flash_info_t * info)
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
info->protect[i] = 0;
}
}
}
@ -305,6 +309,98 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
}
/*
* This function gets the u-boot flash sector protection status
* (flash_info_t.protect[]) in sync with the sector protection
* status stored in hardware.
*/
static void flash_sync_real_protect (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F128J3A:
for (i = 0; i < info->sector_count; ++i) {
info->protect[i] = intel_sector_protected(info, i);
}
break;
case FLASH_AM040:
default:
/* no h/w protect support */
break;
}
}
/*
* checks if "sector" in bank "info" is protected. Should work on intel
* strata flash chips 28FxxxJ3x in 8-bit mode.
* Returns 1 if sector is protected (or timed-out while trying to read
* protection status), 0 if it is not.
*/
static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
{
FPWV *addr;
FPWV *lock_conf_addr;
ulong start;
unsigned char ret;
/*
* first, wait for the WSM to be finished. The rationale for
* waiting for the WSM to become idle for at most
* CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
* because of: (1) erase, (2) program or (3) lock bit
* configuration. So we just wait for the longest timeout of
* the (1)-(3), i.e. the erase timeout.
*/
/* wait at least 35ns (W12) before issuing Read Status Register */
udelay(1);
addr = (FPWV *) info->start[sector];
*addr = (FPW) INTEL_STATUS;
start = get_timer (0);
while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
*addr = (FPW) INTEL_RESET; /* restore read mode */
printf("WSM busy too long, can't get prot status\n");
return 1;
}
}
/* issue the Read Identifier Codes command */
*addr = (FPW) INTEL_READID;
/* wait at least 35ns (W12) before reading */
udelay(1);
/* Intel example code uses offset of 4 for 8-bit flash */
lock_conf_addr = (FPWV *) info->start[sector] + 4;
ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
/* put flash back in read mode */
*addr = (FPW) INTEL_RESET;
return ret;
}
/*
* Checks if "bank1" and "bank2" are on the same chip. Returns 1 if they
* are and 0 otherwise.
*/
static unsigned char same_chip_banks (int bank1, int bank2)
{
unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = {
{1, 1, 0, 0},
{1, 1, 0, 0},
{0, 0, 1, 1},
{0, 0, 1, 1}
};
return same_chip[bank1][bank2];
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
@ -729,7 +825,9 @@ void inline spin_wheel (void)
int flash_real_protect (flash_info_t * info, long sector, int prot)
{
ulong start;
int i;
int i, j;
int curr_bank;
int bank;
int rc = 0;
FPWV *addr = (FPWV *) (info->start[sector]);
int flag = disable_interrupts ();
@ -779,23 +877,54 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
* we have to restore lock bits of protected sectors.
*/
if (!prot) {
for (i = 0; i < info->sector_count; i++) {
if (info->protect[i]) {
start = get_timer (0);
addr = (FPWV *) (info->start[i]);
*addr = INTEL_LOCKBIT; /* Sector lock bit */
*addr = INTEL_PROTECT; /* set */
while ((*addr & INTEL_FINISHED) !=
INTEL_FINISHED) {
if (get_timer (start) >
CFG_FLASH_UNLOCK_TOUT) {
printf ("Flash lock bit operation timed out\n");
rc = 1;
break;
/*
* re-locking must be done for all banks that belong on one
* FLASH chip, as all the sectors on the chip were unlocked
* by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
* that banks never span chips, in particular chips which
* support h/w protection differently).
*/
/* find the current bank number */
curr_bank = CFG_MAX_FLASH_BANKS + 1;
for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) {
if (&flash_info[j] == info) {
curr_bank = j;
}
}
if (curr_bank == CFG_MAX_FLASH_BANKS + 1) {
printf("Error: can't determine bank number!\n");
}
for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) {
if (!same_chip_banks(curr_bank, bank)) {
continue;
}
info = &flash_info[bank];
for (i = 0; i < info->sector_count; i++) {
if (info->protect[i]) {
start = get_timer (0);
addr = (FPWV *) (info->start[i]);
*addr = INTEL_LOCKBIT; /* Sector lock bit */
*addr = INTEL_PROTECT; /* set */
while ((*addr & INTEL_FINISHED) !=
INTEL_FINISHED) {
if (get_timer (start) >
CFG_FLASH_UNLOCK_TOUT) {
printf ("Flash lock bit operation timed out\n");
rc = 1;
break;
}
}
}
}
}
/*
* get the s/w sector protection status in sync with the h/w,
* in case something went wrong during the re-locking.
*/
flash_sync_real_protect(info); /* resets flash to read mode */
}
if (flag)

48
board/amcc/bamboo/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
#OBJS += flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

439
board/amcc/bamboo/bamboo.c Normal file
View File

@ -0,0 +1,439 @@
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
int board_early_init_f(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
#if 0 /* test-only */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
#else
mtebc(pb0ap, 0x04055200); /* FLASH/SRAM */
mtebc(pb0cr, 0xfff18000); /* BAS=0xfe0 1MB r/w 8-bit */
#endif
mtebc(pb3ap, 0x00000000);
mtebc(pb3cr, 0x00000000);
mtebc(pb4ap, 0x00000000);
mtebc(pb4cr, 0x00000000);
mtebc(pb5ap, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
/*setup Address lines for flash sizes larger than 16Meg. */
out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
/*setup emac */
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
/*UART1 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
#if 0 /* test-only */
/*clear tmrclk divisor */
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
#endif
return 0;
}
int checkboard(void)
{
sys_info_t sysinfo;
unsigned char *s = getenv("serial#");
get_sys_info(&sysinfo);
printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
void sdram_init(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_clktr, 0x40000000); /* ?? */
mtsdram(mem_wddctr, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
*------------------------------------------------------------------*/
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_tr1, 0x8080080b); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x84000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
sdram_init();
return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
unsigned long addr;
/*--------------------------------------------------------------------------+
* Bamboo is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Bamboo is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
*
************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
}
#endif

44
board/amcc/bamboo/config.mk Normal file
View File

@ -0,0 +1,44 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# esd ADCIOP boards
#
#TEXT_BASE = 0x00001000
ifeq ($(ramsym),1)
TEXT_BASE = 0xFBD00000
else
TEXT_BASE = 0xFFF80000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

107
board/amcc/bamboo/init.S Normal file
View File

@ -0,0 +1,107 @@
/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ; \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
0xf0000000 must be first, before relocation SA_I must be off to use the
dcache as stack. It is patched after relocation to enable SA_I
*/
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end

155
board/amcc/bamboo/u-boot.lds Normal file
View File

@ -0,0 +1,155 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/bamboo/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

1
board/bubinga405ep/Makefile → board/amcc/bubinga/Makefile
View File

@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)

84
board/amcc/bubinga/bubinga.c Normal file
View File

@ -0,0 +1,84 @@
/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
long int spd_sdram(void);
#include <common.h>
#include <asm/processor.h>
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000010);
mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
unsigned char *s = getenv("serial#");
puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return (0);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/* -------------------------------------------------------------------------
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
long int initdram(int board_type)
{
long int ret;
ret = spd_sdram();
return ret;
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("test: xxx MB - ok\n");
return (0);
}

7
board/walnut405/config.mk → board/amcc/bubinga/config.mk
View File

@ -21,9 +21,4 @@
# MA 02111-1307 USA
#
#
# esd ADCIOP boards
#
#TEXT_BASE = 0xFFFE0000
TEXT_BASE = 0xFFF80000
TEXT_BASE = 0xFFFC0000

204
board/amcc/bubinga/flash.c Normal file
View File

@ -0,0 +1,204 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
/*
* include common flash code (for amcc boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static void flash_get_offsets(ulong base, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 =
flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[0]);
#ifdef CFG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
size_b1 = 0;
flash_info[0].size = size_b0;
}
/* 2 banks */
else {
size_b1 =
flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
&flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
flash_get_offsets(base_b0, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b0 + size_b0 - CFG_MONITOR_LEN,
base_b0 + size_b0 - 1, &flash_info[0]);
/* Also protect sector containing initial power-up instruction */
/* (flash_protect() checks address range - other call ignored) */
(void)flash_protect(FLAG_PROTECT_SET,
0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
(void)flash_protect(FLAG_PROTECT_SET,
0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 =
flash_get_size((vu_long *) base_b1, &flash_info[1]);
flash_get_offsets(base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b1 + size_b1 - CFG_MONITOR_LEN,
base_b1 + size_b1 - 1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR,
base_b0 + size_b0 - CFG_MONITOR_LEN,
base_b0 + size_b0 - 1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
} /* else 2 banks */
return (size_b0 + size_b1);
}
static void flash_get_offsets(ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] =
base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
}

1
board/bubinga405ep/u-boot.lds → board/amcc/bubinga/u-boot.lds
View File

@ -62,7 +62,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/bubinga405ep/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)

555
board/amcc/common/flash.c Normal file
View File

@ -0,0 +1,555 @@
/*
* (C) Copyright 2004-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static int write_word(flash_info_t * info, ulong dest, ulong data);
void flash_print_info(flash_info_t * info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_STM:
printf("STM ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_SST:
printf("SST ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
printf("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AMD016:
printf("AM29F016D (16 Mbit, uniform sector size)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_AM033C:
printf("AM29LV033C (32 Mbit, top boot sector)\n");
break;
case FLASH_SST800A:
printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
case FLASH_SST160A:
printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
printf(" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count - 1))
size = info->start[i + 1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k = 0; k < size; k++) {
if (*flash++ != 0xffffffff) {
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s%s",
info->start[i],
erased ? " E" : " ", info->protect[i] ? "RO " : " ");
}
printf("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
short i;
CFG_FLASH_WORD_SIZE value;
ulong base = (ulong) addr;
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
udelay(1000);
value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr2[1]; /* device ID */
DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) {
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
info->flash_id += FLASH_AMD016;
info->sector_count = 32;
info->size = 0x00200000;
break; /* => 2 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
info->flash_id += FLASH_AMDLV033C;
info->sector_count = 64;
info->size = 0x00400000;
break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] =
base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
/* For AMD29033C flash we need to resend the command of *
* reading flash protection for upper 8 Mb of flash */
if (i == 32) {
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
}
/* issue bank reset to return to read mode */
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
return (info->size);
}
int wait_for_DQ7(flash_info_t * info, int sect)
{
ulong start, now, last;
volatile CFG_FLASH_WORD_SIZE *addr =
(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0);
last = start;
while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
(CFG_FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
return 0;
}
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
for (i = 0; i < 50; i++)
udelay(1000); /* wait 1 ms */
} else {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
/* reset to read mode */
addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word(flash_info_t * info, ulong dest, ulong data)
{
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}

0
board/ebony/Makefile → board/amcc/ebony/Makefile
View File

2
board/ebony/config.mk → board/amcc/ebony/config.mk
View File

@ -30,7 +30,7 @@
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else
TEXT_BASE = 0xFFF80000
TEXT_BASE = 0xFFFC0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1

187
board/ebony/ebony.c → board/amcc/ebony/ebony.c
View File

@ -20,9 +20,7 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include "ebony.h"
#include <asm/processor.h>
#include <spd_sdram.h>
@ -30,99 +28,102 @@
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
long int fixed_sdram (void);
long int fixed_sdram(void);
int board_early_init_f (void)
int board_early_init_f(void)
{
uint reg;
unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned char status;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr (ebccfga, xbcfg);
reg = mfdcr (ebccfgd);
mtdcr (ebccfgd, reg | 0x04000000); /* Set ATC */
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc (pb1ap, 0x02815480); /* NVRAM/RTC */
mtebc (pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc (pb7ap, 0x01015280); /* FPGA registers */
mtebc (pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc(pb7ap, 0x01015280); /* FPGA registers */
mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
/* read FPGA_REG0 and set the bus controller */
status = *fpga_base;
if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
mtebc (pb0ap, 0x9b015480); /* FLASH/SRAM */
mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc (pb2ap, 0x9b015480); /* 4MB FLASH */
mtebc (pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
} else {
mtebc (pb0ap, 0x9b015480); /* 4MB FLASH */
mtebc (pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
/* set CS2 if FLASH_ONBD_N == 0 */
if (!(status & FLASH_ONBD_N)) {
mtebc (pb2ap, 0x9b015480); /* FLASH/SRAM */
mtebc (pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
}
}
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
return 0;
}
int checkboard (void)
int checkboard(void)
{
sys_info_t sysinfo;
unsigned char *s = getenv("serial#");
get_sys_info (&sysinfo);
get_sys_info(&sysinfo);
printf ("Board: IBM 440GP Evaluation Board (Ebony)\n");
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
long int initdram (int board_type)
long int initdram(int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram (0);
dram_size = spd_sdram(0);
#else
dram_size = fixed_sdram ();
dram_size = fixed_sdram();
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
int testdram(void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
@ -133,7 +134,7 @@ int testdram (void)
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
@ -143,7 +144,7 @@ int testdram (void)
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
@ -159,18 +160,18 @@ int testdram (void)
* PLB @ 133 MHz
*
************************************************************************/
long int fixed_sdram (void)
long int fixed_sdram(void)
{
uint reg;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@ -178,28 +179,27 @@ long int fixed_sdram (void)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram (mem_mcsts, reg);
mfsdram(mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
return (128 * 1024 * 1024); /* 128 MB */
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
#endif /* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
@ -214,23 +214,23 @@ long int fixed_sdram (void)
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller * hose )
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
if( (strap & 0x00100000) == 0 ){
printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0;
}
strap = mfdcr(cpc0_strp1);
if ((strap & 0x00100000) == 0) {
printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0;
}
return 1;
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
@ -241,38 +241,37 @@ int pci_pre_init(struct pci_controller * hose )
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
void pci_target_init(struct pci_controller *hose)
{
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
out32r(PCIX0_PIM0SA, 0); /* disable */
out32r(PCIX0_PIM1SA, 0); /* disable */
out32r(PCIX0_PIM2SA, 0); /* disable */
out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
out32r(PCIX0_PIM0LAH, 0);
out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out32r( PCIX0_BAR0, 0 );
out32r(PCIX0_BAR0, 0);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
@ -292,7 +291,7 @@ void pci_target_init(struct pci_controller * hose )
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* The ebony board is always configured as host. */
return(1);
/* The ebony board is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
#endif /* defined(CONFIG_PCI) */

140
board/amcc/ebony/flash.c Normal file
View File

@ -0,0 +1,140 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
{0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
{0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
{0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
{0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
{0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
};
/*
* include common flash code (for amcc boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned char switch_status;
unsigned short index = 0;
int i;
/* read FPGA base register FPGA_REG0 */
switch_status = *fpga_base;
/* check the bitmap of switch status */
if (switch_status & BOOT_SMALL_FLASH) {
index += BOOT_SMALL_FLASH_VAL;
}
if (switch_status & FLASH_ONBD_N) {
index += FLASH_ONBD_N_VAL;
}
if (switch_status & FLASH_SRAM_SEL) {
index += FLASH_SRAM_SEL_VAL;
}
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size((vu_long *)
flash_addr_table[index][i],
&flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[2]);
#ifdef CFG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[2]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
&flash_info[2]);
#endif
total_b += flash_info[i].size;
}
return total_b;
}

0
board/ebony/init.S → board/amcc/ebony/init.S
View File

2
board/ebony/u-boot.lds → board/amcc/ebony/u-boot.lds
View File

@ -67,7 +67,7 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/ebony/init.o (.text)
board/amcc/ebony/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)

0
board/ocotea/Makefile → board/amcc/ocotea/Makefile
View File

0
board/ocotea/config.mk → board/amcc/ocotea/config.mk
View File

150
board/amcc/ocotea/flash.c Normal file
View File

@ -0,0 +1,150 @@
/*
* (C) Copyright 2004-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
{0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
{0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
{0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
{0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
{0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
{0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
{0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
{0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
};
/*
* include common flash code (for amcc boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_word(flash_info_t * info, ulong dest, ulong data);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned char switch_status;
unsigned short index = 0;
int i;
/* read FPGA base register FPGA_REG0 */
switch_status = *fpga_base;
/* check the bitmap of switch status */
if (switch_status & BOOT_SMALL_FLASH) {
index += BOOT_SMALL_FLASH_VAL;
}
if (switch_status & FLASH_ONBD_N) {
index += FLASH_ONBD_N_VAL;
}
if (switch_status & FLASH_SRAM_SEL) {
index += FLASH_SRAM_SEL_VAL;
}
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] =
flash_get_size((vu_long *) flash_addr_table[index][i],
&flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf
("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[i]);
#ifdef CFG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[i]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
&flash_info[i]);
#endif
total_b += flash_info[i].size;
}
return total_b;
}

0
board/ocotea/init.S → board/amcc/ocotea/init.S
View File

12
board/ocotea/ocotea.c → board/amcc/ocotea/ocotea.c
View File

@ -1,6 +1,9 @@
/*
* Copyright (C) 2004 PaulReynolds@lhsolutions.com
*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -184,10 +187,17 @@ int board_early_init_f (void)
int checkboard (void)
{
sys_info_t sysinfo;
unsigned char *s = getenv ("serial#");
get_sys_info (&sysinfo);
printf ("Board: IBM 440GX Evaluation Board\n");
printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
if (s != NULL) {
puts (", serial# ");
puts (s);
}
putc ('\n');
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);

0
board/ocotea/ocotea.h → board/amcc/ocotea/ocotea.h
View File

2
board/ocotea/u-boot.lds → board/amcc/ocotea/u-boot.lds
View File

@ -67,7 +67,7 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/ocotea/init.o (.text)
board/amcc/ocotea/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)

1
board/walnut405/Makefile → board/amcc/walnut/Makefile
View File

@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)

7
board/bubinga405ep/config.mk → board/amcc/walnut/config.mk
View File

@ -21,9 +21,4 @@
# MA 02111-1307 USA
#
#
# esd ADCIOP boards
#
#TEXT_BASE = 0xFFFE0000
TEXT_BASE = 0xFFF80000
TEXT_BASE = 0xFFFC0000

199
board/amcc/walnut/flash.c Normal file
View File

@ -0,0 +1,199 @@
/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
/*
* include common flash code (for amcc boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static void flash_get_offsets(ulong base, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 =
flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[0]);
#ifdef CFG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
size_b1 = 0;
flash_info[0].size = size_b0;
} else {
/* 2 banks */
size_b1 =
flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
&flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr =
(pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr =
(pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
flash_get_offsets(base_b0, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b0 + size_b0 - monitor_flash_len,
base_b0 + size_b0 - 1, &flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 =
flash_get_size((vu_long *) base_b1, &flash_info[1]);
flash_get_offsets(base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b1 + size_b1 -
monitor_flash_len,
base_b1 + size_b1 - 1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR,
base_b0 + size_b0 -
monitor_flash_len,
base_b0 + size_b0 - 1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
} /* else 2 banks */
return (size_b0 + size_b1);
}
static void flash_get_offsets(ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] =
base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
}

1
board/walnut405/u-boot.lds → board/amcc/walnut/u-boot.lds
View File

@ -62,7 +62,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/walnut405/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)

111
board/amcc/walnut/walnut.c Normal file
View File

@ -0,0 +1,111 @@
/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
int board_early_init_f(void)
{
/*-------------------------------------------------------------------------+
| Interrupt controller setup for the Walnut/Sycamore board.
| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
| IRQ 16 405GP internally generated; active low; level sensitive
| IRQ 17-24 RESERVED
| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
| IRQ 27 (EXT IRQ 2) Not Used
| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
| Note for Walnut board:
| An interrupt taken for the FPGA (IRQ 25) indicates that either
| the Mouse, Keyboard, IRDA, or External Expansion caused the
| interrupt. The FPGA must be read to determine which device
| caused the interrupt. The default setting of the FPGA clears
|
+-------------------------------------------------------------------------*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004
*(volatile char *)(FPGA_BRDC) |= 0x1;
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
unsigned char *s = getenv("serial#");
uint pvr = get_pvr();
if (pvr == PVR_405GPR_RB) {
puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
} else {
puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
}
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return (0);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/*
* initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
*/
long int initdram(int board_type)
{
return spd_sdram(0);
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("test: xxx MB - ok\n");
return (0);
}

48
board/amcc/yellowstone/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
OBJS += flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

44
board/amcc/yellowstone/config.mk Normal file
View File

@ -0,0 +1,44 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# esd ADCIOP boards
#
#TEXT_BASE = 0x00001000
ifeq ($(ramsym),1)
TEXT_BASE = 0xFBD00000
else
TEXT_BASE = 0xFFF80000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

311
board/ocotea/flash.c → board/amcc/yellowstone/flash.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2004-2005
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
@ -15,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -31,40 +31,35 @@
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
/*
* Ported to XPedite1000, 1/2 mb boot flash only
* Travis B. Sawyer, <travis.sawyer@sandburst.com>
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
unsigned long flash_addr_table[512][CFG_MAX_FLASH_BANKS] = {
{0xfe000000}
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
{0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
{0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
{0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
{0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
{0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
{0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
{0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
{0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
};
/*-----------------------------------------------------------------------
@ -73,12 +68,9 @@ static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_word(flash_info_t * info, ulong dest, ulong data);
#ifdef CONFIG_OCOTEA
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
#endif
#define ADDR0 0xaaaa
#define ADDR1 0x5554
#define FLASH_WORD_SIZE unsigned short
/*-----------------------------------------------------------------------
*/
@ -87,25 +79,9 @@ unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
unsigned char switch_status;
unsigned short index = 0;
int i;
/* read FPGA base register FPGA_REG0 */
switch_status = *fpga_base;
/* check the bitmap of switch status */
if (switch_status & BOOT_SMALL_FLASH) {
index += BOOT_SMALL_FLASH_VAL;
}
if (switch_status & FLASH_ONBD_N) {
index += FLASH_ONBD_N_VAL;
}
if (switch_status & FLASH_SRAM_SEL) {
index += FLASH_SRAM_SEL_VAL;
}
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
@ -121,11 +97,14 @@ unsigned long flash_init(void)
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], &flash_info[i]);
size_b[i] = flash_get_size((vu_long *)
flash_addr_table[index][i],
&flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
printf
("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
@ -133,11 +112,9 @@ unsigned long flash_init(void)
total_b += flash_info[i].size;
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[2]);
/* FLASH protect Monitor */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE, 0xFFFFFFFF, &flash_info[0]);
return total_b;
}
@ -161,9 +138,6 @@ void flash_print_info(flash_info_t * info)
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_STM:
printf("STM ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
@ -176,6 +150,9 @@ void flash_print_info(flash_info_t * info)
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMD016:
printf("AM29F016D (16 Mbit, uniform sector size)\n");
break;
case FLASH_AM040:
printf("AM29F040 (512 Kbit, uniform sector size)\n");
break;
@ -203,9 +180,6 @@ void flash_print_info(flash_info_t * info)
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_AMDLV033C:
printf("AM29LV033C (32 Mbit, top boot sector)\n");
break;
case FLASH_SST800A:
printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
@ -230,7 +204,7 @@ void flash_print_info(flash_info_t * info)
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *) info->start[i];
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k = 0; k < size; k++) {
if (*flash++ != 0xffffffff) {
@ -249,6 +223,9 @@ void flash_print_info(flash_info_t * info)
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
@ -262,18 +239,19 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
ulong base = (ulong) addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned) addr);
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */
udelay(10000);
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x00AA;
udelay(1000);
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = (FLASH_WORD_SIZE) 0x0055;
udelay(1000);
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x0090;
udelay(1000);
value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
@ -293,96 +271,29 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
return (0); /* no or unknown flash */
}
value = addr2[1]; /* device ID */
#ifdef CONFIG_ADCIOP
value = addr2[0]; /* device ID */
debug("\ndev_code=%x\n", value);
#else
value = addr2[1]; /* device ID */
#endif
DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) {
case (FLASH_WORD_SIZE) AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (FLASH_WORD_SIZE) AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (FLASH_WORD_SIZE) STM_ID_M29W040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (FLASH_WORD_SIZE) AMD_ID_LV033C:
info->flash_id += FLASH_AMDLV033C;
info->sector_count = 64;
info->size = 0x00400000;
break; /* => 4 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
info->flash_id = 0;
info->sector_count = CFG_MAX_FLASH_SECT;
info->size = 0x02000000;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
/* For AMD29033C flash we need to resend the command of *
* reading flash protection for upper 8 Mb of flash */
if ( i == 32 ) {
addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
info->start[i] = (int)base + (i * 0x00020000);
info->protect[i] = 0;
}
/* issue bank reset to return to read mode */
addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0;
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
/* ? ? ? */
}
*(FLASH_WORD_SIZE *) ((int)addr) = (FLASH_WORD_SIZE) 0x00F0; /* reset bank */
return (info->size);
}
@ -391,7 +302,7 @@ int wait_for_DQ7(flash_info_t * info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr =
(FLASH_WORD_SIZE *) (info->start[sect]);
(FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0);
last = start;
@ -457,24 +368,31 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
printf("Erasing sector %p\n", addr2);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x0080;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
asm("sync");
asm("isync");
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
for (i = 0; i < 50; i++)
udelay(1000); /* wait 1 ms */
} else {
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
l_sect = sect;
/*
* Wait for each sector to complete, it's more
@ -494,6 +412,16 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
#if 0
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
wait_for_DQ7(info, l_sect);
DONE:
#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *) info->start[0];
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
@ -512,36 +440,45 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
ulong status_value = 0;
wp = (addr & ~3); /* get lower word aligned address */
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
/*print status if needed */
if ((wp >= (status_value + 0x20000))
&& (status_value < 0xFFFE0000)) {
status_value = wp;
printf("writing to sector 0x%X\n", status_value);
}
data = 0;
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
@ -580,14 +517,14 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
*/
static int write_word(flash_info_t * info, ulong dest, ulong data)
{
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
volatile vu_long *addr2 = (vu_long *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *) dest) &
if ((*((volatile FLASH_WORD_SIZE *)dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
@ -598,9 +535,18 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
(FLASH_WORD_SIZE) 0x00A0;
asm("sync");
asm("isync");
dest2[i] = data2[i];
@ -621,3 +567,6 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
return (0);
}
/*-----------------------------------------------------------------------
*/

107
board/amcc/yellowstone/init.S Normal file
View File

@ -0,0 +1,107 @@
/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ; \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
0xf0000000 must be first, before relocation SA_I must be off to use the
dcache as stack. It is patched after relocation to enable SA_I
*/
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end

155
board/amcc/yellowstone/u-boot.lds Normal file
View File

@ -0,0 +1,155 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yellowstone/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

426
board/amcc/yellowstone/yellowstone.c Normal file
View File

@ -0,0 +1,426 @@
/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
int board_early_init_f(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
mtebc(pb3ap, 0x00000000);
mtebc(pb3cr, 0x00000000);
mtebc(pb4ap, 0x00000000);
mtebc(pb4cr, 0x00000000);
mtebc(pb5ap, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
/*setup Address lines for flash sizes larger than 16Meg. */
out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
/*setup emac */
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
/*UART1 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
/*clear tmrclk divisor */
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
return 0;
}
int checkboard(void)
{
sys_info_t sysinfo;
get_sys_info(&sysinfo);
printf("Board: AMCC YELLOWSTONE\n");
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
return (0);
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
void sdram_init(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_clktr, 0x40000000); /* ?? */
mtsdram(mem_wddctr, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
*------------------------------------------------------------------*/
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_tr1, 0x8080080b); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x84000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
sdram_init();
return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
unsigned long addr;
/*--------------------------------------------------------------------------+
* Bamboo is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
u16 cmdstat;
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Bamboo is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
*
************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
}
#endif

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#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
OBJS += flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

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#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# esd ADCIOP boards
#
#TEXT_BASE = 0x00001000
ifeq ($(ramsym),1)
TEXT_BASE = 0xFBD00000
else
TEXT_BASE = 0xFFF80000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

571
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/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
/*
* Ported to XPedite1000, 1/2 mb boot flash only
* Travis B. Sawyer, <travis.sawyer@sandburst.com>
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
unsigned long flash_addr_table[512][CFG_MAX_FLASH_BANKS] = {
{0xfe000000}
};
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_word(flash_info_t * info, ulong dest, ulong data);
#define ADDR0 0xaaaa
#define ADDR1 0x5554
#define FLASH_WORD_SIZE unsigned short
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned short index = 0;
int i;
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size((vu_long *)
flash_addr_table[index][i],
&flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf
("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
total_b += flash_info[i].size;
}
/* FLASH protect Monitor */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE, 0xFFFFFFFF, &flash_info[0]);
return total_b;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t * info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_SST:
printf("SST ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMD016:
printf("AM29F016D (16 Mbit, uniform sector size)\n");
break;
case FLASH_AM040:
printf("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_SST800A:
printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
case FLASH_SST160A:
printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
printf(" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count - 1))
size = info->start[i + 1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k = 0; k < size; k++) {
if (*flash++ != 0xffffffff) {
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s%s",
info->start[i],
erased ? " E" : " ", info->protect[i] ? "RO " : " ");
}
printf("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong) addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */
udelay(10000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x00AA;
udelay(1000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = (FLASH_WORD_SIZE) 0x0055;
udelay(1000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x0090;
udelay(1000);
value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
case (FLASH_WORD_SIZE) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (FLASH_WORD_SIZE) FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (FLASH_WORD_SIZE) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
case (FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
#ifdef CONFIG_ADCIOP
value = addr2[0]; /* device ID */
debug("\ndev_code=%x\n", value);
#else
value = addr2[1]; /* device ID */
#endif
DEBUGF("\nFLASH DEVICEID: %x\n", value);
info->flash_id = 0;
info->sector_count = CFG_MAX_FLASH_SECT;
info->size = 0x02000000;
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = (int)base + (i * 0x00020000);
info->protect[i] = 0;
}
*(FLASH_WORD_SIZE *) ((int)addr) = (FLASH_WORD_SIZE) 0x00F0; /* reset bank */
return (info->size);
}
int wait_for_DQ7(flash_info_t * info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr =
(FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
(FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
printf("Erasing sector %p\n", addr2);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x0080;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
asm("sync");
asm("isync");
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
#if 0
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
wait_for_DQ7(info, l_sect);
DONE:
#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *) info->start[0];
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
ulong status_value = 0;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
/*print status if needed */
if ((wp >= (status_value + 0x20000))
&& (status_value < 0xFFFE0000)) {
status_value = wp;
printf("writing to sector 0x%X\n", status_value);
}
data = 0;
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word(flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr2 = (vu_long *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *)dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
for (i = 0; i < 4 / sizeof(FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
(FLASH_WORD_SIZE) 0x00A0;
asm("sync");
asm("isync");
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

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/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ; \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
0xf0000000 must be first, before relocation SA_I must be off to use the
dcache as stack. It is patched after relocation to enable SA_I
*/
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end

155
board/amcc/yosemite/u-boot.lds Normal file
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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yosemite/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

424
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/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
int board_early_init_f(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
mtebc(pb3ap, 0x00000000);
mtebc(pb3cr, 0x00000000);
mtebc(pb4ap, 0x00000000);
mtebc(pb4cr, 0x00000000);
mtebc(pb5ap, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
/*setup Address lines for flash sizes larger than 16Meg. */
out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
/*setup emac */
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
/*UART1 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
/*clear tmrclk divisor */
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
return 0;
}
int checkboard(void)
{
sys_info_t sysinfo;
get_sys_info(&sysinfo);
printf("Board: AMCC YOSEMITE\n");
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
return (0);
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
void sdram_init(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_clktr, 0x40000000); /* ?? */
mtsdram(mem_wddctr, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
*------------------------------------------------------------------*/
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_tr1, 0x8080080b); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x84000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
sdram_init();
return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
unsigned long addr;
/*--------------------------------------------------------------------------+
* Bamboo is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Bamboo is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
*
************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
}
#endif

117
board/bubinga405ep/bubinga405ep.c
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@ -1,117 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
long int spd_sdram (void);
#include <common.h>
#include <asm/processor.h>
int board_early_init_f (void)
{
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000010);
mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
mtdcr (uictr, 0x00000010); /* set int trigger levels */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
#if 0
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
/* CS1 */
/* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
mtebc (pb1ap, 0x02815480);
mtebc (pb1cr, 0xF0018000);
p = (unsigned int*)0xEF600708;
t = *p;
t = t | 0x00000400;
*p = t;
/* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
mtebc (pb2ap, 0x04815A80);
mtebc (pb2cr, 0xF0118000);
/* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
mtebc (pb3ap, 0x01815280);
mtebc (pb3cr, 0xF0218000);
/* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
mtebc (pb7ap, 0x01815280);
mtebc (pb7cr, 0xF0318000);
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004
*(volatile char *) (FPGA_BRDC) |= 0x1;
#endif
return 0;
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
unsigned char *s = getenv ("serial#");
puts ("Board: IBM 405EP Eval Board");
if (s != NULL) {
puts (", serial# ");
puts (s);
}
putc ('\n');
return (0);
}
/* -------------------------------------------------------------------------
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
long int initdram (int board_type)
{
long int ret;
ret = spd_sdram ();
return ret;
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: xxx MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */

44
board/bubinga405ep/bubinga405ep.h
View File

@ -1,44 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************
* FLASH Memory Map as used by TQ Monitor:
*
* Start Address Length
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
* | MON8xx code | 0x4000_0100 Reset Vector
* +-----------------------+ 0x400?_????
* | (unused) |
* +-----------------------+ 0x4001_FF00
* | Ethernet Addresses | 0x78
* +-----------------------+ 0x4001_FF78
* | (Reserved for MON8xx) | 0x44
* +-----------------------+ 0x4001_FFBC
* | Lock Address | 0x04
* +-----------------------+ 0x4001_FFC0 ^
* | Hardware Information | 0x40 | MON8xx
* +=======================+ 0x4002_0000 (sector border) -----------------
* | Autostart Header | | Applications
* | ... | v
*
*****************************************************************************/

737
board/bubinga405ep/flash.c
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@ -1,737 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
#ifdef CONFIG_ADCIOP
#define ADDR0 0x0aa9
#define ADDR1 0x0556
#define FLASH_WORD_SIZE unsigned char
#endif
#ifdef CONFIG_CPCI405
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned short
#endif
#ifdef CONFIG_WALNUT405
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
#endif
#ifdef CONFIG_BUBINGA405EP
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
#endif
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
/* Monitor protection ON by default */
(void) flash_protect (FLAG_PROTECT_SET,
FLASH_BASE0_PRELIM,
FLASH_BASE0_PRELIM + CFG_MONITOR_LEN - 1,
&flash_info[0]);
/* Also protect sector containing initial power-up instruction */
(void) flash_protect (FLAG_PROTECT_SET,
0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
size_b1 = 0;
flash_info[0].size = size_b0;
}
/* 2 banks */
else {
size_b1 = flash_get_size ((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr (ebccfga, pb0cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
}
if (size_b0) {
mtdcr (ebccfga, pb1cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
}
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
flash_get_offsets (base_b0, &flash_info[0]);
/* monitor protection ON by default */
(void) flash_protect (FLAG_PROTECT_SET,
base_b0 + size_b0 - CFG_MONITOR_LEN,
base_b0 + size_b0 - 1, &flash_info[0]);
/* Also protect sector containing initial power-up instruction */
/* (flash_protect() checks address range - other call ignored) */
(void) flash_protect (FLAG_PROTECT_SET,
0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
(void) flash_protect (FLAG_PROTECT_SET,
0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
flash_get_offsets (base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void) flash_protect (FLAG_PROTECT_SET,
base_b1 + size_b1 - CFG_MONITOR_LEN,
base_b1 + size_b1 - 1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void) flash_protect (FLAG_PROTECT_CLEAR,
base_b0 + size_b0 - CFG_MONITOR_LEN,
base_b0 + size_b0 - 1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
} /* else 2 banks */
return (size_b0 + size_b1);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count - 1))
size = info->start[i + 1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *) info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k = 0; k < size; k++) {
if (*flash++ != 0xffffffff) {
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf ("\n ");
#if 0 /* test-only */
printf (" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " "
#else
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ", info->protect[i] ? "RO " : " "
#endif
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long * addr, flash_info_t * info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong) addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
/* Write auto select command: read Manufacturer ID */
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
#ifdef CONFIG_ADCIOP
value = addr2[2];
#else
value = addr2[0];
#endif
switch (value) {
case (FLASH_WORD_SIZE) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (FLASH_WORD_SIZE) FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (FLASH_WORD_SIZE) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
#ifdef CONFIG_ADCIOP
value = addr2[0]; /* device ID */
/* printf("\ndev_code=%x\n", value); */
#else
value = addr2[1]; /* device ID */
#endif
switch (value) {
case (FLASH_WORD_SIZE) AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (FLASH_WORD_SIZE) AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (FLASH_WORD_SIZE) AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (FLASH_WORD_SIZE) AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE) AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE) AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (FLASH_WORD_SIZE) AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
#if 0 /* enable when device IDs are available */
case (FLASH_WORD_SIZE) AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (FLASH_WORD_SIZE) AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
#endif
case (FLASH_WORD_SIZE) SST_ID_xF800A:
info->flash_id += FLASH_SST800A;
info->sector_count = 16;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE) SST_ID_xF160A:
info->flash_id += FLASH_SST160A;
info->sector_count = 32;
info->size = 0x00200000;
break; /* => 2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
#ifdef CONFIG_ADCIOP
addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
info->protect[i] = addr2[4] & 1;
#else
addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
#endif
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
#if 0 /* test-only */
#ifdef CONFIG_ADCIOP
addr2 = (volatile unsigned char *) info->start[0];
addr2[ADDR0] = 0xAA;
addr2[ADDR1] = 0x55;
addr2[ADDR0] = 0xF0; /* reset bank */
#else
addr2 = (FLASH_WORD_SIZE *) info->start[0];
*addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
#endif
#else /* test-only */
addr2 = (FLASH_WORD_SIZE *) info->start[0];
*addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
#endif /* test-only */
}
return (info->size);
}
int wait_for_DQ7 (flash_info_t * info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer (0);
last = 0;
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
printf ("Erasing sector %p\n", addr2); /* CLH */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
for (i = 0; i < 50; i++)
udelay (1000); /* wait 1 ms */
} else {
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7 (info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
#if 0
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
wait_for_DQ7 (info, l_sect);
DONE:
#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *) info->start[0];
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_word (info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *) dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

55
board/bubinga405ep/init.S
View File

@ -1,55 +0,0 @@
/*------------------------------------------------------------------------------+ */
/* */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
/* copying it, modifying it, compiling it, and redistributing it either */
/* with or without modifications. No license under IBM patents or */
/* patent applications is to be implied by the copyright license. */
/* */
/* Any user of this software should understand that IBM cannot provide */
/* technical support for this software and will not be responsible for */
/* any consequences resulting from the use of this software. */
/* */
/* Any person who transfers this source code or any derivative work */
/* must include the IBM copyright notice, this paragraph, and the */
/* preceding two paragraphs in the transferred software. */
/* */
/* COPYRIGHT I B M CORPORATION 1995 */
/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
/*------------------------------------------------------------------------------- */
/*----------------------------------------------------------------------------- */
/* Function: ext_bus_cntlr_init */
/* Description: Initializes the External Bus Controller for the external */
/* peripherals. IMPORTANT: For pass1 this code must run from */
/* cache since you can not reliably change a peripheral banks */
/* timing register (pbxap) while running code from that bank. */
/* For ex., since we are running from ROM on bank 0, we can NOT */
/* execute the code that modifies bank 0 timings from ROM, so */
/* we run it from cache. */
/* Bank 0 - Flash and SRAM */
/* Bank 1 - NVRAM/RTC */
/* Bank 2 - Keyboard/Mouse controller */
/* Bank 3 - IR controller */
/* Bank 4 - not used */
/* Bank 5 - not used */
/* Bank 6 - not used */
/* Bank 7 - FPGA registers */
/*----------------------------------------------------------------------------- */
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
/*----------------------------------------------------------------------------- */
/* Function: sdram_init */
/* Description: Dummy implementation here - done in C later */
/*----------------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr

146
board/bubinga405ep/u-boot.lds.debug
View File

@ -1,146 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
/*
cpu/ppc4xx/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
*/
cpu/ppc4xx/start.o (.text)
board/bubinga405ep/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
board/dave/PPChameleonEVB/PPChameleonEVB.c
View File

@ -261,7 +261,7 @@ nand_init(void)
debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
totlen += nand_probe (CFG_NAND1_BASE);
printf ("%4lu MB\n", totlen >>20);
printf ("%3lu MB\n", totlen >>20);
}
#endif

44
board/ebony/ebony.h
View File

@ -1,44 +0,0 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************
* FLASH Memory Map as used by TQ Monitor:
*
* Start Address Length
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
* | MON8xx code | 0x4000_0100 Reset Vector
* +-----------------------+ 0x400?_????
* | (unused) |
* +-----------------------+ 0x4001_FF00
* | Ethernet Addresses | 0x78
* +-----------------------+ 0x4001_FF78
* | (Reserved for MON8xx) | 0x44
* +-----------------------+ 0x4001_FFBC
* | Lock Address | 0x04
* +-----------------------+ 0x4001_FFC0 ^
* | Hardware Information | 0x40 | MON8xx
* +=======================+ 0x4002_0000 (sector border) -----------------
* | Autostart Header | | Applications
* | ... | v
*
*****************************************************************************/

743
board/ebony/flash.c
View File

@ -1,743 +0,0 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
{0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
{0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
{0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
{0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
{0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
};
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
#if 0
static void flash_get_offsets (ulong base, flash_info_t *info);
#endif
#ifdef CONFIG_ADCIOP
#define ADDR0 0x0aa9
#define ADDR1 0x0556
#define FLASH_WORD_SIZE unsigned char
#endif
#ifdef CONFIG_CPCI405
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned short
#endif
#ifdef CONFIG_WALNUT405
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
#endif
#ifdef CONFIG_EBONY
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
#endif
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void) {
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned char * fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned char switch_status;
unsigned short index = 0;
int i;
/* read FPGA base register FPGA_REG0 */
switch_status = *fpga_base;
/* check the bitmap of switch status */
if (switch_status & BOOT_SMALL_FLASH) {
index += BOOT_SMALL_FLASH_VAL;
}
if (switch_status & FLASH_ONBD_N) {
index += FLASH_ONBD_N_VAL;
}
if (switch_status & FLASH_SRAM_SEL) {
index += FLASH_SRAM_SEL_VAL;
}
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size(
(vu_long *)flash_addr_table[index][i], &flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i]<<20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
total_b += flash_info[i].size;
}
return total_b;
}
/*-----------------------------------------------------------------------
*/
#if 0
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040) ||
(info->flash_id == FLASH_AMD016)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
}
#endif /* 0 */
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n");
break;
case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
/* Write auto select command: read Manufacturer ID */
udelay(10000);
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
udelay(1000);
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
udelay(1000);
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
udelay(1000);
#ifdef CONFIG_ADCIOP
value = addr2[2];
#else
value = addr2[0];
#endif
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
case (FLASH_WORD_SIZE)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (FLASH_WORD_SIZE)FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (FLASH_WORD_SIZE)SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
case (FLASH_WORD_SIZE)STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
#ifdef CONFIG_ADCIOP
value = addr2[0]; /* device ID */
debug ("\ndev_code=%x\n", value);
#else
value = addr2[1]; /* device ID */
#endif
DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) {
case (FLASH_WORD_SIZE)AMD_ID_F016D:
info->flash_id += FLASH_AMD016;
info->sector_count = 32;
info->size = 0x00200000;
break; /* => 2 MB */
case (FLASH_WORD_SIZE)STM_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (FLASH_WORD_SIZE)AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (FLASH_WORD_SIZE)AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
#if 0 /* enable when device IDs are available */
case (FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
#endif
case (FLASH_WORD_SIZE)SST_ID_xF800A:
info->flash_id += FLASH_SST800A;
info->sector_count = 16;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)SST_ID_xF160A:
info->flash_id += FLASH_SST160A;
info->sector_count = 32;
info->size = 0x00200000;
break; /* => 2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040) ||
(info->flash_id == FLASH_AMD016)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
#ifdef CONFIG_ADCIOP
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
info->protect[i] = addr2[4] & 1;
#else
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
#endif
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
#if 0 /* test-only */
#ifdef CONFIG_ADCIOP
addr2 = (volatile unsigned char *)info->start[0];
addr2[ADDR0] = 0xAA;
addr2[ADDR1] = 0x55;
addr2[ADDR0] = 0xF0; /* reset bank */
#else
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
#endif
#else /* test-only */
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
#endif /* test-only */
}
return (info->size);
}
int wait_for_DQ7(flash_info_t *info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
start = get_timer (0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
printf("Erasing sector %p\n", addr2);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
for (i=0; i<50; i++)
udelay(1000); /* wait 1 ms */
} else {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
#if 0
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
wait_for_DQ7(info, l_sect);
DONE:
#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *)info->start[0];
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *) dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

135
board/ebony/u-boot.lds.debug
View File

@ -1,135 +0,0 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
ppc/extable.o (.text)
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

32
board/funkwerk/vovpn-gw/vovpn-gw.c
View File

@ -208,22 +208,22 @@ void reset_phy (void)
}
static unsigned long UPMATable[] = {
0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, //Words 0 to 3
0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, //Words 4 to 7
0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 8 to 11
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 12 to 15
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 16 to 19
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23
0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, //Words 24 to 27
0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 28 to 31
0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, //Words 32 to 35
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 36 to 39
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47
0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 48 to 51
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59
0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 //Words 60 to 63
0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
};
int board_early_init_f (void)

144
board/ocotea/u-boot.lds.debug
View File

@ -1,144 +0,0 @@
/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/ocotea/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/440gx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

95
board/pm520/flash.c
View File

@ -75,6 +75,8 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info);
static int write_data (flash_info_t *info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t *info);
void inline spin_wheel (void);
static void flash_sync_real_protect (flash_info_t * info);
static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
/*-----------------------------------------------------------------------
*/
@ -101,6 +103,9 @@ unsigned long flash_init (void)
break;
}
size += flash_info[i].size;
/* get the h/w and s/w protection status in sync */
flash_sync_real_protect(&flash_info[i]);
}
/* Protect monitor and environment sectors
@ -138,7 +143,6 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
@ -270,6 +274,83 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
}
/*
* This function gets the u-boot flash sector protection status
* (flash_info_t.protect[]) in sync with the sector protection
* status stored in hardware.
*/
static void flash_sync_real_protect (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F128J3A:
case FLASH_28F640J3A:
case FLASH_28F320J3A:
for (i = 0; i < info->sector_count; ++i) {
info->protect[i] = intel_sector_protected(info, i);
}
break;
default:
/* no h/w protect support */
break;
}
}
/*
* checks if "sector" in bank "info" is protected. Should work on intel
* strata flash chips 28FxxxJ3x in 8-bit mode.
* Returns 1 if sector is protected (or timed-out while trying to read
* protection status), 0 if it is not.
*/
static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
{
FPWV *addr;
FPWV *lock_conf_addr;
ulong start;
unsigned char ret;
/*
* first, wait for the WSM to be finished. The rationale for
* waiting for the WSM to become idle for at most
* CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
* because of: (1) erase, (2) program or (3) lock bit
* configuration. So we just wait for the longest timeout of
* the (1)-(3), i.e. the erase timeout.
*/
/* wait at least 35ns (W12) before issuing Read Status Register */
udelay(1);
addr = (FPWV *) info->start[sector];
*addr = (FPW) INTEL_STATUS;
start = get_timer (0);
while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
*addr = (FPW) INTEL_RESET; /* restore read mode */
printf("WSM busy too long, can't get prot status\n");
return 1;
}
}
/* issue the Read Identifier Codes command */
*addr = (FPW) INTEL_READID;
/* wait at least 35ns (W12) before reading */
udelay(1);
/* Intel example code uses offset of 2 for 16 bit flash */
lock_conf_addr = (FPWV *) info->start[sector] + 2;
ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
/* put flash back in read mode */
*addr = (FPW) INTEL_RESET;
return ret;
}
/*-----------------------------------------------------------------------
*/
@ -491,7 +572,7 @@ void inline spin_wheel (void)
* 0 - OK
* 1 - Error (timeout, voltage problems, etc.)
*/
int flash_real_protect(flash_info_t *info, long sector, int prot)
int flash_real_protect (flash_info_t *info, long sector, int prot)
{
ulong start;
int i;
@ -531,6 +612,11 @@ int flash_real_protect(flash_info_t *info, long sector, int prot)
/*
* Clear lock bit command clears all sectors lock bits, so
* we have to restore lock bits of protected sectors.
* WARNING: code below re-locks sectors only for one bank (info).
* This causes problems on boards where several banks share
* the same chip, as sectors in othere banks will be unlocked
* but not re-locked. It works fine on pm520 though, as there
* is only one chip and one bank.
*/
if (!prot)
{
@ -553,6 +639,11 @@ int flash_real_protect(flash_info_t *info, long sector, int prot)
}
}
}
/*
* get the s/w sector protection status in sync with the h/w,
* in case something went wrong during the re-locking.
*/
flash_sync_real_protect(info); /* resets flash to read mode */
}
if (flag)

729
board/walnut405/flash.c
View File

@ -1,729 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
#ifdef CONFIG_ADCIOP
#define ADDR0 0x0aa9
#define ADDR1 0x0556
#define FLASH_WORD_SIZE unsigned char
#endif
#ifdef CONFIG_CPCI405
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned short
#endif
#ifdef CONFIG_WALNUT405
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
#endif
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1)
{
/* Setup offsets */
flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
FLASH_BASE0_PRELIM,
FLASH_BASE0_PRELIM+monitor_flash_len-1,
&flash_info[0]);
size_b1 = 0 ;
flash_info[0].size = size_b0;
}
/* 2 banks */
else
{
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1)
{
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
}
if (size_b0)
{
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
flash_get_offsets (base_b0, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b0+size_b0-monitor_flash_len,
base_b0+size_b0-1,
&flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
flash_get_offsets (base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b1+size_b1-monitor_flash_len,
base_b1+size_b1-1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR,
base_b0+size_b0-monitor_flash_len,
base_b0+size_b0-1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
}/* else 2 banks */
return (size_b0 + size_b1);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)){
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf ("\n ");
#if 0 /* test-only */
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
#else
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " "
#endif
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
#ifdef CONFIG_ADCIOP
value = addr2[2];
#else
value = addr2[0];
#endif
switch (value) {
case (FLASH_WORD_SIZE)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (FLASH_WORD_SIZE)FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (FLASH_WORD_SIZE)SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
#ifdef CONFIG_ADCIOP
value = addr2[0]; /* device ID */
/* printf("\ndev_code=%x\n", value); */
#else
value = addr2[1]; /* device ID */
#endif
switch (value) {
case (FLASH_WORD_SIZE)AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */
break;
case (FLASH_WORD_SIZE)AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
#if 0 /* enable when device IDs are available */
case (FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
#endif
case (FLASH_WORD_SIZE)SST_ID_xF800A:
info->flash_id += FLASH_SST800A;
info->sector_count = 16;
info->size = 0x00100000;
break; /* => 1 MB */
case (FLASH_WORD_SIZE)SST_ID_xF160A:
info->flash_id += FLASH_SST160A;
info->sector_count = 32;
info->size = 0x00200000;
break; /* => 2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)){
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
#ifdef CONFIG_ADCIOP
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
info->protect[i] = addr2[4] & 1;
#else
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
info->protect[i] = 0;
else
info->protect[i] = addr2[2] & 1;
#endif
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
#if 0 /* test-only */
#ifdef CONFIG_ADCIOP
addr2 = (volatile unsigned char *)info->start[0];
addr2[ADDR0] = 0xAA;
addr2[ADDR1] = 0x55;
addr2[ADDR0] = 0xF0; /* reset bank */
#else
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
#endif
#else /* test-only */
addr2 = (FLASH_WORD_SIZE *)info->start[0];
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
#endif /* test-only */
}
return (info->size);
}
int wait_for_DQ7(flash_info_t *info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
start = get_timer (0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
printf("Erasing sector %p\n", addr2); /* CLH */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
for (i=0; i<50; i++)
udelay(1000); /* wait 1 ms */
} else {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
#if 0
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
wait_for_DQ7(info, l_sect);
DONE:
#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *)info->start[0];
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *) dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

99
board/walnut405/init.S
View File

@ -1,99 +0,0 @@
/*------------------------------------------------------------------------------+ */
/* */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
/* copying it, modifying it, compiling it, and redistributing it either */
/* with or without modifications. No license under IBM patents or */
/* patent applications is to be implied by the copyright license. */
/* */
/* Any user of this software should understand that IBM cannot provide */
/* technical support for this software and will not be responsible for */
/* any consequences resulting from the use of this software. */
/* */
/* Any person who transfers this source code or any derivative work */
/* must include the IBM copyright notice, this paragraph, and the */
/* preceding two paragraphs in the transferred software. */
/* */
/* COPYRIGHT I B M CORPORATION 1995 */
/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
/*------------------------------------------------------------------------------- */
/*----------------------------------------------------------------------------- */
/* Function: ext_bus_cntlr_init */
/* Description: Initializes the External Bus Controller for the external */
/* peripherals. IMPORTANT: For pass1 this code must run from */
/* cache since you can not reliably change a peripheral banks */
/* timing register (pbxap) while running code from that bank. */
/* For ex., since we are running from ROM on bank 0, we can NOT */
/* execute the code that modifies bank 0 timings from ROM, so */
/* we run it from cache. */
/* Bank 0 - Flash and SRAM */
/* Bank 1 - NVRAM/RTC */
/* Bank 2 - Keyboard/Mouse controller */
/* Bank 3 - IR controller */
/* Bank 4 - not used */
/* Bank 5 - not used */
/* Bank 6 - not used */
/* Bank 7 - FPGA registers */
/*----------------------------------------------------------------------------- */
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
bl ..getAddr
..getAddr:
mflr r3 /* get address of ..getAddr */
mtlr r4 /* restore link register */
addi r4,0,14 /* set ctr to 10; used to prefetch */
mtctr r4 /* 10 cache lines to fit this function */
/* in cache (gives us 8x10=80 instrctns) */
..ebcloop:
icbt r0,r3 /* prefetch cache line for addr in r3 */
addi r3,r3,32 /* move to next cache line */
bdnz ..ebcloop /* continue for 10 cache lines */
/*------------------------------------------------------------------- */
/* Delay to ensure all accesses to ROM are complete before changing */
/* bank 0 timings. 200usec should be enough. */
/* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
/*------------------------------------------------------------------- */
addis r3,0,0x0
ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
mtctr r3
..spinlp:
bdnz ..spinlp /* spin loop */
/*----------------------------------------------------------------------- */
/* Memory Bank 0 (Flash and SRAM) initialization */
/*----------------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addis r4,0,0x9B01
ori r4,r4,0x5480
mtdcr ebccfgd,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
mtdcr ebccfgd,r4
blr
/*----------------------------------------------------------------------------- */
/* Function: sdram_init */
/* Description: Dummy implementation here - done in C later */
/*----------------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr

135
board/walnut405/u-boot.lds.debug
View File

@ -1,135 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

133
board/walnut405/walnut405.c
View File

@ -1,133 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "walnut405.h"
#include <asm/processor.h>
#include <spd_sdram.h>
int board_early_init_f (void)
{
/*-------------------------------------------------------------------------+
| Interrupt controller setup for the Walnut board.
| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
| IRQ 16 405GP internally generated; active low; level sensitive
| IRQ 17-24 RESERVED
| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
| IRQ 27 (EXT IRQ 2) Not Used
| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
| Note for Walnut board:
| An interrupt taken for the FPGA (IRQ 25) indicates that either
| the Mouse, Keyboard, IRDA, or External Expansion caused the
| interrupt. The FPGA must be read to determine which device
| caused the interrupt. The default setting of the FPGA clears
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
/* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
mtebc (pb1ap, 0x02815480);
mtebc (pb1cr, 0xF0018000);
/* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
mtebc (pb2ap, 0x04815A80);
mtebc (pb2cr, 0xF0118000);
/* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
mtebc (pb3ap, 0x01815280);
mtebc (pb3cr, 0xF0218000);
/* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
mtebc (pb7ap, 0x01815280);
mtebc (pb7cr, 0xF0318000);
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004
*(volatile char *) (FPGA_BRDC) |= 0x1;
return 0;
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
unsigned char *s = getenv ("serial#");
unsigned char *e;
puts ("Board: ");
if (!s || strncmp (s, "WALNUT405", 9)) {
puts ("### No HW ID - assuming WALNUT405");
} else {
for (e = s; *e; ++e) {
if (*e == ' ')
break;
}
for (; s < e; ++s) {
putc (*s);
}
}
putc ('\n');
return (0);
}
/* -------------------------------------------------------------------------
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
long int initdram (int board_type)
{
return spd_sdram (0);
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: xxx MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */

44
board/walnut405/walnut405.h
View File

@ -1,44 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************
* FLASH Memory Map as used by TQ Monitor:
*
* Start Address Length
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
* | MON8xx code | 0x4000_0100 Reset Vector
* +-----------------------+ 0x400?_????
* | (unused) |
* +-----------------------+ 0x4001_FF00
* | Ethernet Addresses | 0x78
* +-----------------------+ 0x4001_FF78
* | (Reserved for MON8xx) | 0x44
* +-----------------------+ 0x4001_FFBC
* | Lock Address | 0x04
* +-----------------------+ 0x4001_FFC0 ^
* | Hardware Information | 0x40 | MON8xx
* +=======================+ 0x4002_0000 (sector border) -----------------
* | Autostart Header | | Applications
* | ... | v
*
*****************************************************************************/

10
common/cmd_bdinfo.c
View File

@ -61,13 +61,15 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#endif
print_num ("bootflags", bd->bi_bootflags );
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300)
defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300)
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300 */
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440_EP CONFIG_440_GR */
#if defined(CONFIG_CPM2)
print_str ("vco", strmhz(buf, bd->bi_vco));
print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq));
@ -78,7 +80,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq));
#endif
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300 */
#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440_EP CONFIG_440_GR */
#if defined(CONFIG_MPC8220)
print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq));
print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq));

4
common/cmd_elf.c
View File

@ -78,7 +78,7 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* ====================================================================== */
int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_WALNUT405) || \
#if defined(CONFIG_WALNUT) || \
defined(CFG_VXWORKS_MAC_PTR)
DECLARE_GLOBAL_DATA_PTR;
#endif
@ -121,7 +121,7 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* This will vary from board to board
*/
#if defined(CONFIG_WALNUT405)
#if defined(CONFIG_WALNUT)
tmp = (char *) CFG_NVRAM_BASE_ADDR + 0x500;
memcpy ((char *) tmp, (char *) &gd->bd->bi_enetaddr[3], 3);
#elif defined(CFG_VXWORKS_MAC_PTR)

2
common/lynxkdi.c
View File

@ -20,7 +20,7 @@
#if defined(CONFIG_LYNXKDI)
#include <lynxkdi.h>
#if defined(CONFIG_MPC8260)
#if defined(CONFIG_MPC8260) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
void lynxkdi_boot ( image_header_t *hdr )
{
void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep;

4
common/usb.c
View File

@ -46,7 +46,6 @@
#include <405gp_pci.h>
#endif
#undef USB_DEBUG
#ifdef USB_DEBUG
@ -523,6 +522,7 @@ int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char
if (result > 0)
break;
}
return result;
}
@ -723,6 +723,7 @@ int usb_new_device(struct usb_device *dev)
/* find the port number we're at */
if (parent) {
for (j = 0; j < parent->maxchild; j++) {
if (parent->children[j] == dev) {
port = j;
@ -956,6 +957,7 @@ static int hub_port_reset(struct usb_device *dev, int port,
return -1;
if (portstatus & USB_PORT_STAT_ENABLE) {
break;
}

2
cpu/arm920t/s3c24x0/usb_ohci.c
View File

@ -53,6 +53,7 @@
#define OHCI_USE_NPS /* force NoPowerSwitching mode */
#undef OHCI_VERBOSE_DEBUG /* not always helpful */
/* For initializing controller (mask in an HCFS mode too) */
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
@ -1219,7 +1220,6 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
return stat;
}
/*-------------------------------------------------------------------------*/
/* common code for handling submit messages - used for all but root hub */

30
cpu/ppc4xx/405gp_enet.c
View File

@ -227,7 +227,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* wait for reset */
while (mfdcr (malmcr) & MAL_CR_MMSR) {
};
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
out32 (ZMII_FER, 0);
udelay(100);
/* set RII mode */
out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#elif defined(CONFIG_440)
/* set RMII mode */
out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#endif /* CONFIG_440 */
@ -461,6 +466,18 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
else
out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
mfsdr(sdr_mfr, reg);
/* set speed */
if (speed == _100BASET) {
out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
} else {
reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
}
mtsdr(sdr_mfr, reg);
#endif
#endif
/* Enable broadcast and indvidual address */
@ -498,11 +515,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/*
* Connect interrupt service routines
*/
#if !defined(CONFIG_405EP)
/* 405EP has one EWU interrupt */
irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
#endif
irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
}
@ -993,12 +1005,6 @@ int ppc_4xx_eth_initialize (bd_t * bis)
mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
mtdcr (malier, mal_ier);
#if defined(CONFIG_405EP)
/* 405EP has one EWU interrupt */
irq_install_handler (VECNUM_EWU0,
(interrupt_handler_t *) enetInt,
dev);
#endif
/* install MAL interrupt handler */
irq_install_handler (VECNUM_MS,
(interrupt_handler_t *) enetInt,

6
cpu/ppc4xx/405gp_pci.c
View File

@ -437,7 +437,7 @@ void pci_440_init (struct pci_controller *hose)
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440_GX) || defined (CONFIG_440_EP) || defined(CONFIG_440_GR)
mfsdr(sdr_sdstp1,strap);
if ( (strap & 0x00010000) == 0 ){
printf("PCI: SDR0_STRP1[PISE] not set.\n");
@ -498,7 +498,7 @@ void pci_440_init (struct pci_controller *hose)
#if defined(CONFIG_440_GX)
out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
#else
#elif defined(PCIX0_BRDGOPT1)
out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
#endif
@ -531,7 +531,9 @@ void pci_440_init (struct pci_controller *hose)
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
#if !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
hose->last_busno = pci_hose_scan(hose);
}
}

44
cpu/ppc4xx/440gx_enet.c
View File

@ -167,6 +167,8 @@ static void ppc_440x_eth_halt (struct eth_device *dev)
/* EMAC RESET */
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
hw_p->print_speed = 1; /* print speed message again next time */
return;
}
@ -277,7 +279,9 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
unsigned short devnum;
unsigned short reg_short;
sys_info_t sysinfo;
#if defined(CONFIG_440_GX)
int ethgroup;
#endif
EMAC_440GX_HW_PST hw_p = dev->priv;
@ -289,7 +293,6 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
msr = mfmsr ();
mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
@ -320,7 +323,12 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* MAL Channel RESET */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
#endif
mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
/* wait for reset */
@ -354,7 +362,9 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
out32 (ZMII_FER, 0);
udelay (100);
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440_GX)
ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
#else
if ((devnum == 0) || (devnum == 1)) {
@ -499,6 +509,15 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
mfsdr(sdr_mfr, reg);
if (speed == 100) {
reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
} else {
reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
}
mtsdr(sdr_mfr, reg);
#endif
/* Set ZMII/RGMII speed according to the phy link speed */
reg = in32 (ZMII_SSR);
if ( (speed == 100) || (speed == 1000) )
@ -618,8 +637,12 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
mtdcr (maltxbattr, 0x0);
#if defined (CONFIG_440_EP) || defined (CONFIG_440_GR)
mtdcr (maltxctp2r, hw_p->tx);
#else
mtdcr (maltxctp1r, hw_p->tx);
#endif
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
mtdcr (malrxctp1r, hw_p->rx);
/* set RX buffer size */
@ -658,7 +681,11 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
/* Enable MAL transmit and receive channels */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
#endif
mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
/* set transmit enable & receive enable */
@ -1148,19 +1175,24 @@ static int ppc_440x_eth_rx (struct eth_device *dev)
int ppc_440x_eth_initialize (bd_t * bis)
{
static int virgin = 0;
unsigned long pfc1;
struct eth_device *dev;
int eth_num = 0;
EMAC_440GX_HW_PST hw = NULL;
#if defined(CONFIG_440_GX)
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);
pfc1 &= ~(0x01e00000);
pfc1 |= 0x01200000;
mtsdr (sdr_pfc1, pfc1);
#endif
/* set phy num and mode */
bis->bi_phynum[0] = CONFIG_PHY_ADDR;
#if defined(CONFIG_PHY1_ADDR)
bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
#endif
#if defined(CONFIG_440_GX)
bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[0] = 0;
@ -1170,6 +1202,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
#if defined (CONFIG_440_GX)
ppc_440x_eth_setup_bridge(0, bis);
#endif
#endif
for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
@ -1256,6 +1289,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
}
hw->devnum = eth_num;
hw->print_speed = 1;
sprintf (dev->name, "ppc_440x_eth%d", eth_num);
dev->priv = (void *) hw;

2
cpu/ppc4xx/Makefile
View File

@ -31,7 +31,7 @@ COBJS = 405gp_enet.o 405gp_pci.o 440gx_enet.o \
bedbug_405.o commproc.o \
cpu.o cpu_init.o i2c.o interrupts.o \
miiphy.o miiphy_440.o sdram.o serial.o \
spd_sdram.o speed.o traps.o
spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o
OBJS = $(AOBJS) $(COBJS)

44
cpu/ppc4xx/cpu.c
View File

@ -71,17 +71,17 @@ int checkcpu (void)
get_sys_info(&sys_info);
#ifdef CONFIG_405GP
puts ("IBM PowerPC 405GP");
puts ("AMCC PowerPC 405GP");
if (pvr == PVR_405GPR_RB) {
putc('r');
}
puts (" Rev. ");
#endif
#ifdef CONFIG_405CR
puts ("IBM PowerPC 405CR Rev. ");
puts ("AMCC PowerPC 405CR Rev. ");
#endif
#ifdef CONFIG_405EP
puts ("IBM PowerPC 405EP Rev. ");
puts ("AMCC PowerPC 405EP Rev. ");
#endif
switch (pvr) {
case PVR_405GP_RB:
@ -152,10 +152,10 @@ int checkcpu (void)
#endif
#if defined(CONFIG_440)
puts ("IBM PowerPC 440 G");
puts ("AMCC PowerPC 440 ");
switch(pvr) {
case PVR_440GP_RB:
puts("P Rev. B");
puts("GP Rev. B");
/* See errata 1.12: CHIP_4 */
if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
(mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
@ -167,19 +167,35 @@ int checkcpu (void)
}
break;
case PVR_440GP_RC:
puts("P Rev. C");
puts("GP Rev. C");
break;
case PVR_440GX_RA:
puts("X Rev. A");
puts("GX Rev. A");
break;
case PVR_440GX_RB:
puts("X Rev. B");
puts("GX Rev. B");
break;
case PVR_440GX_RC:
puts("X Rev. C");
puts("GX Rev. C");
break;
#if defined(CONFIG_440_GR)
case PVR_440EP_RA:
puts("GR Rev. A");
break;
case PVR_440EP_RB:
puts("GR Rev. B");
break;
#else
case PVR_440EP_RA:
puts("EP Rev. A");
break;
case PVR_440EP_RB:
puts("EP Rev. B");
break;
#endif
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
printf ("UNKNOWN (PVR=%08x)", pvr);
break;
}
#endif
@ -193,6 +209,12 @@ int checkcpu (void)
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
/*give reset to BCSR*/
*(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
#else
/*
* Initiate system reset in debug control register DBCR
*/
@ -202,6 +224,8 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#else
__asm__ __volatile__("mtspr 0x3f2, 3");
#endif
#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
return 1;
}

4
cpu/ppc4xx/cpu_init.c
View File

@ -188,7 +188,11 @@ cpu_init_f (void)
unsigned long val;
val = mfspr(tcr);
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
#endif
mtspr(tcr, val);
val = mfspr(tsr);

5
cpu/ppc4xx/interrupts.c
View File

@ -430,7 +430,10 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440 */
if (irqa[i].handler != NULL) {
/*
* print warning when replacing with a different irq vector
*/
if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) {
printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
vec, (uint) handler, (uint) irqa[i].handler);
}

13
cpu/ppc4xx/serial.c
View File

@ -269,9 +269,14 @@ int serial_tstc ()
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
#else
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#if defined(CONFIG_440_GX)
#endif
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
@ -301,14 +306,14 @@ int serial_tstc ()
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
#endif /* CONFIG_440_GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#endif /* CONFIG_440_GX */
@ -460,7 +465,7 @@ int serial_init(void)
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {

2271
cpu/ppc4xx/spd_sdram.c
View File

File diff suppressed because it is too large Load Diff

95
cpu/ppc4xx/speed.c
View File

@ -194,7 +194,96 @@ ulong get_PCI_freq (void)
#elif defined(CONFIG_440)
#if !defined(CONFIG_440_GX)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
void get_sys_info (sys_info_t *sysInfo)
{
unsigned long temp;
unsigned long reg;
unsigned long lfdiv;
unsigned long m;
unsigned long prbdv0;
/*
WARNING: ASSUMES the following:
ENG=1
PRADV0=1
PRBDV0=1
*/
/* Decode CPR0_PLLD0 for divisors */
mfclk(clk_plld, reg);
temp = (reg & PLLD_FWDVA_MASK) >> 16;
sysInfo->pllFwdDivA = temp ? temp : 16;
temp = (reg & PLLD_FWDVB_MASK) >> 8;
sysInfo->pllFwdDivB = temp ? temp: 8 ;
temp = (reg & PLLD_FBDV_MASK) >> 24;
sysInfo->pllFbkDiv = temp ? temp : 32;
lfdiv = reg & PLLD_LFBDV_MASK;
mfclk(clk_opbd, reg);
temp = (reg & OPBDDV_MASK) >> 24;
sysInfo->pllOpbDiv = temp ? temp : 4;
mfclk(clk_perd, reg);
temp = (reg & PERDV_MASK) >> 24;
sysInfo->pllExtBusDiv = temp ? temp : 8;
mfclk(clk_primbd, reg);
temp = (reg & PRBDV_MASK) >> 24;
prbdv0 = temp ? temp : 8;
mfclk(clk_spcid, reg);
temp = (reg & SPCID_MASK) >> 24;
sysInfo->pllPciDiv = temp ? temp : 4;
/* Calculate 'M' based on feedback source */
mfsdr(sdr_sdstp0, reg);
temp = (reg & PLLSYS0_SEL_MASK) >> 27;
if (temp == 0) { /* PLL output */
/* Figure which pll to use */
mfclk(clk_pllc, reg);
temp = (reg & PLLC_SRC_MASK) >> 29;
if (!temp) /* PLLOUTA */
m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
else /* PLLOUTB */
m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
}
else if (temp == 1) /* CPU output */
m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
else /* PerClk */
m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
/* Now calculate the individual clocks */
sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv;
/* Figure which timer source to use */
if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */
if (CONFIG_SYS_CLK_FREQ > temp)
sysInfo->freqTmrClk = temp;
else
sysInfo->freqTmrClk = CONFIG_SYS_CLK_FREQ;
}
else /* Internal clock */
sysInfo->freqTmrClk = sysInfo->freqProcessor;
}
/********************************************
* get_PCI_freq
* return PCI bus freq in Hz
*********************************************/
ulong get_PCI_freq (void)
{
sys_info_t sys_info;
get_sys_info (&sys_info);
return sys_info.freqPCI;
}
#elif !defined(CONFIG_440_GX)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
@ -220,8 +309,8 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
sysInfo->freqPLB >>= 1;
if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
sysInfo->freqPLB >>= 1;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;

39
cpu/ppc4xx/start.S
View File

@ -344,7 +344,7 @@ _start:
lis r1,0x0002 /* set CE bit (Critical Exceptions) */
ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
mtmsr r1 /* change MSR */
#else
#elif !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
bl __440gx_msr_set
b __440gx_msr_continue
@ -377,6 +377,21 @@ __440gx_msr_continue:
/* Setup the internal SRAM */
/*----------------------------------------------------------------*/
li r0,0
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
/* Clear Dcache to use as RAM */
lis r3,CFG_INIT_RAM_ADDR@h
li r4,CFG_INIT_RAM_END@l
rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31
beq ..d_ran
addi r5,r5,0x0001
..d_ran:
mtctr r5
..d_ag:
dcbz r0,r3
addi r3,r3,32
bdnz ..d_ag
#else
#if defined (CONFIG_440_GX)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
@ -407,6 +422,7 @@ __440gx_msr_continue:
#else
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
#endif
#endif
/*----------------------------------------------------------------*/
@ -957,7 +973,7 @@ invalidate_icache:
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
#else
@ -983,7 +999,7 @@ flush_dcache:
mtdccr r10
/* do loop for # of congruence classes. */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
@ -1210,6 +1226,15 @@ ppcSync:
*/
.globl relocate_code
relocate_code:
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
addi r1,r0,0x0000 /* Tlb entry #0 */
tlbre r0,r1,0x0002 /* Read contents */
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */
isync
#endif
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Init Data pointer */
mr r10, r5 /* Save copy of Destination Address */
@ -1433,7 +1458,7 @@ trap_reloc:
#ifdef CONFIG_405EP
ppc405ep_init:
#ifdef CONFIG_BUBINGA405EP
#ifdef CONFIG_BUBINGA
/*
* Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
* function) to support FPGA and NVRAM accesses below.
@ -1513,7 +1538,7 @@ ppc405ep_init:
#endif
addi r3,0,CPC0_PCI_HOST_CFG_EN
#ifdef CONFIG_BUBINGA405EP
#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
! Check FPGA for PCI internal/external arbitration
@ -1548,7 +1573,7 @@ ppc405ep_init:
/* and CPU has been reset */
/* so skip to next section */
#ifdef CONFIG_BUBINGA405EP
#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
! Read NVRAM to get value to write in PLLMR.
@ -1583,7 +1608,7 @@ ppc405ep_init:
cmpi cr0,0,r5,1 /* See if PLL is locked */
beq pll_write
..no_pllset:
#endif /* CONFIG_BUBINGA405EP */
#endif /* CONFIG_BUBINGA */
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */

1642
cpu/ppc4xx/usb_ohci.c Normal file
View File

File diff suppressed because it is too large Load Diff

410
cpu/ppc4xx/usb_ohci.h Normal file
View File

@ -0,0 +1,410 @@
/*
* URB OHCI HCD (Host Controller Driver) for USB.
*
* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
* (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
*
* usb-ohci.h
*/
static int cc_to_error[16] = {
/* mapping of the OHCI CC status to error codes */
/* No Error */ 0,
/* CRC Error */ USB_ST_CRC_ERR,
/* Bit Stuff */ USB_ST_BIT_ERR,
/* Data Togg */ USB_ST_CRC_ERR,
/* Stall */ USB_ST_STALLED,
/* DevNotResp */ -1,
/* PIDCheck */ USB_ST_BIT_ERR,
/* UnExpPID */ USB_ST_BIT_ERR,
/* DataOver */ USB_ST_BUF_ERR,
/* DataUnder */ USB_ST_BUF_ERR,
/* reservd */ -1,
/* reservd */ -1,
/* BufferOver */ USB_ST_BUF_ERR,
/* BuffUnder */ USB_ST_BUF_ERR,
/* Not Access */ -1,
/* Not Access */ -1
};
/* ED States */
#define ED_NEW 0x00
#define ED_UNLINK 0x01
#define ED_OPER 0x02
#define ED_DEL 0x04
#define ED_URB_DEL 0x08
/* usb_ohci_ed */
struct ed {
__u32 hwINFO;
__u32 hwTailP;
__u32 hwHeadP;
__u32 hwNextED;
struct ed *ed_prev;
__u8 int_period;
__u8 int_branch;
__u8 int_load;
__u8 int_interval;
__u8 state;
__u8 type;
__u16 last_iso;
struct ed *ed_rm_list;
struct usb_device *usb_dev;
__u32 unused[3];
} __attribute((aligned(16)));
typedef struct ed ed_t;
/* TD info field */
#define TD_CC 0xf0000000
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
#define TD_EC 0x0C000000
#define TD_T 0x03000000
#define TD_T_DATA0 0x02000000
#define TD_T_DATA1 0x03000000
#define TD_T_TOGGLE 0x00000000
#define TD_R 0x00040000
#define TD_DI 0x00E00000
#define TD_DI_SET(X) (((X) & 0x07)<< 21)
#define TD_DP 0x00180000
#define TD_DP_SETUP 0x00000000
#define TD_DP_IN 0x00100000
#define TD_DP_OUT 0x00080000
#define TD_ISO 0x00010000
#define TD_DEL 0x00020000
/* CC Codes */
#define TD_CC_NOERROR 0x00
#define TD_CC_CRC 0x01
#define TD_CC_BITSTUFFING 0x02
#define TD_CC_DATATOGGLEM 0x03
#define TD_CC_STALL 0x04
#define TD_DEVNOTRESP 0x05
#define TD_PIDCHECKFAIL 0x06
#define TD_UNEXPECTEDPID 0x07
#define TD_DATAOVERRUN 0x08
#define TD_DATAUNDERRUN 0x09
#define TD_BUFFEROVERRUN 0x0C
#define TD_BUFFERUNDERRUN 0x0D
#define TD_NOTACCESSED 0x0F
#define MAXPSW 1
struct td {
__u32 hwINFO;
__u32 hwCBP; /* Current Buffer Pointer */
__u32 hwNextTD; /* Next TD Pointer */
__u32 hwBE; /* Memory Buffer End Pointer */
__u16 hwPSW[MAXPSW];
__u8 unused;
__u8 index;
struct ed *ed;
struct td *next_dl_td;
struct usb_device *usb_dev;
int transfer_len;
__u32 data;
__u32 unused2[2];
} __attribute((aligned(32)));
typedef struct td td_t;
#define OHCI_ED_SKIP (1 << 14)
/*
* The HCCA (Host Controller Communications Area) is a 256 byte
* structure defined in the OHCI spec. that the host controller is
* told the base address of. It must be 256-byte aligned.
*/
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca {
__u32 int_table[NUM_INTS]; /* Interrupt ED table */
#if defined(CONFIG_MPC5200)
__u16 pad1; /* set to 0 on each frame_no change */
__u16 frame_no; /* current frame number */
#else
__u16 frame_no; /* current frame number */
__u16 pad1; /* set to 0 on each frame_no change */
#endif
__u32 done_head; /* info returned for an interrupt */
u8 reserved_for_hc[116];
} __attribute((aligned(256)));
/*
* Maximum number of root hub ports.
*/
#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
/*
* This is the structure of the OHCI controller's memory mapped I/O
* region. This is Memory Mapped I/O. You must use the readl() and
* writel() macros defined in asm/io.h to access these!!
*/
struct ohci_regs {
/* control and status registers */
__u32 revision;
__u32 control;
__u32 cmdstatus;
__u32 intrstatus;
__u32 intrenable;
__u32 intrdisable;
/* memory pointers */
__u32 hcca;
__u32 ed_periodcurrent;
__u32 ed_controlhead;
__u32 ed_controlcurrent;
__u32 ed_bulkhead;
__u32 ed_bulkcurrent;
__u32 donehead;
/* frame counters */
__u32 fminterval;
__u32 fmremaining;
__u32 fmnumber;
__u32 periodicstart;
__u32 lsthresh;
/* Root hub ports */
struct ohci_roothub_regs {
__u32 a;
__u32 b;
__u32 status;
__u32 portstatus[MAX_ROOT_PORTS];
} roothub;
} __attribute((aligned(32)));
/* OHCI CONTROL AND STATUS REGISTER MASKS */
/*
* HcControl (control) register masks
*/
#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
/* pre-shifted values for HCFS */
# define OHCI_USB_RESET (0 << 6)
# define OHCI_USB_RESUME (1 << 6)
# define OHCI_USB_OPER (2 << 6)
# define OHCI_USB_SUSPEND (3 << 6)
/*
* HcCommandStatus (cmdstatus) register masks
*/
#define OHCI_HCR (1 << 0) /* host controller reset */
#define OHCI_CLF (1 << 1) /* control list filled */
#define OHCI_BLF (1 << 2) /* bulk list filled */
#define OHCI_OCR (1 << 3) /* ownership change request */
#define OHCI_SOC (3 << 16) /* scheduling overrun count */
/*
* masks used with interrupt registers:
* HcInterruptStatus (intrstatus)
* HcInterruptEnable (intrenable)
* HcInterruptDisable (intrdisable)
*/
#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
#define OHCI_INTR_SF (1 << 2) /* start frame */
#define OHCI_INTR_RD (1 << 3) /* resume detect */
#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
#define OHCI_INTR_OC (1 << 30) /* ownership change */
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
/* Virtual Root HUB */
struct virt_root_hub {
int devnum; /* Address of Root Hub endpoint */
void *dev; /* was urb */
void *int_addr;
int send;
int interval;
};
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
/* destination of request */
#define RH_INTERFACE 0x01
#define RH_ENDPOINT 0x02
#define RH_OTHER 0x03
#define RH_CLASS 0x20
#define RH_VENDOR 0x40
/* Requests: bRequest << 8 | bmRequestType */
#define RH_GET_STATUS 0x0080
#define RH_CLEAR_FEATURE 0x0100
#define RH_SET_FEATURE 0x0300
#define RH_SET_ADDRESS 0x0500
#define RH_GET_DESCRIPTOR 0x0680
#define RH_SET_DESCRIPTOR 0x0700
#define RH_GET_CONFIGURATION 0x0880
#define RH_SET_CONFIGURATION 0x0900
#define RH_GET_STATE 0x0280
#define RH_GET_INTERFACE 0x0A80
#define RH_SET_INTERFACE 0x0B00
#define RH_SYNC_FRAME 0x0C80
/* Our Vendor Specific Request */
#define RH_SET_EP 0x2000
/* Hub port features */
#define RH_PORT_CONNECTION 0x00
#define RH_PORT_ENABLE 0x01
#define RH_PORT_SUSPEND 0x02
#define RH_PORT_OVER_CURRENT 0x03
#define RH_PORT_RESET 0x04
#define RH_PORT_POWER 0x08
#define RH_PORT_LOW_SPEED 0x09
#define RH_C_PORT_CONNECTION 0x10
#define RH_C_PORT_ENABLE 0x11
#define RH_C_PORT_SUSPEND 0x12
#define RH_C_PORT_OVER_CURRENT 0x13
#define RH_C_PORT_RESET 0x14
/* Hub features */
#define RH_C_HUB_LOCAL_POWER 0x00
#define RH_C_HUB_OVER_CURRENT 0x01
#define RH_DEVICE_REMOTE_WAKEUP 0x00
#define RH_ENDPOINT_STALL 0x01
#define RH_ACK 0x01
#define RH_REQ_ERR -1
#define RH_NACK 0x00
/* OHCI ROOT HUB REGISTER MASKS */
/* roothub.portstatus [i] bits */
#define RH_PS_CCS 0x00000001 /* current connect status */
#define RH_PS_PES 0x00000002 /* port enable status */
#define RH_PS_PSS 0x00000004 /* port suspend status */
#define RH_PS_POCI 0x00000008 /* port over current indicator */
#define RH_PS_PRS 0x00000010 /* port reset status */
#define RH_PS_PPS 0x00000100 /* port power status */
#define RH_PS_LSDA 0x00000200 /* low speed device attached */
#define RH_PS_CSC 0x00010000 /* connect status change */
#define RH_PS_PESC 0x00020000 /* port enable status change */
#define RH_PS_PSSC 0x00040000 /* port suspend status change */
#define RH_PS_OCIC 0x00080000 /* over current indicator change */
#define RH_PS_PRSC 0x00100000 /* port reset status change */
/* roothub.status bits */
#define RH_HS_LPS 0x00000001 /* local power status */
#define RH_HS_OCI 0x00000002 /* over current indicator */
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
#define RH_HS_LPSC 0x00010000 /* local power status change */
#define RH_HS_OCIC 0x00020000 /* over current indicator change */
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
/* roothub.b masks */
#define RH_B_DR 0x0000ffff /* device removable flags */
#define RH_B_PPCM 0xffff0000 /* port power control mask */
/* roothub.a masks */
#define RH_A_NDP (0xff << 0) /* number of downstream ports */
#define RH_A_PSM (1 << 8) /* power switching mode */
#define RH_A_NPS (1 << 9) /* no power switching */
#define RH_A_DT (1 << 10) /* device type (mbz) */
#define RH_A_OCPM (1 << 11) /* over current protection mode */
#define RH_A_NOCP (1 << 12) /* no over current protection */
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
/* urb */
#define N_URB_TD 48
typedef struct {
ed_t *ed;
__u16 length; /* number of tds associated with this request */
__u16 td_cnt; /* number of tds already serviced */
int state;
unsigned long pipe;
int actual_length;
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
} urb_priv_t;
#define URB_DEL 1
/*
* This is the full ohci controller description
*
* Note how the "proper" USB information is just
* a subset of what the full implementation needs. (Linus)
*/
typedef struct ohci {
struct ohci_hcca *hcca; /* hcca */
/*dma_addr_t hcca_dma; */
int irq;
int disabled; /* e.g. got a UE, we're hung */
int sleeping;
unsigned long flags; /* for HC bugs */
struct ohci_regs *regs; /* OHCI controller's memory */
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t *ed_bulktail; /* last endpoint of bulk list */
ed_t *ed_controltail; /* last endpoint of control list */
int intrstatus;
__u32 hc_control; /* copy of the hc control reg */
struct usb_device *dev[32];
struct virt_root_hub rh;
const char *slot_name;
} ohci_t;
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
struct ohci_device {
ed_t ed[NUM_EDS];
int ed_cnt;
};
/* hcd */
/* endpoint */
static int ep_link(ohci_t * ohci, ed_t * ed);
static int ep_unlink(ohci_t * ohci, ed_t * ed);
static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
/*-------------------------------------------------------------------------*/
/* we need more TDs than EDs */
#define NUM_TD 64
/* +1 so we can align the storage */
td_t gtd[NUM_TD + 1];
/* pointers to aligned storage */
td_t *ptd;
/* TDs ... */
static inline struct td *td_alloc(struct usb_device *usb_dev)
{
int i;
struct td *td;
td = NULL;
for (i = 0; i < NUM_TD; i++) {
if (ptd[i].usb_dev == NULL) {
td = &ptd[i];
td->usb_dev = usb_dev;
break;
}
}
return td;
}
static inline void ed_free(struct ed *ed)
{
ed->usb_dev = NULL;
}

214
cpu/ppc4xx/usbdev.c Normal file
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@ -0,0 +1,214 @@
/*USB 1.1,2.0 device*/
#include <common.h>
#include <asm/processor.h>
#ifdef CONFIG_440_EP
#include <usb.h>
#include "usbdev.h"
#include "vecnum.h"
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
unsigned char set_value = -1;
void process_endpoints(unsigned short usb2d0_intrin)
{
/*will hold the packet received */
struct usb_device_descriptor usb_device_packet;
struct usb_config_descriptor usb_config_packet;
struct usb_string_descriptor usb_string_packet;
struct devrequest setup_packet;
unsigned int *setup_packet_pt;
unsigned char *packet_pt;
int temp, temp1;
int i;
/*printf("{USB device} - endpoint 0x%X \n", usb2d0_intrin); */
/*set usb address, seems to not work unless it is done in the next
interrupt, so that is why it is done this way */
if (set_value != -1)
*(unsigned char *)USB2D0_FADDR_8 = set_value;
/*endpoint 1 */
if (usb2d0_intrin & 0x01) {
setup_packet_pt = (unsigned int *)&setup_packet;
/*copy packet */
setup_packet_pt[0] = *(unsigned int *)USB2D0_FIFO_0;
setup_packet_pt[1] = *(unsigned int *)USB2D0_FIFO_0;
temp = *(unsigned int *)USB2D0_FIFO_0;
temp1 = *(unsigned int *)USB2D0_FIFO_0;
/*do some swapping */
setup_packet.value = swap_16(setup_packet.value);
setup_packet.index = swap_16(setup_packet.index);
setup_packet.length = swap_16(setup_packet.length);
/*clear rx packet */
*(unsigned short *)USB2D0_INCSR0_8 = 0x48;
/*printf("0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", setup_packet.requesttype,
setup_packet.request, setup_packet.value,
setup_packet.index, setup_packet.length, temp, temp1 ); */
switch (setup_packet.request) {
case USB_REQ_GET_DESCRIPTOR:
switch (setup_packet.value >> 8) {
case USB_DT_DEVICE:
/*create packet */
usb_device_packet.bLength = 18;
usb_device_packet.bDescriptorType =
USB_DT_DEVICE;
#ifdef USB_2_0_DEVICE
usb_device_packet.bcdUSB = swap_16(0x200);
#else
usb_device_packet.bcdUSB = swap_16(0x110);
#endif
usb_device_packet.bDeviceClass = 0xff;
usb_device_packet.bDeviceSubClass = 0;
usb_device_packet.bDeviceProtocol = 0;
usb_device_packet.bMaxPacketSize0 = 32;
usb_device_packet.idVendor = swap_16(1);
usb_device_packet.idProduct = swap_16(2);
usb_device_packet.bcdDevice = swap_16(0x300);
usb_device_packet.iManufacturer = 1;
usb_device_packet.iProduct = 1;
usb_device_packet.iSerialNumber = 1;
usb_device_packet.bNumConfigurations = 1;
/*put packet in fifo */
packet_pt = (unsigned char *)&usb_device_packet;
break;
case USB_DT_CONFIG:
/*create packet */
usb_config_packet.bLength = 9;
usb_config_packet.bDescriptorType =
USB_DT_CONFIG;
usb_config_packet.wTotalLength = swap_16(25);
usb_config_packet.bNumInterfaces = 1;
usb_config_packet.bConfigurationValue = 1;
usb_config_packet.iConfiguration = 0;
usb_config_packet.bmAttributes = 0x40;
usb_config_packet.MaxPower = 0;
/*put packet in fifo */
packet_pt = (unsigned char *)&usb_config_packet;
break;
case USB_DT_STRING:
/*create packet */
usb_string_packet.bLength = 2;
usb_string_packet.bDescriptorType =
USB_DT_STRING;
usb_string_packet.wData[0] = 0x0094;
/*put packet in fifo */
packet_pt = (unsigned char *)&usb_string_packet;
break;
}
/*put packet in fifo */
for (i = 0; i < (setup_packet.length); i++) {
*(unsigned char *)USB2D0_FIFO_0 = packet_pt[i];
}
/*give tx command */
*(unsigned short *)USB2D0_INCSR0_8 = 0x0a;
break;
case USB_REQ_SET_ADDRESS:
/*copy usb address */
set_value = setup_packet.value;
break;
}
}
}
void process_other(unsigned char usb2d0_intrusb)
{
/*check for sof */
if (usb2d0_intrusb & 0x08) {
/*printf("{USB device} - sof detected\n"); */
}
/*check for reset */
if (usb2d0_intrusb & 0x04) {
/*printf("{USB device} - reset detected\n"); */
/*copy usb address of zero, need to do this when usb reset */
set_value = 0;
}
if (usb2d0_intrusb & 0x02) {
/*printf("{USB device} - resume detected\n"); */
}
if (usb2d0_intrusb & 0x01) {
/*printf("{USB device} - suspend detected\n"); */
}
}
int usbInt(void)
{
/*Must read these 2 registers and use values to clear interrupts. If you
do not read them then the interrupt will not be cleared. If you do not
use the variable the optimizer will not do a read. */
volatile unsigned short usb2d0_intrin =
*(unsigned short *)USB2D0_INTRIN_16;
volatile unsigned char usb2d0_intrusb =
*(unsigned char *)USB2D0_INTRUSB_8;
/*check if there was an endpoint interrupt */
if (usb2d0_intrin != 0) {
process_endpoints(usb2d0_intrin);
}
/*check for other interrupts */
if (usb2d0_intrusb != 0) {
process_other(usb2d0_intrusb);
}
return 0;
}
void usb_dev_init()
{
#ifdef USB_2_0_DEVICE
printf("USB 2.0 Device init\n");
/*select 2.0 device */
mtsdr(sdr_usb0, 0x0); /* 2.0 */
/*usb dev init */
*(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */
#else
printf("USB 1.1 Device init\n");
/*select 1.1 device */
mtsdr(sdr_usb0, 0x2); /* 1.1 */
/*usb dev init */
*(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */
#endif
/*enable interrupts */
*(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f;
irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt,
NULL);
}
#endif /*CONFIG_440_EP */

31
cpu/ppc4xx/usbdev.h Normal file
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@ -0,0 +1,31 @@
#include <config.h>
/*Common Registers*/
#define USB2D0_INTRIN_16 (CFG_USB_DEVICE | 0x100)
#define USB2D0_POWER_8 (CFG_USB_DEVICE | 0x102)
#define USB2D0_FADDR_8 (CFG_USB_DEVICE | 0x103)
#define USB2D0_INTRINE_16 (CFG_USB_DEVICE | 0x104)
#define USB2D0_INTROUT_16 (CFG_USB_DEVICE | 0x106)
#define USB2D0_INTRUSBE_8 (CFG_USB_DEVICE | 0x108)
#define USB2D0_INTRUSB_8 (CFG_USB_DEVICE | 0x109)
#define USB2D0_INTROUTE_16 (CFG_USB_DEVICE | 0x10a)
#define USB2D0_TSTMODE_8 (CFG_USB_DEVICE | 0x10c)
#define USB2D0_INDEX_8 (CFG_USB_DEVICE | 0x10d)
#define USB2D0_FRAME_16 (CFG_USB_DEVICE | 0x10e)
/*Indexed Registers*/
#define USB2D0_INCSR0_8 (CFG_USB_DEVICE | 0x110)
#define USB2D0_INCSR_16 (CFG_USB_DEVICE | 0x110)
#define USB2D0_INMAXP_16 (CFG_USB_DEVICE | 0x112)
#define USB2D0_OUTCSR_16 (CFG_USB_DEVICE | 0x114)
#define USB2D0_OUTMAXP_16 (CFG_USB_DEVICE | 0x116)
#define USB2D0_OUTCOUNT0_8 (CFG_USB_DEVICE | 0x11a)
#define USB2D0_OUTCOUNT_16 (CFG_USB_DEVICE | 0x11a)
/*FIFOs*/
#define USB2D0_FIFO_0 (CFG_USB_DEVICE | 0x120)
#define USB2D0_FIFO_1 (CFG_USB_DEVICE | 0x124)
#define USB2D0_FIFO_2 (CFG_USB_DEVICE | 0x128)
#define USB2D0_FIFO_3 (CFG_USB_DEVICE | 0x12c)
void usb_dev_init(void);

1
cpu/ppc4xx/vecnum.h
View File

@ -69,6 +69,7 @@
#define VECNUM_MS (32 + 0 ) /* MAL SERR */
#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */
#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */

31
doc/README.AMCC-eval-boards-cleanup Normal file
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@ -0,0 +1,31 @@
---------------------------------------------------------------------
Cleanup of AMCC eval boards (Walnut/Sycamore, Bubinga, Ebony, Ocotea)
---------------------------------------------------------------------
Changes to all AMCC eval boards:
--------------------------------
o Changed u-boot image size to 256 kBytes instead of 512 kBytes on most
boards.
o Use 115200 baud as default console baudrate.
o Added config option to use redundant environment in flash. This is also
the default setting. Option for environment in nvram is still available
for backward compatibility.
o Merged board specific flash drivers to common flash driver:
board/amcc/common/flash.c
Sycamore/Walnut (one port supporting both eval boards):
-------------------------------------------------------
o Cleanup to allow easier "cloning" for different (custom) boards:
o Moved EBC configuration from board specific asm-file "init.S"
using defines in board configuration file. No board specific
asm file needed anymore.
August 01 2005, Stefan Roese <sr@denx.de>

2
drivers/pci_indirect.c
View File

@ -52,7 +52,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_440_GX)
#elif defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \

10
include/405gp_enet.h
View File

@ -67,7 +67,11 @@ struct arp_entry {
/*Register addresses */
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
#endif
#define ZMII_FER (ZMII_BASE)
#define ZMII_SSR (ZMII_BASE + 4)
#define ZMII_SMIISR (ZMII_BASE + 8)
@ -77,7 +81,11 @@ struct arp_entry {
#endif /* CONFIG_440 */
#if defined(CONFIG_440)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#endif
#else
#define EMAC_BASE 0xEF600800
#endif

4
include/440_i2c.h
View File

@ -1,7 +1,11 @@
#ifndef _440_i2c_h_
#define _440_i2c_h_
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
#else
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
#endif /*CONFIG_440_EP CONFIG_440_GR*/
#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)

8
include/440gx_enet.h
View File

@ -140,7 +140,11 @@ typedef struct emac_440gx_hw_st {
/*ZMII Bridge Register addresses */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
#endif
#define ZMII_FER (ZMII_BASE)
#define ZMII_SSR (ZMII_BASE + 4)
#define ZMII_SMIISR (ZMII_BASE + 8)
@ -272,7 +276,11 @@ typedef struct emac_440gx_hw_st {
/* Ethernet MAC Regsiter Addresses */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#endif
#define EMAC_M0 (EMAC_BASE)
#define EMAC_M1 (EMAC_BASE + 4)

2
include/asm-ppc/processor.h
View File

@ -723,6 +723,8 @@
#define PVR_405GPR_RB 0x50910951
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
#define PVR_440EP_RB 0x422218D3
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892

7
include/asm-ppc/u-boot.h
View File

@ -101,13 +101,18 @@ typedef struct bd_info {
unsigned char bi_enet3addr[6];
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX)
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
unsigned int bi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
#endif
#if defined(CONFIG_NX823)
unsigned char bi_sernum[8];
#endif
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
int bi_phynum[2]; /* Determines phy mapping */
int bi_phymode[2]; /* Determines phy mode */
#endif
#if defined(CONFIG_440_GX)
int bi_phynum[4]; /* Determines phy mapping */
int bi_phymode[4]; /* Determines phy mode */

2
include/configs/PPChameleonEVB.h
View File

@ -47,7 +47,7 @@
* CONFIG_PPCHAMELEON_CLK_33
*/
#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
#define CONFIG_PPCHAMELEON_CLK_33
#define CONFIG_PPCHAMELEON_CLK_25
#endif
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))

316
include/configs/bamboo.h Normal file
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@ -0,0 +1,316 @@
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* bamboo.h - configuration for BAMBOO board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440_EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* disable - takes long time! */
/*#define CONFIG_SYS_CLK_FREQ 66666666 /X* external freq to pll */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
/*Don't change either of these*/
#define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
#define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
/*#define CFG_SDRAM_BANKS (2) */
#define CFG_SDRAM_BANKS (1)
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* NVRAM/RTC
*
* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
* The DS1558 code assumes this condition
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#if 0 /* test-only */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
#else
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CFG_I2C_MULTI_EEPROMS
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x0
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
#define CONFIG_BOOTDELAY 3 /* disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.4.251
#define CONFIG_ETHADDR 00:10:EC:00:12:34
#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_SERVERIP 10.0.4.115
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#ifdef CONFIG_440_EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
0 ) & ~CFG_CMD_IMLS)
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

175
include/configs/BUBINGA405EP.h → include/configs/bubinga.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000, 2001
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -28,11 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/* Debug options */
/*#define __DEBUG_START_FROM_SRAM__ */
/*#define DEBUG 1*/
/*
* High Level Configuration Options
* (easy to change)
@ -40,7 +35,7 @@
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_BUBINGA405EP 1 /* ...on a BUBINGA405EP board */
#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
@ -49,8 +44,6 @@
#define CONFIG_NO_SERIAL_EEPROM
/*#undef CONFIG_NO_SERIAL_EEPROM*/
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM
/*
@ -75,48 +68,59 @@
#endif
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#ifdef CFG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_FLASH
/*
* Define here the location of the environment variables (FLASH or NVRAM).
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
* supported for backward compatibility.
*/
#if 1
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#ifdef CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#endif
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=bubinga\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/bubinga/uImage\0" \
"kernel_addr=fff80000\0" \
"ramdisk_addr=fff90000\0" \
"load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#if 1
#define CONFIG_BOOTCOMMAND "" /* autoboot command */
#else
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
#endif
/* Size (bytes) of interrupt driven serial port buffer.
* Set to 0 to use polling instead of interrupts.
* Setting to 0 will also disable RTS/CTS handshaking.
*/
#if 0
#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
#else
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#endif
#if 0
#define CONFIG_BOOTARGS "root=/dev/nfs " \
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
"nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
#else
#define CONFIG_BOOTARGS "root=/dev/hda1 " \
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@ -126,29 +130,8 @@
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
/*
#ifndef __DEBUG_START_FROM_SRAM__
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_KGDB | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
CFG_CMD_ELF )
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_KGDB | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_DATE | \
CFG_CMD_ELF )
#endif
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_CACHE | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
@ -156,14 +139,13 @@
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_KGDB | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
0 )
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -198,6 +180,7 @@
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
@ -211,6 +194,17 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
@ -224,7 +218,6 @@
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
@ -239,8 +232,8 @@
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
@ -253,9 +246,6 @@
* External peripheral base address
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
#define CFG_IR_REG_BASE_ADDR 0xF0200000
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
@ -266,20 +256,11 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#ifdef __DEBUG_START_FROM_SRAM__
#define CFG_SRAM_BASE 0xFFF80000
#define CFG_FLASH_BASE 0xFFF00000
#define CFG_MONITOR_BASE CFG_SRAM_BASE
#else
#define CFG_SRAM_BASE 0xFFF00000
#define CFG_FLASH_BASE 0xFFF80000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#endif
/*#define CFG_MONITOR_LEN (200 * 1024) /XXX* Reserve 200 kB for Monitor */
#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 200 kB for Monitor */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
/*
* For booting Linux, the board info and command line data
@ -287,6 +268,7 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
@ -296,13 +278,20 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* BEG ENVIRONNEMENT FLASH */
#define CFG_FLASH_ADDR0 0x5555
#define CFG_FLASH_ADDR1 0x2aaa
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
#endif
/* END ENVIRONNEMENT FLASH */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* NVRAM organization
*/
@ -332,7 +321,6 @@
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
@ -424,7 +412,6 @@
#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
/*
* Internal Definitions
*

121
include/configs/EBONY.h → include/configs/ebony.h
View File

@ -36,20 +36,31 @@
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
/*
* Define here the location of the environment variables (FLASH or NVRAM).
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
* supported for backward compatibility.
*/
#if 1
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#endif
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
@ -69,7 +80,7 @@
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE 9600
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
@ -87,16 +98,37 @@
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_NVRAM */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_ADDR0 0x5555
#define CFG_FLASH_ADDR1 0x2aaa
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
@ -112,22 +144,47 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#undef CONFIG_BOOTARGS
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=ebony\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/ebony/uImage\0" \
"kernel_addr=ff800000\0" \
"ramdisk_addr=ff810000\0" \
"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOOTARGS "root=/dev/hda1 "
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
#define CONFIG_BOOTDELAY -1 /* disable autoboot */
#define CONFIG_BAUDRATE 9600
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@ -135,16 +192,22 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 8 /* PHY address */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_I2C | \
CFG_CMD_KGDB | \
CFG_CMD_DHCP | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
CFG_CMD_ELF )
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -173,6 +236,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
/*-----------------------------------------------------------------------
* PCI stuff
@ -188,7 +257,7 @@
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/*

120
include/configs/OCOTEA.h → include/configs/ocotea.h
View File

@ -1,6 +1,9 @@
/*
* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -84,6 +87,21 @@
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
/*
* Define here the location of the environment variables (FLASH or NVRAM).
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
* supported for backward compatibility.
*/
#if 1
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#endif
/*-----------------------------------------------------------------------
* NVRAM/RTC
*
@ -97,6 +115,12 @@
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_NVRAM */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
@ -107,6 +131,20 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_ADDR0 0x5555
#define CFG_FLASH_ADDR1 0x2aaa
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
@ -122,22 +160,46 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1
#undef CONFIG_BOOTARGS
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=ocotea\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/ocotea/uImage\0" \
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
"load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BOOTARGS "root=/dev/hda1 "
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
#define CONFIG_BOOTDELAY -1 /* disable autoboot */
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@ -151,32 +213,22 @@
#define CONFIG_PHY3_ADDR 0x18
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.1.2.3
#define CONFIG_ETHADDR 00:04:AC:E3:28:8A
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:04:AC:E3:28:8B
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:04:AC:E3:28:8C
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR 00:04:AC:E3:28:8D
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_SERVERIP 10.1.2.2
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_KGDB | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@ -206,22 +258,28 @@
#define CFG_HZ 100 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/*
@ -233,7 +291,7 @@
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */

255
include/configs/WALNUT405.h → include/configs/walnut.h
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2000, 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* (C) Copyright 2000-2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -34,69 +34,80 @@
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WALNUT405 1 /* ...on a WALNUT405 board */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
/* ...and on a SYCAMORE board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#ifdef CFG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_FLASH
#else
#ifdef CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_NVRAM
#endif
#endif
#undef CONFIG_BOOTARGS
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#if 1
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
#else
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
#endif
/* Size (bytes) of interrupt driven serial port buffer.
* Set to 0 to use polling instead of interrupts.
* Setting to 0 will also disable RTS/CTS handshaking.
*/
#if 0
#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
#else
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=walnut\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/walnut/uImage\0" \
"kernel_addr=fff80000\0" \
"ramdisk_addr=fff80000\0" \
"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#if 0
#define CONFIG_BOOTARGS "root=/dev/nfs " \
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
"nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTARGS "root=/dev/hda1 " \
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_KGDB | \
CFG_CMD_DHCP | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
CFG_CMD_ELF )
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -111,9 +122,9 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
@ -131,9 +142,10 @@
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
@ -142,46 +154,46 @@
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* External peripheral base address
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
#define CFG_IR_REG_BASE_ADDR 0xF0200000
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@ -190,9 +202,20 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFF80000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
/*
* Define here the location of the environment variables (FLASH or NVRAM).
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
* supported for backward compatibility.
*/
#if 1
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#endif
/*
* For booting Linux, the board info and command line data
@ -200,22 +223,35 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* BEG ENVIRONNEMENT FLASH */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_ADDR0 0x5555
#define CFG_FLASH_ADDR1 0x2aaa
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
#endif
/* END ENVIRONNEMENT FLASH */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* NVRAM organization
*/
@ -227,44 +263,61 @@
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CFG_EBC_PB0AP 0x9B015480
#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB1AP 0x02815480
#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
#define CFG_EBC_PB2AP 0x04815A80
#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB3AP 0x01815280
#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB7AP 0x01815280
#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
* External peripheral base address
*-----------------------------------------------------------------------
*/
#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
#define CFG_IR_REG_BASE_ADDR 0xF0200000
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area
*/
#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
*/
#define SPD_EEPROM_ADDRESS 0x50
#define SPD_EEPROM_ADDRESS 0x50
/*
* Internal Definitions

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/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* yellowstone.h - configuration for YELLOWSTONE board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */
#define CONFIG_440_GR 1 /* Specific PPC440GR support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* disable - takes long time! */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
/*Don't change either of these*/
#define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
#define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2)
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 9600
#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* NVRAM/RTC
*
* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
* The DS1558 code assumes this condition
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CFG_I2C_MULTI_EEPROMS
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x0
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
#define CONFIG_BOOTDELAY 3 /* disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.4.251
#define CONFIG_ETHADDR 00:10:EC:00:12:34
#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_SERVERIP 10.0.4.115
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#ifdef CONFIG_440_EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
0 ) & ~CFG_CMD_IMLS)
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

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/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* yosemite.h - configuration for YOSEMITE board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */
#define CONFIG_440_EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* disable - takes long time! */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
/*Don't change either of these*/
#define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
#define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2)
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 9600
#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* NVRAM/RTC
*
* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
* The DS1558 code assumes this condition
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#if 1 /* test-only */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
#else
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CFG_I2C_MULTI_EEPROMS
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x0
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
#define CONFIG_BOOTDELAY 3 /* disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.4.251
#define CONFIG_ETHADDR 00:10:EC:00:12:34
#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_SERVERIP 10.0.4.115
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#ifdef CONFIG_440_EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
0 ) & ~CFG_CMD_IMLS)
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

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