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Merge with /home/sr/git/u-boot

This commit is contained in:
Wolfgang Denk 2005-12-01 01:38:13 +01:00
parent b6f8435664 d96f41e016
commit 4a86d779ff
47 changed files with 2475 additions and 2146 deletions
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27
CHANGELOG
View File

@ -2,6 +2,33 @@
Changes for U-Boot 1.1.4:
======================================================================
* Add support for TQM8541/8555 boards, TQM85xx support reworked:
- Support for TQM8541/8555 boards added.
- Complete rework of TQM8540/8560 support.
- Common TQM85xx code now supports all current TQM85xx platforms
(TQM8540/8541/8555/8560).
- DDR SDRAM size detection added.
- CAS latency default values can be overwritten by setting "serial#"
to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
If problems are detected with this non default CAS latency,
the default values will be used instead.
- Flash size detection added.
- Moved FCC ethernet driver initialization behind TSEC driver init
-> TSEC is first device.
Patch by Stefan Roese, 30 Nov 2005
* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
Patch by John Otken, 23 Nov 2005
* Changed PPC44x startup message (cpu info, speed...) to common style:
On PPC44x platforms, the startup message generated in "cpu.c" only
comprised the ppc type and revision but not additional information
like speed etc. Those speed infos where printed in the board specific
code. This new implementation now prints all CPU infos in the common
cpu specific code. No board specific code is needed anymore and
therefore removed from all current 44x implementations.
Patch by Stefan Roese, 27 Nov 2005
* Adjust TQM834x PHY addresses for latest hardware revision.
* Increase malloc arena on TQM5200 board to 256 kB.

4
CREDITS
View File

@ -317,6 +317,10 @@ E: rof@sysgo.de
D: Initial support for SSV-DNP1110, SMC91111 driver
W: www.elinos.com
N: John Otken
E: jotken@softadvances.com
D: Support for AMCC Luan 440SP board
N: Tolunay Orkun
E: torkun@nextio.com
D: Support for Cogent CSB272 & CSB472 boards

9
MAINTAINERS
View File

@ -240,6 +240,10 @@ Tolunay Orkun <torkun@nextio.com>
csb272 PPC405GP
csb472 PPC405GP
John Otken <jotken@softadvances.com>
luan PPC440SP
Keith Outwater <Keith_Outwater@mvis.com>
GEN860T MPC860T
@ -270,10 +274,15 @@ Daniel Poirot <dan.poirot@windriver.com>
Stefan Roese <sr@denx.de>
uc100 MPC857
TQM85xx MPC8540/8541/8555/8560
bamboo PPC440EP
bunbinga PPC405EP
ebony PPC440GP
ocotea PPC440GX
p3p440 PPC440GP
sycamore PPC405GPr
walnut PPC405GP
yellowstone PPC440GR

15
MAKEALL
View File

@ -68,12 +68,13 @@ LIST_4xx=" \
csb472 DASA_SIM DP405 DU405 \
ebony ERIC EXBITGEN G2000 \
HH405 HUB405 JSE KAREF \
METROBOX MIP405 MIP405T ML2 \
ml300 ocotea OCRTC ORSG \
p3p440 PCI405 PIP405 PLU405 \
PMC405 PPChameleonEVB sbc405 VOH405 \
VOM405 W7OLMC W7OLMG walnut \
WUH405 XPEDITE1K yellowstone yosemite \
luan METROBOX MIP405 MIP405T \
ML2 ml300 ocotea OCRTC \
ORSG p3p440 PCI405 PIP405 \
PLU405 PMC405 PPChameleonEVB sbc405 \
VOH405 VOM405 W7OLMC W7OLMG \
walnut WUH405 XPEDITE1K yellowstone \
yosemite \
"
#########################################################################
@ -127,7 +128,7 @@ LIST_85xx=" \
MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \
MPC8555CDS MPC8560ADS PM854 PM856 \
sbc8540 sbc8560 stxgp3 TQM8540 \
TQM8560 \
TQM8541 TQM8555 TQM8560 \
"
#########################################################################

26
Makefile
View File

@ -815,6 +815,9 @@ JSE_config: unconfig
KAREF_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx karef sandburst
luan_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx luan amcc
METROBOX_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx metrobox sandburst
@ -1322,11 +1325,24 @@ sbc8560_66_config: unconfig
stxgp3_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
TQM8540_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx tqm8540
TQM8560_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx tqm8560
TQM8540_config \
TQM8541_config \
TQM8555_config \
TQM8560_config: unconfig
@case "$@" in \
TQM8540_config) CTYPE=8540;; \
TQM8541_config) CTYPE=8541;; \
TQM8555_config) CTYPE=8555;; \
TQM8560_config) CTYPE=8560;; \
esac; \
>include/config.h ; \
echo "... TQM"$${CTYPE}; \
echo "#define CONFIG_MPC$${CTYPE}">>include/config.h; \
echo "#define CONFIG_TQM$${CTYPE}">>include/config.h; \
echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>include/config.h; \
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>include/config.h; \
echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>include/config.h
@./mkconfig -a TQM85xx ppc mpc85xx tqm85xx
#########################################################################
## 74xx/7xx Systems

23
board/amcc/bamboo/bamboo.c
View File

@ -359,10 +359,7 @@ void nand_init(void)
int checkboard(void)
{
sys_info_t sysinfo;
unsigned char *s = getenv("serial#");
get_sys_info(&sysinfo);
char *s = getenv("serial#");
printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
@ -371,12 +368,6 @@ int checkboard(void)
}
putc('\n');
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
@ -502,20 +493,8 @@ int testdram(void)
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
unsigned long addr;
/*--------------------------------------------------------------------------+
* Bamboo is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.

8
board/amcc/ebony/ebony.c
View File

@ -90,11 +90,8 @@ int board_early_init_f(void)
int checkboard(void)
{
sys_info_t sysinfo;
char *s = getenv("serial#");
get_sys_info(&sysinfo);
printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
@ -102,11 +99,6 @@ int checkboard(void)
}
putc('\n');
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}

18
board/tqm8560/Makefile → board/amcc/luan/Makefile
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2001
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -12,7 +12,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@ -25,15 +25,15 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
SOBJS := init.o
#SOBJS :=
OBJS = $(BOARD).o
OBJS += flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
@ -41,8 +41,8 @@ distclean: clean
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
sinclude .depend
#########################################################################

29
board/tqm8560/config.mk → board/amcc/luan/config.mk
View File

@ -1,6 +1,6 @@
# Copyright 2004 Freescale Semiconductor.
# Modified by Xianghua Xiao, X.Xiao@motorola.com
# (C) Copyright 2002,Motorola Inc.
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
@ -22,8 +22,23 @@
#
#
# tqm8560 board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 256k
# esd ADCIOP boards
#
TEXT_BASE = 0xfffc0000
#TEXT_BASE = 0x00001000
ifeq ($(ramsym),1)
TEXT_BASE = 0xFBD00000
else
TEXT_BASE = 0xFFFC0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

85
board/amcc/luan/epld.h Normal file
View File

@ -0,0 +1,85 @@
#define EPLD0_FSEL_FB2 0x80
#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */
#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */
#define EPLD0_RAW_CARD_BIT1 0x10
#define EPLD0_RAW_CARD_BIT2 0x08
#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */
#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */
#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */
#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */
#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */
#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */
#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */
#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */
#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */
#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */
#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */
#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */
#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */
#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */
#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */
#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */
#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */
#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */
#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */
#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */
#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */
#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */
#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */
#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */
#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */
#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */
#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */
#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */
#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */
#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */
#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */
#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */
#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */
#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */
#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */
#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */
#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */
#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */
#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */
#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */
#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */
#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */
#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */
#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */
#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */
#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */
#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */
typedef struct {
unsigned char status; /* misc status */
unsigned char clock; /* clock status, PCI-X clock control */
unsigned char ethuart; /* Ethernet, UART status */
unsigned char leds; /* LED register */
unsigned char vth01; /* PCI0, PCI1 VTH register */
unsigned char pciints; /* PCI0, PCI1 interrupts */
unsigned char pci2; /* PCI2 interrupts, clock control */
unsigned char vth2; /* PCI2 VTH register */
unsigned char filler1[4096-8];
unsigned char gpio00; /* GPIO bits 0-7 */
unsigned char gpio08; /* GPIO bits 8-15 */
unsigned char gpio16; /* GPIO bits 16-23 */
unsigned char gpio24; /* GPIO bits 24-31 */
unsigned char filler2[4096-4];
unsigned char version; /* EPLD version */
} epld_t;

111
board/amcc/luan/flash.c Normal file
View File

@ -0,0 +1,111 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = {
{0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */
};
/*
* include common flash code (for amcc boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned short index = 0;
int i;
/* read FPGA base register FPGA_REG0 */
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size((vu_long *)
flash_addr_table[index][i],
&flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[2]);
#ifdef CFG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[2]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
&flash_info[2]);
#endif
total_b += flash_info[i].size;
}
return total_b;
}

132
board/amcc/luan/init.S Normal file
View File

@ -0,0 +1,132 @@
/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ; \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */
/* large flash */
tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
#else /* else booting from small flash */
tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
#endif
tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I )
#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */
tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */
tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
#elif (CFG_SMALL_FLASH == 0xfff00000)
tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
#else
#error DONT KNOW SRAM LOCATION
#endif
/* internal ram (l2 cache) */
tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I )
/* peripherals at f0000000 */
tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
/* PCI */
#if (CONFIG_COMMANDS & CFG_CMD_PCI)
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
#endif
tlbtab_end

458
board/amcc/luan/luan.c Normal file
View File

@ -0,0 +1,458 @@
/*
* (C) Copyright 2005
* John Otken, jotken@softadvances.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include "epld.h"
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*************************************************************************
* int board_early_init_f()
*
************************************************************************/
int board_early_init_f(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
mtebc( pb2ap, 0x03800000 );
mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic1sr, 0xffffffff );
mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
return 0;
}
/*************************************************************************
* int misc_init_r()
*
************************************************************************/
int misc_init_r(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
return 0;
}
/*************************************************************************
* int checkboard()
*
************************************************************************/
int checkboard(void)
{
char *s = getenv("serial#");
printf("Board: Luan - AMCC PPC440SP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return 0;
}
/*************************************************************************
* long int fixed_sdram()
*
************************************************************************/
static long int fixed_sdram(void)
{ /* DDR2 init from BDI2000 script */
mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */
mtdcr( 0x11, 0x84000000 );
mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
mtdcr( 0x11, 0x2D122000 );
mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */
mtdcr( 0x11, 0x00800026 );
mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
mtdcr( 0x11, 0x82000800 );
mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */
mtdcr( 0x11, 0x80000000 );
mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */
mtdcr( 0x11, 0x00000201 );
mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */
mtdcr( 0x11, 0x00000201 );
mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */
mtdcr( 0x11, 0x08200000 );
mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */
mtdcr( 0x11, 0x80201000 );
mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */
mtdcr( 0x11, 0x42103242 );
mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */
mtdcr( 0x11, 0x0C100D14 );
mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */
mtdcr( 0x11, 0x00000642 );
mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */
mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */
mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */
mtdcr( 0x11, 0x81b80000 );
mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */
mtdcr( 0x11, 0x82100400 );
mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */
mtdcr( 0x11, 0x80820000 );
mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */
mtdcr( 0x11, 0x80830000 );
mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */
mtdcr( 0x11, 0x80810000 );
mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */
mtdcr( 0x11, 0x80800542 );
mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */
mtdcr( 0x11, 0x82100400 );
mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */
mtdcr( 0x11, 0x99080000 );
mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */
mtdcr( 0x11, 0x99080000 );
mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */
mtdcr( 0x11, 0x99080000 );
mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */
mtdcr( 0x11, 0x99080000 );
mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */
mtdcr( 0x11, 0x80800442 );
mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */
mtdcr( 0x11, 0x80810380 );
mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */
mtdcr( 0x11, 0x80810000 );
udelay( 10*1000 );
mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */
mtdcr( 0x11, 0x28000000 ); /* set DC_EN */
udelay( 100*1000 );
mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */
mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */
mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */
mtdcr( 0x11, 0x00000000 );
mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */
mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */
mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */
mtdcr( 0x11, 0x00000200 );
return 512 << 20;
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram( int board_type )
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram (0);
#else
dram_size = fixed_sdram ();
#endif
return dram_size;
}
/*************************************************************************
* int testdram()
*
************************************************************************/
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *) 0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init( struct pci_controller *hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The luan board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
*
************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
}
#endif
/*************************************************************************
* int on_off()
*
************************************************************************/
static int on_off( const char *s )
{
if (strcmp(s, "on") == 0) {
return 1;
} else if (strcmp(s, "off") == 0) {
return 0;
}
return -1;
}
/*************************************************************************
* void l2cache_disable()
*
************************************************************************/
static void l2cache_disable(void)
{
mtdcr( l2_cache_cfg, 0 );
}
/*************************************************************************
* void l2cache_enable()
*
************************************************************************/
static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
{
mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
mtdcr( l2_cache_snp1, 0 );
__asm__ volatile ("sync"); /* msync */
mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
__asm__ volatile ("sync");
}
/*************************************************************************
* int l2cache_status()
*
************************************************************************/
static int l2cache_status(void)
{
return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
}
/*************************************************************************
* int do_l2cache()
*
************************************************************************/
int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
{
switch (argc) {
case 2: /* on / off */
switch (on_off(argv[1])) {
case 0: l2cache_disable();
break;
case 1: l2cache_enable();
break;
}
/* FALL TROUGH */
case 1: /* get status */
printf ("L2 Cache is %s\n",
l2cache_status() ? "ON" : "OFF");
return 0;
default:
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
return 0;
}
U_BOOT_CMD(
l2cache, 2, 1, do_l2cache,
"l2cache - enable or disable L2 cache\n",
"[on, off]\n"
" - enable or disable L2 cache\n"
);

103
board/tqm8560/u-boot.lds → board/amcc/luan/u-boot.lds
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2002,2003, Motorola,Inc.
* Xianghua Xiao, X.Xiao@motorola.com.
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -34,61 +34,67 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
board/tqm8560/init.o (.bootpg)
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
.text :
{
cpu/mpc85xx/start.o (.text)
board/tqm8560/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/luan/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@ -104,10 +110,10 @@ SECTIONS
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
.data :
{
*(.data)
*(.data1)
@ -124,6 +130,7 @@ SECTIONS
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
@ -137,7 +144,7 @@ SECTIONS
__init_end = .;
__bss_start = .;
.bss :
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)

8
board/amcc/ocotea/ocotea.c
View File

@ -186,11 +186,8 @@ int board_early_init_f (void)
int checkboard (void)
{
sys_info_t sysinfo;
char *s = getenv ("serial#");
get_sys_info (&sysinfo);
printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
if (s != NULL) {
puts (", serial# ");
@ -198,11 +195,6 @@ int checkboard (void)
}
putc ('\n');
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}

24
board/amcc/yellowstone/yellowstone.c
View File

@ -188,10 +188,7 @@ int misc_init_r (void)
int checkboard(void)
{
sys_info_t sysinfo;
unsigned char *s = getenv("serial#");
get_sys_info(&sysinfo);
char *s = getenv("serial#");
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
if (s != NULL) {
@ -200,13 +197,6 @@ int checkboard(void)
}
putc('\n');
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
return (0);
}
@ -325,20 +315,8 @@ int testdram(void)
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
unsigned long addr;
/*--------------------------------------------------------------------------+
* Bamboo is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.

24
board/amcc/yosemite/yosemite.c
View File

@ -184,10 +184,7 @@ int misc_init_r (void)
int checkboard(void)
{
sys_info_t sysinfo;
unsigned char *s = getenv("serial#");
get_sys_info(&sysinfo);
char *s = getenv("serial#");
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
@ -196,13 +193,6 @@ int checkboard(void)
}
putc('\n');
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
return (0);
}
@ -321,20 +311,8 @@ int testdram(void)
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
unsigned long addr;
/*--------------------------------------------------------------------------+
* Bamboo is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.

11
board/prodrive/p3p440/p3p440.c
View File

@ -120,11 +120,7 @@ int board_early_init_f(void)
int checkboard(void)
{
sys_info_t sysinfo;
char *s = getenv("serial#");
char buf[32];
get_sys_info(&sysinfo);
printf("Board: P3P440");
if (s != NULL) {
@ -140,13 +136,6 @@ int checkboard(void)
putc('\n');
printf(" at %s MHz (VCO=%lu, PLB=%lu, OPB=%lu, EBC=%lu MHz)\n",
strmhz(buf, sysinfo.freqProcessor),
sysinfo.freqVCOMhz / 1000000,
sysinfo.freqPLB / 1000000,
sysinfo.freqOPB / 1000000,
sysinfo.freqEPB / 1000000);
return (0);
}

6
board/sandburst/karef/karef.c
View File

@ -305,12 +305,6 @@ int checkboard (void)
printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
}
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
/* Fix the ack in the bme 32 */
udelay(5000);
out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);

7
board/sandburst/metrobox/metrobox.c
View File

@ -272,13 +272,6 @@ int checkboard (void)
printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
/* Fix the ack in the bme 32 */
udelay(5000);
out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);

241
board/tqm8540/init.S
View File

@ -1,241 +0,0 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>
/*
* TLB0 and TLB1 Entries
*
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
* these TLB entries are established.
*
* The TLB entries for DDR are dynamically setup in spd_sdram()
* and use TLB1 Entries 8 through 15 as needed according to the
* size of DDR memory.
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
* MAS2: epn, sharen, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
#define entry_start \
mflr r1 ; \
bl 0f ;
#define entry_end \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
/*
* Number of TLB0 and TLB1 entries in the following table
*/
.long 13
/*
* TLB0 16K Cacheable, non-guarded
* 0xd001_0000 16K Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
* controler and real memory have been configured.
*
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 0, 1: 32M Non-cacheable, guarded
* 0xfe000000 32M FLASH
* Out of reset this entry is only 4K.
*/
.long TLB1_MAS0(1, 1, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
.long TLB1_MAS0(1, 2, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
.long TLB1_MAS0(1, 3, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
.long TLB1_MAS0(1, 4, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
.long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
.long TLB1_MAS0(1, 6, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 7: 256M DDR
* 0x00000000 256M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
.long TLB1_MAS0(1, 7, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 8, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
/*
* Rapid IO at 0xc000_0000 for 512 M
*/
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 0x05
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
.long LAWBAR4,LAWAR4
entry_end

284
board/tqm8540/tqm8540.c
View File

@ -1,284 +0,0 @@
/*
* Copyright 2005 DENX Software Engineering
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc (unsigned int dram_size);
#endif
extern long int spd_sdram (void);
void local_bus_init (void);
long int fixed_sdram (void);
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
puts ("Board: TQM8540\n");
#ifdef CONFIG_PCI
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
printf ("PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
long int initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *) CFG_IMMR;
#if defined(CONFIG_DDR_DLL)
{
volatile ccsr_gur_t *gur= &immap->im_gur;
int i,x;
x = 10;
/*
* Work around to stabilize DDR DLL
*/
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
udelay (200);
while (gur->ddrdllcr != 0x81000100) {
gur->devdisr = gur->devdisr | 0x00010000;
asm("sync;isync;msync");
for (i=0; i<x; i++)
;
gur->devdisr = gur->devdisr & 0xfff7ffff;
asm("sync;isync;msync");
x++;
}
}
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
#if defined(CONFIG_DDR_ECC)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc (dram_size);
#endif
return dram_size;
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
/*
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
* If localbus freq is > 133Mhz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
get_sys_info (&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
lbc->ltedr = 0xa4c80000; /* DK: !!! */
} else if (lbc_hz >= 133) {
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
} else {
/*
* On REV1 boards, need to change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4 temporarily.
*/
uint pvr = get_pvr ();
uint temp_lbcdll = 0;
if (pvr == PVR_85xx_REV1) {
/* FIXME: Justify the high bit here. */
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
udelay (200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm ("sync;isync;msync");
}
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf ("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
ddr->err_disable = 0x0000000D;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
asm ("sync;isync;msync");
udelay (500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
asm ("sync; isync; msync");
udelay (500);
#endif
return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER}},
{}
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc85xxads_config_table,
#endif
};
#endif /* CONFIG_PCI */
void pci_init_board (void)
{
#ifdef CONFIG_PCI
extern void pci_mpc85xx_init (struct pci_controller *hose);
pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}

2
board/tqm8540/Makefile → board/tqm85xx/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
OBJS := $(BOARD).o sdram.o
SOBJS := init.o
#SOBJS :=

2
board/tqm8540/config.mk → board/tqm85xx/config.mk
View File

@ -22,7 +22,7 @@
#
#
# tqm8540 board
# tqm85xx board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 256k
#

31
board/tqm8560/init.S → board/tqm85xx/init.S
View File

@ -108,18 +108,18 @@ tlb1_entry:
/*
* TLB 0, 1: 32M Non-cacheable, guarded
* 0xfe000000 32M FLASH
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
.long TLB1_MAS0(1, 1, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 2: 256M Non-cacheable, guarded
@ -171,23 +171,21 @@ tlb1_entry:
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 7: 256M DDR
* 0x00000000 256M DDR System memory
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
.long TLB1_MAS0(1, 7, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 8, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
@ -207,19 +205,14 @@ tlb1_entry:
* If flash is 8M at default position (last 8M), no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))

226
board/tqm85xx/sdram.c Normal file
View File

@ -0,0 +1,226 @@
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd.h>
struct sdram_conf_s {
unsigned long size;
unsigned long reg;
};
typedef struct sdram_conf_s sdram_conf_t;
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
{(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
};
#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
int cas_latency(void);
/*
* Autodetect onboard DDR SDRAM on 85xx platforms
*
* NOTE: Some of the hardcoded values are hardware dependant,
* so this should be extended for other future boards
* using this routine!
*/
long int sdram_setup(int casl)
{
int i;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
unsigned long cfg_ddr_timing1;
unsigned long cfg_ddr_mode;
/*
* Disable memory controller.
*/
ddr->cs0_config = 0;
ddr->sdram_cfg = 0;
switch (casl) {
case 20:
cfg_ddr_timing1 = 0x47405331 | (3 << 16);
cfg_ddr_mode = 0x40020002 | (2 << 4);
break;
case 25:
cfg_ddr_timing1 = 0x47405331 | (4 << 16);
cfg_ddr_mode = 0x40020002 | (6 << 4);
break;
case 30:
default:
cfg_ddr_timing1 = 0x47405331 | (5 << 16);
cfg_ddr_mode = 0x40020002 | (3 << 4);
break;
}
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
ddr->cs0_config = ddr_cs_conf[0].reg;
ddr->timing_cfg_1 = cfg_ddr_timing1;
ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
ddr->sdram_mode = cfg_ddr_mode;
ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
ddr->err_disable = 0x0000000D;
asm ("sync;isync;msync");
udelay(1000);
ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
asm ("sync; isync; msync");
udelay(1000);
for (i=0; i<N_DDR_CS_CONF; i++) {
ddr->cs0_config = ddr_cs_conf[i].reg;
if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
/*
* OK, size detected -> all done
*/
return ddr_cs_conf[i].size;
}
}
return 0; /* nothing found ! */
}
void board_add_ram_info(int use_default)
{
int casl;
if (use_default)
casl = CONFIG_DDR_DEFAULT_CL;
else
casl = cas_latency();
puts(" (CL=");
switch (casl) {
case 20:
puts("2)");
break;
case 25:
puts("2.5)");
break;
case 30:
puts("3)");
break;
}
}
long int initdram (int board_type)
{
long dram_size = 0;
int casl;
#if defined(CONFIG_DDR_DLL)
/*
* This DLL-Override only used on TQM8540 and TQM8560
*/
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_gur_t *gur= &immap->im_gur;
int i,x;
x = 10;
/*
* Work around to stabilize DDR DLL
*/
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
udelay (200);
while (gur->ddrdllcr != 0x81000100) {
gur->devdisr = gur->devdisr | 0x00010000;
asm("sync;isync;msync");
for (i=0; i<x; i++)
;
gur->devdisr = gur->devdisr & 0xfff7ffff;
asm("sync;isync;msync");
x++;
}
}
#endif
casl = cas_latency();
dram_size = sdram_setup(casl);
if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
/*
* Try again with default CAS latency
*/
puts("Problem with CAS lantency");
board_add_ram_info(1);
puts(", using default CL!\n");
casl = CONFIG_DDR_DEFAULT_CL;
dram_size = sdram_setup(casl);
puts(" ");
}
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf ("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test passed.\n");
return 0;
}
#endif

274
board/tqm8560/tqm8560.c → board/tqm85xx/tqm85xx.c
View File

@ -1,5 +1,7 @@
/*
* Copyright 2005 DENX Software Engineering
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
@ -32,16 +34,15 @@
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
#include <flash.h>
#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc (unsigned int dram_size);
#endif
extern long int spd_sdram (void);
extern flash_info_t flash_info[]; /* FLASH chips info */
void local_bus_init (void);
long int fixed_sdram (void);
ulong flash_get_size (ulong base, int banknum);
#ifdef CONFIG_CPM2
/*
* I/O Port configuration table
*
@ -53,24 +54,24 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
@ -89,20 +90,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
@ -135,12 +136,12 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
@ -195,16 +196,49 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
#endif /* CONFIG_CPM2 */
#define CASL_STRING1 "casl=xx"
#define CASL_STRING2 "casl="
int board_early_init_f (void)
static const int casl_table[] = { 20, 25, 30 };
#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
int cas_latency(void)
{
return 0;
char *s = getenv("serial#");
int casl;
int val;
int i;
casl = CONFIG_DDR_DEFAULT_CL;
if (s != NULL) {
if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
strlen(CASL_STRING2)) == 0) {
val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
for (i=0; i<N_CASL; ++i) {
if (val == casl_table[i]) {
return val;
}
}
}
}
return casl;
}
int checkboard (void)
{
puts ("Board: TQM8560\n");
char *s = getenv("serial#");
printf("Board: %s", CONFIG_BOARDNAME);
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef CONFIG_PCI
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
@ -212,6 +246,7 @@ int checkboard (void)
#else
printf ("PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
@ -220,59 +255,69 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
int misc_init_r (void)
{
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *) CFG_IMMR;
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
#if defined(CONFIG_DDR_DLL)
{
volatile ccsr_gur_t *gur= &immap->im_gur;
int i,x;
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
x = 10;
/*
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
/*
* Work around to stabilize DDR DLL
* Re-check to get correct base address
*/
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
udelay (200);
while (gur->ddrdllcr != 0x81000100) {
gur->devdisr = gur->devdisr | 0x00010000;
asm("sync;isync;msync");
for (i=0; i<x; i++)
;
gur->devdisr = gur->devdisr & 0xfff7ffff;
asm("sync;isync;msync");
x++;
}
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
}
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
#if defined(CONFIG_DDR_ECC)
/*
* Initialize and enable DDR ECC.
* Check if only one FLASH bank is available
*/
ddr_enable_ecc (dram_size);
#endif
if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
memctl->or1 = 0;
memctl->br1 = 0;
return dram_size;
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE, 0xffffffff,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
}
return 0;
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
@ -329,79 +374,6 @@ void local_bus_init (void)
}
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf ("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
ddr->err_disable = 0x0000000D;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
asm ("sync;isync;msync");
udelay (500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
asm ("sync; isync; msync");
udelay (500);
#endif
return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.

4
board/tqm8540/u-boot.lds → board/tqm85xx/u-boot.lds
View File

@ -35,7 +35,7 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
board/tqm8540/init.o (.bootpg)
board/tqm85xx/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@ -65,7 +65,7 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
board/tqm8540/init.o (.text)
board/tqm85xx/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)

8
board/xpedite1k/xpedite1k.c
View File

@ -96,15 +96,7 @@ int board_early_init_f(void)
int checkboard (void)
{
sys_info_t sysinfo;
get_sys_info (&sysinfo);
printf ("Board: XES XPedite1000 440GX\n");
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}

54
cpu/ppc4xx/405gp_pci.c
View File

@ -437,11 +437,11 @@ void pci_440_init (struct pci_controller *hose)
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
unsigned long strap;
mfsdr(sdr_sdstp1,strap);
if ( (strap & 0x00010000) == 0 ){
if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
@ -450,7 +450,7 @@ void pci_440_init (struct pci_controller *hose)
unsigned long strap;
strap = mfdcr(cpc0_strp1);
if( (strap & 0x00040000) == 0 ){
if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
@ -466,26 +466,26 @@ void pci_440_init (struct pci_controller *hose)
pci_set_region(hose->regions + reg_num++,
0x00000000,
PCIX0_IOBASE,
0x10000,
PCI_REGION_IO);
PCIX0_IOBASE,
0x10000,
PCI_REGION_IO);
pci_set_region(hose->regions + reg_num++,
CFG_PCI_TARGBASE,
CFG_PCI_MEMBASE,
0x10000000,
PCI_REGION_MEM );
CFG_PCI_MEMBASE,
0x10000000,
PCI_REGION_MEM );
hose->region_count = reg_num;
pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
#if defined(CFG_PCI_PRE_INIT)
/* Let board change/modify hose & do initial checks */
if( pci_pre_init (hose) == 0 ){
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#endif
pci_register_hose( hose );
@ -496,9 +496,9 @@ void pci_440_init (struct pci_controller *hose)
#if defined(CFG_PCI_TARGET_INIT)
pci_target_init(hose); /* Let board setup pci target */
#else
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
#if defined(CONFIG_440GX)
@ -524,24 +524,24 @@ void pci_440_init (struct pci_controller *hose)
out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
out32r( PCIX0_POM0PCIAH, 0x00000000 );
out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
#endif
/*--------------------------------------------------------------------------+
* PCI host configuration -- we don't make any assumptions here ... the
* _board_must_indicate_ what to do -- there's just too many runtime
* scenarios in environments like cPCI, PPMC, etc. to make a determination
* based on hard-coded values or state of arbiter enable.
* _board_must_indicate_ what to do -- there's just too many runtime
* scenarios in environments like cPCI, PPMC, etc. to make a determination
* based on hard-coded values or state of arbiter enable.
*--------------------------------------------------------------------------*/
if( is_pci_host(hose) ){
if (is_pci_host(hose)) {
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
hose->last_busno = pci_hose_scan(hose);
}
hose->last_busno = pci_hose_scan(hose);
}
}

75
cpu/ppc4xx/4xx_enet.c
View File

@ -314,9 +314,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
unsigned mode_reg;
unsigned short devnum;
unsigned short reg_short;
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
sys_info_t sysinfo;
int ethgroup;
#if defined(CONFIG_440GX)
int ethgroup = -1;
#endif
#endif
EMAC_4XX_HW_PST hw_p = dev->priv;
@ -328,7 +330,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
return -1;
}
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
#endif
@ -371,7 +373,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
hw_p->tx_u_index = 0; /* Transmit User Queue Index */
#if defined(CONFIG_440)
#if defined(CONFIG_440) && !defined(CONFIG_440SP)
/* set RMII mode */
/* NOTE: 440GX spec states that mode is mutually exclusive */
/* NOTE: Therefore, disable all other EMACS, since we handle */
@ -399,7 +401,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#endif
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
#endif /* defined(CONFIG_440) */
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
__asm__ volatile ("eieio");
@ -414,7 +416,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
failsafe--;
}
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
@ -429,7 +431,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) */
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
@ -466,7 +468,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (hw_p->first_init == 0) {
miiphy_reset (dev->name, reg);
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_CIS8201_PHY)
/*
* Cicada 8201 PHY needs to have an extended register whacked
@ -542,7 +544,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
#if defined(CONFIG_440)
#if defined(CONFIG_440) && !defined(CONFIG_440SP)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
if (speed == 100) {
@ -570,10 +572,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out32 (RGMII_SSR, reg);
}
#endif /* defined(CONFIG_440) */
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
/* set the Mal configuration reg */
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
@ -756,9 +758,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
/* set speed */
if (speed == _1000BASET)
if (speed == _1000BASET) {
#if defined(CONFIG_440SP)
#define SDR0_PFC1_EM_1000 0x00200000
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);
pfc1 |= SDR0_PFC1_EM_1000;
mtsdr (sdr_pfc1, pfc1);
#endif
mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
else if (speed == _100BASET)
} else if (speed == _100BASET)
mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
else
mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
@ -883,8 +892,21 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
}
}
#if defined (CONFIG_440)
#if defined(CONFIG_440SP)
/*
* Hack: On 440SP all enet irq sources are located on UIC1
* Needs some cleanup. --sr
*/
#define UIC0MSR uic1msr
#define UIC0SR uic1sr
#else
#define UIC0MSR uic0msr
#define UIC0SR uic0sr
#endif
int enetInt (struct eth_device *dev)
{
int serviced;
@ -911,20 +933,17 @@ int enetInt (struct eth_device *dev)
hw_p = dev->priv;
/* enter loop that stays in interrupt code until nothing to service */
do {
serviced = 0;
my_uic0msr = mfdcr (uic0msr);
my_uic0msr = mfdcr (UIC0MSR);
my_uic1msr = mfdcr (uic1msr);
#if defined(CONFIG_440GX)
my_uic2msr = mfdcr (uic2msr);
#endif
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
&& !(my_uic1msr &
(UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
UIC_MRDE))) {
&& !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
/* not for us */
return (rc);
}
@ -962,12 +981,13 @@ int enetInt (struct eth_device *dev)
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
return (rc); /* we had errors so get out */
}
}
#if !defined(CONFIG_440SP)
if (hw_p->devnum == 1) {
if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
@ -979,7 +999,7 @@ int enetInt (struct eth_device *dev)
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
return (rc); /* we had errors so get out */
}
@ -996,7 +1016,7 @@ int enetInt (struct eth_device *dev)
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (uic2sr, UIC_ETH2);
return (rc); /* we had errors so get out */
@ -1014,18 +1034,20 @@ int enetInt (struct eth_device *dev)
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (uic2sr, UIC_ETH3);
return (rc); /* we had errors so get out */
}
}
#endif /* CONFIG_440GX */
#endif /* !CONFIG_440SP */
/* handle MAX TX EOB interrupt from a tx */
if (my_uic0msr & UIC_MTE) {
mal_rx_eob = mfdcr (maltxeobisr);
mtdcr (maltxeobisr, mal_rx_eob);
mtdcr (uic0sr, UIC_MTE);
mtdcr (UIC0SR, UIC_MTE);
}
/* handle MAL RX EOB interupt from a receive */
/* check for EOB on valid channels */
@ -1040,7 +1062,8 @@ int enetInt (struct eth_device *dev)
rc = 0;
}
}
mtdcr (uic0sr, UIC_MRE); /* Clear */
mtdcr (UIC0SR, UIC_MRE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
switch (hw_p->devnum) {
case 0:
@ -1489,7 +1512,7 @@ int ppc_4xx_eth_initialize (bd_t * bis)
#endif
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register (dev->name,
emac4xx_miiphy_read, emac4xx_miiphy_write);
emac4xx_miiphy_read, emac4xx_miiphy_write);
#endif
} /* end for each supported device */
@ -1531,7 +1554,7 @@ int emac4xx_miiphy_initialize (bd_t * bis)
{
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register ("ppc_4xx_eth0",
emac4xx_miiphy_read, emac4xx_miiphy_write);
emac4xx_miiphy_read, emac4xx_miiphy_write);
#endif
return 0;

279
cpu/ppc4xx/cpu.c
View File

@ -39,121 +39,146 @@
#if defined(CONFIG_440)
static int do_chip_reset( unsigned long sys0, unsigned long sys1 );
#define FREQ_EBC (sys_info.freqEPB)
#else
#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define PCI_ASYNC
int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
unsigned long val;
mfsdr(cpc0_strp1, val);
return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
#endif
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
#endif
#if defined(CONFIG_405EP)
return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
#endif
#if defined(CONFIG_440GP)
return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
unsigned long val;
mfsdr(sdr_sdstp1, val);
return (val & SDR0_SDSTP1_PAE_MASK);
#endif
}
#endif
#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440GX) || defined(CONFIG_440SP)
#define I2C_BOOTROM
int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
unsigned long val;
mfsdr(sdr_sdcs, val);
return (val & SDR0_SDCS_SDD);
#endif
}
#endif
#if defined(CONFIG_440)
static int do_chip_reset(unsigned long sys0, unsigned long sys1);
#endif
/* ------------------------------------------------------------------------- */
int checkcpu (void)
{
#if defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_440) || \
defined(CONFIG_IOP480)
uint pvr = get_pvr();
#endif
#if defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_IOP480)
#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
DECLARE_GLOBAL_DATA_PTR;
uint pvr = get_pvr();
ulong clock = gd->cpu_clk;
char buf[32];
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
PPC405_SYS_INFO sys_info;
#if !defined(CONFIG_IOP480)
sys_info_t sys_info;
puts ("CPU: ");
get_sys_info(&sys_info);
#ifdef CONFIG_405GP
puts ("AMCC PowerPC 405GP");
if (pvr == PVR_405GPR_RB) {
putc('r');
}
puts (" Rev. ");
puts("AMCC PowerPC 4");
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
puts("05");
#endif
#ifdef CONFIG_405CR
puts ("AMCC PowerPC 405CR Rev. ");
#endif
#ifdef CONFIG_405EP
puts ("AMCC PowerPC 405EP Rev. ");
#if defined(CONFIG_440)
puts("40");
#endif
switch (pvr) {
case PVR_405GP_RB:
case PVR_405GPR_RB:
putc('B');
puts("GP Rev. B");
break;
case PVR_405GP_RC:
#ifdef CONFIG_405CR
case PVR_405CR_RC:
#endif
putc('C');
puts("GP Rev. C");
break;
case PVR_405GP_RD:
putc('D');
puts("GP Rev. D");
break;
#ifdef CONFIG_405GP
case PVR_405GP_RE:
putc('E');
case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
puts("GP Rev. E");
break;
#endif
case PVR_405CR_RA:
putc('A');
puts("CR Rev. A");
break;
case PVR_405CR_RB:
puts("CR Rev. B");
break;
#ifdef CONFIG_405CR
case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
puts("CR Rev. C");
break;
#endif
case PVR_405GPR_RB:
puts("GPr Rev. B");
break;
case PVR_405EP_RB:
putc('B');
puts("EP Rev. B");
break;
default:
printf ("? (PVR=%08x)", pvr);
break;
}
printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
sys_info.freqPLB / 1000000,
sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
#if defined(CONFIG_405GP)
if (mfdcr(strap) & PSR_PCI_ASYNC_EN) {
printf (" PCI async ext clock used, ");
} else {
printf (" PCI sync clock at %lu MHz, ",
sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
}
printf ("%sternal PCI arbiter enabled\n",
(mfdcr(strap) & PSR_PCI_ARBIT_EN) ? "in" : "ex");
#elif defined(CONFIG_405EP)
printf (" IIC Boot EEPROM %sabled\n",
(mfdcr(cpc0_boot) & CPC0_BOOT_SEP) ? "en" : "dis");
printf (" PCI async ext clock used, ");
printf ("%sternal PCI arbiter enabled\n",
(mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) ? "in" : "ex");
#endif
#if defined(CONFIG_405EP)
printf (" 16 kB I-Cache 16 kB D-Cache");
#else
printf (" 16 kB I-Cache %d kB D-Cache",
((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
#ifdef CONFIG_IOP480
printf ("PLX IOP480 (PVR=%08x)", pvr);
printf (" at %s MHz:", strmhz(buf, clock));
printf (" %u kB I-Cache", 4);
printf (" %u kB D-Cache", 2);
#endif
#if defined(CONFIG_440)
puts ("AMCC PowerPC 440");
switch(pvr) {
case PVR_440GP_RB:
puts("GP Rev. B");
/* See errata 1.12: CHIP_4 */
@ -166,40 +191,103 @@ int checkcpu (void)
mfdcr(cpc0_strp1) );
}
break;
case PVR_440GP_RC:
puts("GP Rev. C");
break;
case PVR_440GX_RA:
puts("GX Rev. A");
break;
case PVR_440GX_RB:
puts("GX Rev. B");
break;
case PVR_440GX_RC:
puts("GX Rev. C");
break;
case PVR_440GX_RF:
puts("GX Rev. F");
break;
case PVR_440EP_RA:
puts("EP Rev. A");
break;
#ifdef CONFIG_440EP
case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
puts("EP Rev. B");
break;
#endif /* CONFIG_440EP */
#ifdef CONFIG_440GR
case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
puts("GR Rev. A");
break;
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */
case PVR_440SP_RA:
puts("SP Rev. A");
break;
case PVR_440SP_RB:
puts("SP Rev. B");
break;
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;
}
printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
sys_info.freqPLB / 1000000,
sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
FREQ_EBC / 1000000);
#if defined(I2C_BOOTROM)
printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#endif
puts ("\n");
#if defined(CONFIG_PCI)
printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif
#if defined(PCI_ASYNC)
if (pci_async_enabled()) {
printf (", PCI async ext clock used");
} else {
printf (", PCI sync clock at %lu MHz",
sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
}
#endif
#if defined(CONFIG_PCI)
putc('\n');
#endif
#if defined(CONFIG_405EP)
printf (" 16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
printf (" 32 kB I-Cache 32 kB D-Cache");
#else
printf (" 16 kB I-Cache %d kB D-Cache",
((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* !defined(CONFIG_IOP480) */
#if defined(CONFIG_IOP480)
printf ("PLX IOP480 (PVR=%08x)", pvr);
printf (" at %s MHz:", strmhz(buf, clock));
printf (" %u kB I-Cache", 4);
printf (" %u kB D-Cache", 2);
#endif
#endif /* !defined(CONFIG_405) */
putc ('\n');
return 0;
}
@ -230,8 +318,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#if defined(CONFIG_440)
static
int do_chip_reset (unsigned long sys0, unsigned long sys1)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
/* Changes to cpc0_sys0 and cpc0_sys1 require chip
* reset.
@ -252,31 +339,13 @@ int do_chip_reset (unsigned long sys0, unsigned long sys1)
*/
unsigned long get_tbclk (void)
{
#if defined(CONFIG_440)
#if !defined(CONFIG_IOP480)
sys_info_t sys_info;
get_sys_info(&sys_info);
return (sys_info.freqProcessor);
#elif defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_405) || \
defined(CONFIG_405EP)
PPC405_SYS_INFO sys_info;
get_sys_info(&sys_info);
return (sys_info.freqProcessor);
#elif defined(CONFIG_IOP480)
return (66000000);
#else
# error get_tbclk() not implemented
return (66000000);
#endif
}

2
cpu/ppc4xx/miiphy.c
View File

@ -104,7 +104,7 @@ int phy_setup_aneg (char *devname, unsigned char addr)
/***********************************************************/
unsigned int miiphy_getemac_offset (void)
{
#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI)
unsigned long zmii;
unsigned long eoffset;

15
cpu/ppc4xx/serial.c
View File

@ -276,7 +276,12 @@ int serial_tstc ()
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440SP)
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
@ -306,14 +311,14 @@ int serial_tstc ()
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#endif /* CONFIG_440GX */
@ -436,7 +441,7 @@ int serial_init(void)
unsigned long tmp;
#endif
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mfsdr(UART0_SDR,reg);
@ -465,7 +470,7 @@ int serial_init(void)
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {

2
cpu/ppc4xx/speed.c
View File

@ -283,7 +283,7 @@ ulong get_PCI_freq (void)
return sys_info.freqPCI;
}
#elif !defined(CONFIG_440GX)
#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;

20
cpu/ppc4xx/start.S
View File

@ -166,7 +166,7 @@ _start_440:
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
#if defined (CONFIG_440GX) /* NOTE: 440GX adds machine check status regs */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */
mtspr mcsrr0,r0
mtspr mcsrr1,r0
mfspr r1, mcsr
@ -394,7 +394,7 @@ __440gx_msr_continue:
addi r3,r3,32
bdnz ..d_ag
#else
#if defined (CONFIG_440GX)
#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
@ -409,7 +409,7 @@ __440gx_msr_continue:
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
ori r1,r1,0x0980 /* first 64k */
mtdcr isram0_sb0cr,r1
lis r1,0x8001
@ -432,7 +432,6 @@ __440gx_msr_continue:
/*----------------------------------------------------------------*/
lis r1,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET@l
li r0,0
stwu r0,-4(r1)
stwu r0,-4(r1) /* Terminate call chain */
@ -977,12 +976,8 @@ invalidate_icache:
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
#else
addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
#endif
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
@ -1003,15 +998,10 @@ flush_dcache:
mtdccr r10
/* do loop for # of congruence classes. */
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
#else
addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
#endif
mtctr r10
addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
@ -1233,9 +1223,9 @@ relocate_code:
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
addi r1,r0,0x0000 /* Tlb entry #0 */
addi r1,r0,0x0000 /* TLB entry #0 */
tlbre r0,r1,0x0002 /* Read contents */
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */
isync
#endif

30
cpu/ppc4xx/vecnum.h
View File

@ -31,7 +31,35 @@
#ifndef _VECNUMS_H_
#define _VECNUMS_H_
#if defined(CONFIG_440)
#if defined(CONFIG_440SP)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */
#define VECNUM_U1 1 /* UART1 */
#define VECNUM_IIC0 2 /* IIC0 */
#define VECNUM_IIC1 3 /* IIC1 */
#define VECNUM_PIM 4 /* PCI inbound message */
#define VECNUM_PCRW 5 /* PCI command reg write */
#define VECNUM_PPM 6 /* PCI power management */
#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
/* UIC 1 */
#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
#define VECNUM_MS (32 + 1) /* MAL SERR */
#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
#elif defined(CONFIG_440)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */

2
include/asm-ppc/processor.h
View File

@ -731,6 +731,8 @@
#define PVR_440GX_RC 0x51B21892
#define PVR_440GX_RF 0x51B21894
#define PVR_405EP_RB 0x51210950
#define PVR_440SP_RA 0x53221850
#define PVR_440SP_RB 0x53221891
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000

464
include/configs/TQM8540.h
View File

@ -1,464 +0,0 @@
/*
* Copyright 2005 DENX Software Engineering
* Wolfgang Denk <wd@denx.de>
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* TQM8540 board configuration file
*
* Make sure you change the MAC address and other network params first,
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_MPC8540 1 /* MPC8540 specific */
#define CONFIG_TQM8540 1 /* TQM8540 board specific */
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/*
* sysclk for MPC85xx
*
* Two valid values are:
* 33000000
* 66000000
*
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
* is likely the desired value here, so that is now the default.
* The board, however, can run at 66MHz. In any event, this value
* must match the settings of some switches. Details can be found
* in the README.mpc85xxads.
*/
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 33333333
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x10000000
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#else
/*
* Manually set up DDR parameters
*/
#define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
#define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
#define CFG_DDR_CS0_CONFIG 0x80000102
#define CFG_DDR_TIMING_1 0x47445331
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
#endif
/*
* Flash on the Local Bus
*/
#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
*/
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
| CFG_LBC_LSDMR_RFCR5 \
| CFG_LBC_LSDMR_PRETOACT3 \
| CFG_LBC_LSDMR_ACTTORW3 \
| CFG_LBC_LSDMR_BL8 \
| CFG_LBC_LSDMR_WRC2 \
| CFG_LBC_LSDMR_CL3 \
| CFG_LBC_LSDMR_RFEN \
)
/*
* SDRAM Controller configuration sequence.
*/
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL)
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/* I2C EEPROM */
/*
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
*/
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
/* Options are TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC1"
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#if defined(CFG_RAMBOOT)
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
#else
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_NFS | \
CFG_CMD_SNTP )
#endif
#if defined(CONFIG_PCI)
# define ADD_PCI_CMD (CFG_CMD_PCI)
#else
# define ADD_PCI_CMD 0
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
ADD_PCI_CMD | \
CFG_CMD_I2C | \
CFG_CMD_DATE | \
CFG_CMD_EEPROM | \
CFG_CMD_DTT | \
CFG_CMD_MII | \
CFG_CMD_PING )
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
":$hostname:$netdev:off panic=1\0" \
"addcons=setenv bootargs $bootargs " \
"console=$consdev,$baudrate\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm $kernel_addr\0" \
"flash_self=run ramargs addip addcons;" \
"bootm $kernel_addr $ramdisk_addr\0" \
"net_nfs=tftp $loadaddr $bootfile;" \
"run nfsargs addip addcons;bootm\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"bootfile=/tftpboot/tqm8540/uImage\0" \
"kernel_addr=FE000000\0" \
"ramdisk_addr=FE100000\0" \
"load=tftp 100000 /tftpboot/tqm8540/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#endif /* __CONFIG_H */

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include/configs/TQM8560.h
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@ -1,473 +0,0 @@
/*
* Copyright 2005 DENX Software Engineering
* Wolfgang Denk <wd@denx.de>
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* TQM8560 board configuration file
*
* Make sure you change the MAC address and other network params first,
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8560 1 /* MPC8560 specific */
#define CONFIG_TQM8560 1 /* TQM8560 board specific */
/*
* BIG FAT WARNING: Right now PCI seems to have a problem on the
* TQM8560 on the Starter Kit. So, if the board doen't come up
* please disable the PCI support for now. sr@denx.de, 15-09-2005
*/
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/*
* sysclk for MPC85xx
*
* Two valid values are:
* 33000000
* 66000000
*
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
* is likely the desired value here, so that is now the default.
* The board, however, can run at 66MHz. In any event, this value
* must match the settings of some switches. Details can be found
* in the README.mpc85xxads.
*/
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 33333333
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x10000000
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#else
/*
* Manually set up DDR parameters
*/
#define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
#define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
#define CFG_DDR_CS0_CONFIG 0x80000102
#define CFG_DDR_TIMING_1 0x47445331
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
#endif
/*
* Flash on the Local Bus
*/
#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
*/
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
| CFG_LBC_LSDMR_RFCR5 \
| CFG_LBC_LSDMR_PRETOACT3 \
| CFG_LBC_LSDMR_ACTTORW3 \
| CFG_LBC_LSDMR_BL8 \
| CFG_LBC_LSDMR_WRC2 \
| CFG_LBC_LSDMR_CL3 \
| CFG_LBC_LSDMR_RFEN \
)
/*
* SDRAM Controller configuration sequence.
*/
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL)
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/* I2C EEPROM */
/*
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
*/
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
/* Options are TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */
#define CONFIG_ETHER_ON_FCC
#define CONFIG_ETHER_ON_FCC3
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
/*
* Environment
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#if defined(CFG_RAMBOOT)
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
#else
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_NFS | \
CFG_CMD_SNTP )
#endif
#if defined(CONFIG_PCI)
# define ADD_PCI_CMD (CFG_CMD_PCI)
#else
# define ADD_PCI_CMD 0
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
ADD_PCI_CMD | \
CFG_CMD_I2C | \
CFG_CMD_DATE | \
CFG_CMD_EEPROM | \
CFG_CMD_DTT | \
CFG_CMD_MII | \
CFG_CMD_PING )
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
":$hostname:$netdev:off panic=1\0" \
"addcons=setenv bootargs $bootargs " \
"console=$consdev,$baudrate\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm $kernel_addr\0" \
"flash_self=run ramargs addip addcons;" \
"bootm $kernel_addr $ramdisk_addr\0" \
"net_nfs=tftp $loadaddr $bootfile;" \
"run nfsargs addip addcons;bootm\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"bootfile=/tftpboot/tqm8560/uImage\0" \
"kernel_addr=FE000000\0" \
"ramdisk_addr=FE100000\0" \
"load=tftp 100000 /tftpboot/tqm8560/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#endif /* __CONFIG_H */

452
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/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Wolfgang Denk <wd@denx.de>
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* TQM85xx (8560/40/55/41) board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
/*
* Only MPC8540 doesn't have CPM module
*/
#ifndef CONFIG_MPC8540
#define CONFIG_CPM2 1 /* has CPM2 */
#endif
/*
* sysclk for MPC85xx
*
* Two valid values are:
* 33000000
* 66000000
*
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
* is likely the desired value here, so that is now the default.
* The board, however, can run at 66MHz. In any event, this value
* must match the settings of some switches. Details can be found
* in the README.mpc85xxads.
*/
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 33333333
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00000000
#define CFG_MEMTEST_END 0x10000000
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
#define CONFIG_DDR_DLL /* DLL fix needed */
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
/*
* Flash on the Local Bus
*/
#define CFG_FLASH0 0xFC000000
#define CFG_FLASH1 0xF8000000
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
#define CFG_FLASH_CFI /* flash is CFI compat. */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#if defined(CONFIG_TQM8560)
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
#else
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#endif /* CONFIG_TQM8560 */
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/* I2C EEPROM */
/*
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
*/
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
/* Options are TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC0"
#if defined(CONFIG_TQM8540)
/*
* TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
* The FEC port is connected on the same signals as the FCC3 port
* of the TQM8560 to the baseboard (STK85xx Starterkit).
*
* On the STK85xx Starterkit the X47/X50 jumper has to be set to
* a - d (X50.2 - 3) to enable the FEC port.
*/
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#endif
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
/*
* TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
* can be used at once, since only one FCC port is available on the STK85xx
* Starterkit.
*
* To use this port you have to configure U-Boot to use the FCC port 1...2
* and set the X47/X50 jumper to:
* FCC1: a - b (X47.2 - X50.2)
* FCC2: a - c (X50.2 - 1)
*/
#define CONFIG_ETHER_ON_FCC
#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
#endif
#if defined(CONFIG_TQM8560)
/*
* TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
* can be used at once, since only one FCC port is available on the STK85xx
* Starterkit.
*
* To use this port you have to configure U-Boot to use the FCC port 1...3
* and set the X47/X50 jumper to:
* FCC1: a - b (X47.2 - X50.2)
* FCC2: a - c (X50.2 - 1)
* FCC3: a - d (X50.2 - 3)
*/
#define CONFIG_ETHER_ON_FCC
#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
#endif
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
#define CONFIG_ETHER_ON_FCC1
#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#endif
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
#define CONFIG_ETHER_ON_FCC2
#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#endif
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
#define CONFIG_ETHER_ON_FCC3
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#endif
/*
* Environment
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_TIMESTAMP /* Print image info with ts */
#if defined(CONFIG_PCI)
# define ADD_PCI_CMD (CFG_CMD_PCI)
#else
# define ADD_PCI_CMD 0
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_NFS | \
CFG_CMD_SNTP | \
ADD_PCI_CMD | \
CFG_CMD_I2C | \
CFG_CMD_DATE | \
CFG_CMD_EEPROM | \
CFG_CMD_DTT | \
CFG_CMD_MII | \
CFG_CMD_PING )
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
":$hostname:$netdev:off panic=1\0" \
"addcons=setenv bootargs $bootargs " \
"console=$consdev,$baudrate\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm $kernel_addr\0" \
"flash_self=run ramargs addip addcons;" \
"bootm $kernel_addr $ramdisk_addr\0" \
"net_nfs=tftp $loadaddr $bootfile;" \
"run nfsargs addip addcons;bootm\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"kernel_addr=FE000000\0" \
"ramdisk_addr=FE100000\0" \
"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#endif /* __CONFIG_H */

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* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

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/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
* John Otken, jotken@softadvances.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* luan.h - configuration for LUAN board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_LUAN 1 /* Board is Luan */
#define CONFIG_440SP 1 /* Specific PPC440SP support */
#define CONFIG_4xx 1 /* PPC4xx family */
#define CONFIG_440 1
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */
#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
#if CFG_LARGE_FLASH == 0xffc00000
#define CFG_FLASH_BASE CFG_LARGE_FLASH
#else
#define CFG_FLASH_BASE CFG_SMALL_FLASH
#endif
#undef CFG_DRAM_TEST
#if CFG_SRAM_BASE
#define CFG_KBYTES_SDRAM 1024*2
#else
#define CFG_KBYTES_SDRAM 1024
#endif
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#undef CONFIG_SERIAL_MULTI
#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
/*
* Define here the location of the environment variables (FLASH or EEPROM).
* Note: DENX encourages to use redundant environment in FLASH.
*/
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_ADDR0 0x555
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */
#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */
#define IIC0_DIMM0_ADDR 0x52
#define IIC0_DIMM1_ADDR 0x53
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=luan\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/luan/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc100000\0" \
"load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* needed for NetConsole */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_CACHE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SETGETDCR | \
CFG_CMD_SDRAM | \
0)
/* this must be included AFTER the definition of CONFIG_COMMANDS */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#undef CONFIG_LYNXKDI /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#if (CONFIG_COMMANDS & CFG_CMD_PCI)
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#undef CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

223
include/ppc440.h
View File

@ -78,7 +78,7 @@
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
@ -178,7 +178,6 @@
#define sdr_plbtr 0x4200
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
/*-----------------------------------------------------------------------------
| SDRAM Controller
+----------------------------------------------------------------------------*/
@ -504,7 +503,7 @@
/*-----------------------------------------------------------------------------
| L2 Cache
+----------------------------------------------------------------------------*/
#if defined (CONFIG_440GX)
#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
@ -527,7 +526,7 @@
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
#define CNTRL_DCR_BASE 0x0b0
#if defined (CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
@ -690,6 +689,40 @@
/*---------------------------------------------------------------------------+
| Universal interrupt controller 0 interrupts (UIC0)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440SP)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_IIC1 0x10000000 /* IIC */
#define UIC_PIM 0x08000000 /* PCI0 inbound message */
#define UIC_PCRW 0x04000000 /* PCI0 command write register */
#define UIC_PPM 0x02000000 /* PCI0 power management */
#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
#define UIC_P1CRW 0x00200000 /* PCI1 command write register */
#define UIC_P1PM 0x00100000 /* PCI1 power management */
#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
#define UIC_P2IM 0x00020000 /* PCI2 inbound message */
#define UIC_P2CRW 0x00010000 /* PCI2 command register write */
#define UIC_P2PM 0x00008000 /* PCI2 power management */
#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
#define UIC_D0CSF 0x00000800 /* DMA0 command status */
#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
#define UIC_D1CSF 0x00000200 /* DMA1 command status */
#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
#define UIC_GPTCT 0x00000004 /* GPT count timer */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
#else /* CONFIG_440SP */
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
@ -722,6 +755,7 @@
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
#endif /* CONFIG_440SP */
/* For compatibility with 405 code */
#define UIC_MAL_TXEOB UIC_MTE
@ -730,6 +764,40 @@
/*---------------------------------------------------------------------------+
| Universal interrupt controller 1 interrupts (UIC1)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440SP)
#define UIC_EIR0 0x80000000 /* External interrupt 0 */
#define UIC_MS 0x40000000 /* MAL SERR */
#define UIC_MTDE 0x20000000 /* MAL TXDE */
#define UIC_MRDE 0x10000000 /* MAL RXDE */
#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
#define UIC_MTE 0x02000000 /* MAL TXEOB */
#define UIC_MRE 0x01000000 /* MAL RXEOB */
#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
#define UIC_L2C 0x00100000 /* L2 cache */
#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
#define UIC_EIR1 0x00004000 /* External interrupt 1 */
#define UIC_EIR2 0x00002000 /* External interrupt 2 */
#define UIC_EIR3 0x00001000 /* External interrupt 3 */
#define UIC_EIR4 0x00000800 /* External interrupt 4 */
#define UIC_EIR5 0x00000400 /* External interrupt 5 */
#define UIC_DMAE 0x00000200 /* DMA error */
#define UIC_I2OE 0x00000100 /* I2O error */
#define UIC_SRE 0x00000080 /* Serial ROM error */
#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
#define UIC_ETH0 0x00000008 /* Ethernet 0 */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Reserved */
#define UIC_XOR 0x00000001 /* XOR */
#else /* CONFIG_440SP */
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
@ -762,6 +830,7 @@
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Ethernet 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
#endif /* CONFIG_440SP */
/* For compatibility with 405 code */
#define UIC_MAL_SERR UIC_MS
@ -850,6 +919,11 @@
#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
#define EBC_BXAP_BCE_DISABLE 0x00000000
#define EBC_BXAP_BCE_ENABLE 0x00400000
#define EBC_BXAP_BCT_MASK 0x00300000
#define EBC_BXAP_BCT_2TRANS 0x00000000
#define EBC_BXAP_BCT_4TRANS 0x00100000
#define EBC_BXAP_BCT_8TRANS 0x00200000
#define EBC_BXAP_BCT_16TRANS 0x00300000
#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
@ -905,133 +979,22 @@
#define EBC_CFG_PR_128 0x0000C000
/*-----------------------------------------------------------------------------+
| SDR 0 Bit Settings
| SDR0 Bit Settings
+-----------------------------------------------------------------------------*/
#define SDR0_SDSTP0_ENG_MASK 0x80000000
#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
#define SDR0_SDSTP0_SRC_MASK 0x40000000
#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
#define SDR0_SDSTP0_SEL_MASK 0x38000000
#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
#define SDR0_SDSTP0_SEL_CPU 0x08000000
#define SDR0_SDSTP0_SEL_EBC 0x28000000
#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
#define SDR0_SDCS_SDD (0x80000000 >> 31)
#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
#define SDR0_SDSTP1_EBCDV0_MASK 0x03000000
#define SDR0_SDSTP1_EBCDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define SDR0_SDSTP1_EBCDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
#define SDR0_SDSTP1_RW_MASK 0x00300000
#define SDR0_SDSTP1_RW_8BIT 0x00000000
#define SDR0_SDSTP1_RW_16BIT 0x00100000
#define SDR0_SDSTP1_RW_32BIT 0x00200000
#define SDR0_SDSTP1_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
#define SDR0_SDSTP1_RW_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
#define SDR0_SDSTP1_EARV_MASK 0x00080000
#define SDR0_SDSTP1_EARV_EBC 0x00000000
#define SDR0_SDSTP1_EARV_PCI 0x00080000
#define SDR0_SDSTP1_PAE_MASK 0x00040000
#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
#define SDR0_SDSTP1_PHCE_MASK 0x00020000
#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
#define SDR0_SDSTP1_PISE_MASK 0x00010000
#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
#define SDR0_SDSTP1_PISE_ENABLE 0x00010000
#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
#define SDR0_SDSTP1_PCWE_MASK 0x00008000
#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
#define SDR0_SDSTP1_PPIM_MASK 0x00008000
#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
#define SDR0_SDSTP1_PR64E_MASK 0x00000400
#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
#define SDR0_SDSTP1_PXFS_MASK 0x00000300
#define SDR0_SDSTP1_PXFS_HIGH 0x00000000
#define SDR0_SDSTP1_PXFS_MED 0x00000100
#define SDR0_SDSTP1_PXFS_LOW 0x00000200
#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
#define SDR0_SDSTP1_PDM_MASK 0x00000040
#define SDR0_SDSTP1_PDM_MULTIPOINT 0x00000000
#define SDR0_SDSTP1_PDM_P2P 0x00000040
#define SDR0_SDSTP1_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<6)
#define SDR0_SDSTP1_PDM_DECODE(n) ((((unsigned long)(n))>>6)&0x01)
#define SDR0_SDSTP1_EPS_MASK 0x00000038
#define SDR0_SDSTP1_EPS_GROUP0 0x00000000
#define SDR0_SDSTP1_EPS_GROUP1 0x00000008
#define SDR0_SDSTP1_EPS_GROUP2 0x00000010
#define SDR0_SDSTP1_EPS_GROUP3 0x00000018
#define SDR0_SDSTP1_EPS_GROUP4 0x00000020
#define SDR0_SDSTP1_EPS_GROUP5 0x00000028
#define SDR0_SDSTP1_EPS_GROUP6 0x00000030
#define SDR0_SDSTP1_EPS_GROUP7 0x00000038
#define SDR0_SDSTP1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<3)
#define SDR0_SDSTP1_EPS_DECODE(n) ((((unsigned long)(n))>>3)&0x07)
#define SDR0_SDSTP1_RMII_MASK 0x00000004
#define SDR0_SDSTP1_RMII_100MBIT 0x00000000
#define SDR0_SDSTP1_RMII_10MBIT 0x00000004
#define SDR0_SDSTP1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
#define SDR0_SDSTP1_RMII_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
#define SDR0_SDSTP1_TRE_MASK 0x00000002
#define SDR0_SDSTP1_TRE_DISABLE 0x00000000
#define SDR0_SDSTP1_TRE_ENABLE 0x00000002
#define SDR0_SDSTP1_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
#define SDR0_SDSTP1_TRE_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
#define SDR0_SDSTP1_NTO1_MASK 0x00000001
#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
#define SDR0_EBC_RW_MASK 0x30000000
#define SDR0_EBC_RW_8BIT 0x00000000
#define SDR0_EBC_RW_16BIT 0x10000000
#define SDR0_EBC_RW_32BIT 0x20000000
#define SDR0_EBC_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
#define SDR0_EBC_RW_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
#if defined(CONFIG_440GP)
#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
#endif /* defined(CONFIG_440GP) */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#define SDR0_UARTX_UXICS_MASK 0xF0000000
#define SDR0_UARTX_UXICS_PLB 0x20000000
@ -1196,7 +1159,7 @@
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */

6
include/ppc4xx_enet.h
View File

@ -131,7 +131,9 @@ typedef struct emac_4xx_hw_st {
#if defined(CONFIG_440GX)
#define EMAC_NUM_DEV 4
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && defined(CONFIG_NET_MULTI)
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
defined(CONFIG_NET_MULTI) && \
!defined(CONFIG_440SP)
#define EMAC_NUM_DEV 2
#else
#define EMAC_NUM_DEV 1
@ -321,7 +323,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)

10
lib_ppc/board.c
View File

@ -197,6 +197,10 @@ static int init_baudrate (void)
/***********************************************************************/
#ifdef CONFIG_ADD_RAM_INFO
void board_add_ram_info(int);
#endif
static int init_func_ram (void)
{
#ifdef CONFIG_BOARD_TYPES
@ -207,7 +211,11 @@ static int init_func_ram (void)
puts ("DRAM: ");
if ((gd->ram_size = initdram (board_type)) > 0) {
print_size (gd->ram_size, "\n");
print_size (gd->ram_size, "");
#ifdef CONFIG_ADD_RAM_INFO
board_add_ram_info(0);
#endif
putc('\n');
return (0);
}
puts (failed);

6
net/eth.c
View File

@ -162,9 +162,6 @@ int eth_initialize(bd_t *bis)
#ifdef SCC_ENET
scc_initialize(bis);
#endif
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
#endif
#if defined(CONFIG_MPC5xxx_FEC)
mpc5xxx_fec_initialize(bis);
#endif
@ -198,6 +195,9 @@ int eth_initialize(bd_t *bis)
tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
# endif
#endif
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
#endif
#if defined(CONFIG_AU1X00)
au1x00_enet_initialize(bis);
#endif