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ColdFire: Add M5235EVB Platform for MCF523x 

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew 2007-08-16 19:23:50 -05:00 committed by John Rigby
parent 8ae158cd87
commit 4a442d3186
22 changed files with 3303 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
CREDITS
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@ -491,7 +491,7 @@ W: www.monstr.eu
N: TsiChung Liew
E: Tsi-Chung.Liew@freescale.com
D: Support for ColdFire MCF532x, MCF5445x
D: Support for ColdFire MCF523x, MCF532x, MCF5445x
W: www.freescale.com
N: Hayden Fraser

1
MAINTAINERS
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@ -608,6 +608,7 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com>
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M5235EVB mcf52x2
M5329EVB mcf532x
M54455EVB mcf5445x

1
MAKEALL
View File

@ -618,6 +618,7 @@ LIST_coldfire=" \
EB+MCF-EV123 \
EB+MCF-EV123_internal \
idmr \
M5235EVB \
M5249EVB \
M5253EVB \
M5271EVB \

25
Makefile
View File

@ -1639,6 +1639,25 @@ ZPC1900_config: unconfig
## Coldfire
#########################################################################
M5235EVB_config \
M5235EVB_Flash16_config \
M5235EVB_Flash32_config: unconfig
@case "$@" in \
M5235EVB_config) FLASH=16;; \
M5235EVB_Flash16_config) FLASH=16;; \
M5235EVB_Flash32_config) FLASH=32;; \
esac; \
>include/config.h ; \
if [ "$${FLASH}" != "16" ] ; then \
echo "#define NORFLASH_PS32BIT 1" >> include/config.h ; \
echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \
else \
echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \
fi
@$(MKCONFIG) -a M5235EVB m68k mcf523x m5235evb freescale
M5249EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
@ -1710,13 +1729,13 @@ M54455EVB_i66_config : unconfig
esac; \
>include/config.h ; \
if [ "$${FLASH}" == "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> include/config.h ; \
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "... with INTEL boot..." ; \
else \
echo "#define CFG_ATMEL_BOOT" >> include/config.h ; \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "... with ATMEL boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >>include/config.h ; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
echo "... with $${FREQ}Hz input clock"
@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale

44
board/freescale/m5235evb/Makefile Normal file
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@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

28
board/freescale/m5235evb/config.mk Normal file
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@ -0,0 +1,28 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
/*TEXT_BASE = 0xFFC00000*/
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

117
board/freescale/m5235evb/m5235evb.c Normal file
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@ -0,0 +1,117 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M5235 EVB\n");
return 0;
};
long int initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 dramsize, i, dramclk;
/*
* When booting from external Flash, the port-size is less than
* the port-size of SDRAM. In this case it is necessary to enable
* Data[15:0] on Port Address/Data.
*/
gpio->par_ad =
GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
GPIO_PAR_AD_DATAL;
/* Initialize PAR to enable SDRAM signals */
gpio->par_sdram =
GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
dramsize = CFG_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
/* Initialize DRAM Control Register: DCR */
sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
/* Initialize DACR0 */
sdram->dacr0 =
SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
/* Initialize DMR0 */
sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
/* Set IP (bit 3) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_IP;
/* Wait 30ns to allow banks to precharge */
for (i = 0; i < 5; i++) {
asm("nop");
}
/* Write to this block to initiate precharge */
*(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_RE;
/* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 0x2000; i++) {
asm("nop");
}
/* Finish the configuration by issuing the MRS. */
sdram->dacr0 |= SDRAMC_DARCn_IMRS;
/* Write to the SDRAM Mode Register */
*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

307
board/freescale/m5235evb/mii.c Normal file
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@ -0,0 +1,307 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
}
return 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
#define STR_ID_KS8721BL "KS8721BL"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
strcpy(info->phy_name,
STR_ID_KS8721BL);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
printf(STR_ID_KS8721BL);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

145
board/freescale/m5235evb/u-boot.16 Normal file
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@ -0,0 +1,145 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf523x/start.o (.text)
cpu/mcf523x/cpu_init.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

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board/freescale/m5235evb/u-boot.32 Normal file
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@ -0,0 +1,153 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf523x/start.o (.text)
cpu/mcf523x/cpu.o (.text)
cpu/mcf523x/cpu_init.o (.text)
cpu/mcf523x/interrupts.o (.text)
cpu/mcf523x/speed.o (.text)
lib_m68k/libm68k.a (.text)
common/dlmalloc.o (.text)
common/cmd_bootm.o (.text)
common/cmd_flash.o (.text)
common/cmd_elf.o (.text)
common/cmd_mem.o (.text)
common/console.o (.text)
common/main.o (.text)
lib_generic/libgeneric.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

145
board/freescale/m5235evb/u-boot.lds Normal file
View File

@ -0,0 +1,145 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf523x/start.o (.text)
cpu/mcf523x/cpu_init.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

48
cpu/mcf523x/Makefile Normal file
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@ -0,0 +1,48 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
# CFLAGS += -DET_DEBUG
LIB = lib$(CPU).a
START = start.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

27
cpu/mcf523x/config.mk Normal file
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#
# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
PLATFORM_CPPFLAGS += -m5307 -fPIC

109
cpu/mcf523x/cpu.c Normal file
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@ -0,0 +1,109 @@
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
ccm->rcr = CCM_RCR_SOFTRST;
/* we don't return! */
return 0;
};
int checkcpu(void)
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
msk = (ccm->cir >> 6);
ver = (ccm->cir & 0x003f);
switch (msk) {
case 0x31:
id = 5235;
break;
}
if (id) {
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n",
(int)(gd->cpu_clk / 1000000),
(int)(gd->bus_clk / 1000000));
}
return 0;
};
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdp->sr = 0x5555; /* Count register */
asm("nop");
wdp->sr = 0xAAAA; /* Count register */
}
int watchdog_disable(void)
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
puts("WATCHDOG:disabled\n");
return (0);
}
int watchdog_init(void)
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CFG_CLK / CFG_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module |= (wdog_module / 8192);
wdp->mr = wdog_module;
wdp->cr = WTM_WCR_EN;
puts("WATCHDOG:enabled\n");
return (0);
}
#endif /* CONFIG_WATCHDOG */

145
cpu/mcf523x/cpu_init.c Normal file
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/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
volatile scm_t *scm = (scm_t *) MMAP_SCM;
/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
wdog->cr = 0;
#endif
scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
gpio->par_cs = 0;
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
fbcs->csar0 = CFG_CS0_BASE;
fbcs->cscr0 = CFG_CS0_CTRL;
fbcs->csmr0 = CFG_CS0_MASK;
#endif
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS1;
fbcs->csar1 = CFG_CS1_BASE;
fbcs->cscr1 = CFG_CS1_CTRL;
fbcs->csmr1 = CFG_CS1_MASK;
#endif
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS2;
fbcs->csar2 = CFG_CS2_BASE;
fbcs->cscr2 = CFG_CS2_CTRL;
fbcs->csmr2 = CFG_CS2_MASK;
#endif
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS3;
fbcs->csar3 = CFG_CS3_BASE;
fbcs->cscr3 = CFG_CS3_CTRL;
fbcs->csmr3 = CFG_CS3_MASK;
#endif
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS4;
fbcs->csar4 = CFG_CS4_BASE;
fbcs->cscr4 = CFG_CS4_CTRL;
fbcs->csmr4 = CFG_CS4_MASK;
#endif
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS5;
fbcs->csar5 = CFG_CS5_BASE;
fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK;
#endif
#if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS6;
fbcs->csar6 = CFG_CS6_BASE;
fbcs->cscr6 = CFG_CS6_CTRL;
fbcs->csmr6 = CFG_CS6_MASK;
#endif
#if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL))
gpio->par_cs |= GPIO_PAR_CS_CS7;
fbcs->csar7 = CFG_CS7_BASE;
fbcs->cscr7 = CFG_CS7_CTRL;
fbcs->csmr7 = CFG_CS7_MASK;
#endif
#ifdef CONFIG_FSL_I2C
gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK);
gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA);
#endif
icache_enable();
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r(void)
{
return (0);
}
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
case 0:
gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
break;
case 1:
gpio->par_uart =
(GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
break;
case 2:
gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
break;
}
}

49
cpu/mcf523x/interrupts.c Normal file
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@ -0,0 +1,49 @@
/*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrl0 |= 0x1;
enable_interrupts();
return 0;
}
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
intp->imrl0 &= ~INTC_IPRL_INT0;
intp->imrl0 &= ~CFG_TMRINTR_MASK;
}
#endif

48
cpu/mcf523x/speed.c Normal file
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/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks(void)
{
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
pll->syncr = PLL_SYNCR_MFD(1);
while (!(pll->synsr & PLL_SYNSR_LOCK));
gd->bus_clk = CFG_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
return (0);
}

340
cpu/mcf523x/start.S Normal file
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/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@;
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte;
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
INITSP: .long 0x00000000 /* Initial SP */
INITPC: .long _START /* Initial PC */
vector02: .long _FAULT /* Access Error */
vector03: .long _FAULT /* Address Error */
vector04: .long _FAULT /* Illegal Instruction */
vector05: .long _FAULT /* Reserved */
vector06: .long _FAULT /* Reserved */
vector07: .long _FAULT /* Reserved */
vector08: .long _FAULT /* Privilege Violation */
vector09: .long _FAULT /* Trace */
vector0A: .long _FAULT /* Unimplemented A-Line */
vector0B: .long _FAULT /* Unimplemented F-Line */
vector0C: .long _FAULT /* Debug Interrupt */
vector0D: .long _FAULT /* Reserved */
vector0E: .long _FAULT /* Format Error */
vector0F: .long _FAULT /* Unitialized Int. */
/* Reserved */
vector10_17:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector18: .long _FAULT /* Spurious Interrupt */
vector19: .long _FAULT /* Autovector Level 1 */
vector1A: .long _FAULT /* Autovector Level 2 */
vector1B: .long _FAULT /* Autovector Level 3 */
vector1C: .long _FAULT /* Autovector Level 4 */
vector1D: .long _FAULT /* Autovector Level 5 */
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector30_3F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector64_127:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector128_191:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.text
.globl _start
_start:
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
move.l #CFG_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
nop
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
/* initialize general use internal ram */
move.l #0, %d0
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
move.l %d0, (%a1)
move.l %d0, (%a2)
/* set stackpointer to end of internal ram to get some stackspace for the
first c-code */
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
bsr cpu_init_f /* run low-level CPU init code (from flash) */
bsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CFG_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CFG_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CFG_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CFG_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CFG_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/*------------------------------------------------------------------------------*/
/* exception code */
.globl _fault
_fault:
jmp _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/*------------------------------------------------------------------------------*/
/* cache functions */
.globl icache_enable
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
nop
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #(CFG_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80400100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
.globl icache_disable
icache_disable:
move.l #0x00000100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Disable cache */
clr.l %d0 /* Setup cache mask */
movec %d0, %ACR0
movec %d0, %ACR1
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl icache_status
icache_status:
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
move.l (%a1), %d0
rts
.globl icache_invalid
icache_invalid:
move.l #0x80600100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
rts
.globl dcache_enable
dcache_enable:
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
/* No dcache, just a dummy function */
.globl dcache_disable
dcache_disable:
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl dcache_status
dcache_status:
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
move.l (%a1), %d0
rts
/*------------------------------------------------------------------------------*/
.globl version_string
version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"

29
include/asm-m68k/immap.h
View File

@ -26,6 +26,35 @@
#ifndef __IMMAP_H
#define __IMMAP_H
#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>
#define CFG_FEC0_IOBASE (MMAP_FEC)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR3)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5235 */
#ifdef CONFIG_M5249
#include <asm/immap_5249.h>
#include <asm/m5249.h>

378
include/asm-m68k/immap_5235.h Normal file
View File

@ -0,0 +1,378 @@
/*
* MCF5329 Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5235__
#define __IMMAP_5235__
#define MMAP_SCM (CFG_MBAR + 0x00000000)
#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
#define MMAP_I2C (CFG_MBAR + 0x00000300)
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
#define MMAP_FEC (CFG_MBAR + 0x00001000)
#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
#define MMAP_CCM (CFG_MBAR + 0x00110000)
#define MMAP_PLL (CFG_MBAR + 0x00120000)
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
#define MMAP_MDHA (CFG_MBAR + 0x00190000)
#define MMAP_RNG (CFG_MBAR + 0x001A0000)
#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
/* System Control Module register */
typedef struct scm_ctrl {
u32 ipsbar; /* 0x00 - MBAR */
u32 res1; /* 0x04 */
u32 rambar; /* 0x08 - RAMBAR */
u32 res2; /* 0x0C */
u8 crsr; /* 0x10 Core Reset Status Register */
u8 cwcr; /* 0x11 Core Watchdog Control Register */
u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
u8 cwsr; /* 0x13 Core Watchdog Service Register */
u32 dmareqc; /* 0x14 */
u32 res3; /* 0x18 */
u32 mpark; /* 0x1C */
u8 mpr; /* 0x20 */
u8 res4[3]; /* 0x21 - 0x23 */
u8 pacr0; /* 0x24 */
u8 pacr1; /* 0x25 */
u8 pacr2; /* 0x26 */
u8 pacr3; /* 0x27 */
u8 pacr4; /* 0x28 */
u32 res5; /* 0x29 */
u8 pacr5; /* 0x2a */
u8 pacr6; /* 0x2b */
u8 pacr7; /* 0x2c */
u32 res6; /* 0x2d */
u8 pacr8; /* 0x2e */
u32 res7; /* 0x2f */
u8 gpacr; /* 0x30 */
u8 res8[3]; /* 0x31 - 0x33 */
} scm_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u16 dcr; /* 0x00 Control register */
u16 res1[3]; /* 0x02 - 0x07 */
u32 dacr0; /* 0x08 address and control register 0 */
u32 dmr0; /* 0x0C mask register block 0 */
u32 dacr1; /* 0x10 address and control register 1 */
u32 dmr1; /* 0x14 mask register block 1 */
} sdram_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
u8 podr_addr; /* 0x00 */
u8 podr_datah; /* 0x01 */
u8 podr_datal; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_bs; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_sdram; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
u8 podr_uarth; /* 0x08 */
u8 podr_uartl; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 podr_etpu; /* 0x0C */
u8 res1[3]; /* 0x0D - 0x0F */
/* Port Data Direction Registers */
u8 pddr_addr; /* 0x10 */
u8 pddr_datah; /* 0x11 */
u8 pddr_datal; /* 0x12 */
u8 pddr_busctl; /* 0x13 */
u8 pddr_bs; /* 0x14 */
u8 pddr_cs; /* 0x15 */
u8 pddr_sdram; /* 0x16 */
u8 pddr_feci2c; /* 0x17 */
u8 pddr_uarth; /* 0x18 */
u8 pddr_uartl; /* 0x19 */
u8 pddr_qspi; /* 0x1A */
u8 pddr_timer; /* 0x1B */
u8 pddr_etpu; /* 0x1C */
u8 res2[3]; /* 0x1D - 0x1F */
/* Port Data Direction Registers */
u8 ppdsdr_addr; /* 0x20 */
u8 ppdsdr_datah; /* 0x21 */
u8 ppdsdr_datal; /* 0x22 */
u8 ppdsdr_busctl; /* 0x23 */
u8 ppdsdr_bs; /* 0x24 */
u8 ppdsdr_cs; /* 0x25 */
u8 ppdsdr_sdram; /* 0x26 */
u8 ppdsdr_feci2c; /* 0x27 */
u8 ppdsdr_uarth; /* 0x28 */
u8 ppdsdr_uartl; /* 0x29 */
u8 ppdsdr_qspi; /* 0x2A */
u8 ppdsdr_timer; /* 0x2B */
u8 ppdsdr_etpu; /* 0x2C */
u8 res3[3]; /* 0x2D - 0x2F */
/* Port Clear Output Data Registers */
u8 pclrr_addr; /* 0x30 */
u8 pclrr_datah; /* 0x31 */
u8 pclrr_datal; /* 0x32 */
u8 pclrr_busctl; /* 0x33 */
u8 pclrr_bs; /* 0x34 */
u8 pclrr_cs; /* 0x35 */
u8 pclrr_sdram; /* 0x36 */
u8 pclrr_feci2c; /* 0x37 */
u8 pclrr_uarth; /* 0x38 */
u8 pclrr_uartl; /* 0x39 */
u8 pclrr_qspi; /* 0x3A */
u8 pclrr_timer; /* 0x3B */
u8 pclrr_etpu; /* 0x3C */
u8 res4[3]; /* 0x3D - 0x3F */
/* Pin Assignment Registers */
u8 par_ad; /* 0x40 */
u8 res5; /* 0x41 */
u16 par_busctl; /* 0x42 */
u8 par_bs; /* 0x44 */
u8 par_cs; /* 0x45 */
u8 par_sdram; /* 0x46 */
u8 par_feci2c; /* 0x47 */
u16 par_uart; /* 0x48 */
u8 par_qspi; /* 0x4A */
u8 res6; /* 0x4B */
u16 par_timer; /* 0x4C */
u8 par_etpu; /* 0x4E */
u8 res7; /* 0x4F */
/* Drive Strength Control Registers */
u8 dscr_eim; /* 0x50 */
u8 dscr_etpu; /* 0x51 */
u8 dscr_feci2c; /* 0x52 */
u8 dscr_uart; /* 0x53 */
u8 dscr_qspi; /* 0x54 */
u8 dscr_timer; /* 0x55 */
u16 res8; /* 0x56 */
} gpio_t;
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u8 rcr; /* 0x01 */
u8 rsr; /* 0x02 */
u16 res1; /* 0x03 */
u16 ccr; /* 0x04 Chip configuration register */
u16 lpcr; /* 0x06 Low-power Control register */
u16 rcon; /* 0x08 Rreset configuration register */
u16 cir; /* 0x0a Chip identification register */
} ccm_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u32 syncr; /* 0x00 synthesizer control register */
u32 synsr; /* 0x04 synthesizer status register */
} pll_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
u16 cr; /* 0x00 Control register */
u16 mr; /* 0x02 Modulus register */
u16 cntr; /* 0x04 Count register */
u16 sr; /* 0x06 Service register */
} wdog_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
#endif /* __IMMAP_5235__ */

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/*
* mcf5329.h -- Definitions for Freescale Coldfire 5329
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef mcf5235_h
#define mcf5235_h
/****************************************************************************/
/*********************************************************************
* System Control Module (SCM)
*********************************************************************/
/* Bit definition and macros for SCM_IPSBAR */
#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
#define SCM_IPSBAR_V (0x00000001)
/* Bit definition and macros for SCM_RAMBAR */
#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
#define SCM_RAMBAR_BDE (0x00000200)
/* Bit definition and macros for SCM_CRSR */
#define SCM_CRSR_EXT (0x80)
/* Bit definitions and macros for SCM_CWCR */
#define SCM_CWCR_CWE (0x80)
#define SCM_CWCR_CWRI (0x40)
#define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
#define SCM_CWCR_CWTA (0x04)
#define SCM_CWCR_CWTAVAL (0x02)
#define SCM_CWCR_CWTIC (0x01)
/* Bit definitions and macros for SCM_LPICR */
#define SCM_LPICR_ENBSTOP (0x80)
#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
#define SCM_LPICR_XLPM_IPL_ANY (0x00)
#define SCM_LPICR_XLPM_IPL_L2_7 (0x10)
#define SCM_LPICR_XLPM_IPL_L3_7 (0x20)
#define SCM_LPICR_XLPM_IPL_L4_7 (0x30)
#define SCM_LPICR_XLPM_IPL_L5_7 (0x40)
#define SCM_LPICR_XLPM_IPL_L6_7 (0x50)
#define SCM_LPICR_XLPM_IPL_L7 (0x70)
/* Bit definitions and macros for SCM_DMAREQC */
#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)
#define SCM_DMAREQC_EXT_ETPU (0x00080000)
#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)
#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)
#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)
#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)
#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)
#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)
#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))
#define SCM_DMAREQC_DMACn_DTMR0 (0x04)
#define SCM_DMAREQC_DMACn_DTMR1 (0x05)
#define SCM_DMAREQC_DMACn_DTMR2 (0x06)
#define SCM_DMAREQC_DMACn_DTMR3 (0x07)
#define SCM_DMAREQC_DMACn_UART0RX (0x08)
#define SCM_DMAREQC_DMACn_UART1RX (0x09)
#define SCM_DMAREQC_DMACn_UART2RX (0x0A)
#define SCM_DMAREQC_DMACn_UART0TX (0x0C)
#define SCM_DMAREQC_DMACn_UART1TX (0x0D)
#define SCM_DMAREQC_DMACn_UART3TX (0x0E)
/* Bit definitions and macros for SCM_MPARK */
#define SCM_MPARK_M2_P_EN (0x02000000)
#define SCM_MPARK_M3_PRTY_MSK (0x00C00000)
#define SCM_MPARK_M3_PRTY_4TH (0x00000000)
#define SCM_MPARK_M3_PRTY_3RD (0x00400000)
#define SCM_MPARK_M3_PRTY_2ND (0x00800000)
#define SCM_MPARK_M3_PRTY_1ST (0x00C00000)
#define SCM_MPARK_M2_PRTY_MSK (0x00300000)
#define SCM_MPARK_M2_PRTY_4TH (0x00000000)
#define SCM_MPARK_M2_PRTY_3RD (0x00100000)
#define SCM_MPARK_M2_PRTY_2ND (0x00200000)
#define SCM_MPARK_M2_PRTY_1ST (0x00300000)
#define SCM_MPARK_M0_PRTY_MSK (0x000C0000)
#define SCM_MPARK_M0_PRTY_4TH (0x00000000)
#define SCM_MPARK_M0_PRTY_3RD (0x00040000)
#define SCM_MPARK_M0_PRTY_2ND (0x00080000)
#define SCM_MPARK_M0_PRTY_1ST (0x000C0000)
#define SCM_MPARK_FIXED (0x00004000)
#define SCM_MPARK_TIMEOUT (0x00002000)
#define SCM_MPARK_PRKLAST (0x00001000)
#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)
/* Bit definitions and macros for SCM_MPR */
#define SCM_MPR_MPR3 (0x08)
#define SCM_MPR_MPR2 (0x04)
#define SCM_MPR_MPR1 (0x02)
#define SCM_MPR_MPR0 (0x01)
/* Bit definitions and macros for SCM_PACRn */
#define SCM_PACRn_LOCK1 (0x80)
#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)
#define SCM_PACRn_LOCK0 (0x08)
#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
/* Bit definitions and macros for SCM_GPACR */
#define SCM_PACRn_LOCK (0x80)
#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* Bit definitions and macros for SDRAMC_DCR */
#define SDRAMC_DCR_NAM (0x2000)
#define SDRAMC_DCR_COC (0x1000)
#define SDRAMC_DCR_IS (0x0800)
#define SDRAMC_DCR_RTIM_MASK (0x0C00)
#define SDRAMC_DCR_RTIM_3CLKS (0x0000)
#define SDRAMC_DCR_RTIM_6CLKS (0x0200)
#define SDRAMC_DCR_RTIM_9CLKS (0x0400)
#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for SDRAMC_DARCn */
#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18)
#define SDRAMC_DARCn_RE (0x00008000)
#define SDRAMC_DARCn_CASL_MASK (0x00003000)
#define SDRAMC_DARCn_CASL_C0 (0x00000000)
#define SDRAMC_DARCn_CASL_C1 (0x00001000)
#define SDRAMC_DARCn_CASL_C2 (0x00002000)
#define SDRAMC_DARCn_CASL_C3 (0x00003000)
#define SDRAMC_DARCn_CBM_MASK (0x00000700)
#define SDRAMC_DARCn_CBM_CMD17 (0x00000000)
#define SDRAMC_DARCn_CBM_CMD18 (0x00000100)
#define SDRAMC_DARCn_CBM_CMD19 (0x00000200)
#define SDRAMC_DARCn_CBM_CMD20 (0x00000300)
#define SDRAMC_DARCn_CBM_CMD21 (0x00000400)
#define SDRAMC_DARCn_CBM_CMD22 (0x00000500)
#define SDRAMC_DARCn_CBM_CMD23 (0x00000600)
#define SDRAMC_DARCn_CBM_CMD24 (0x00000700)
#define SDRAMC_DARCn_IMRS (0x00000040)
#define SDRAMC_DARCn_PS_MASK (0x00000030)
#define SDRAMC_DARCn_PS_32 (0x00000000)
#define SDRAMC_DARCn_PS_16 (0x00000010)
#define SDRAMC_DARCn_PS_8 (0x00000020)
#define SDRAMC_DARCn_IP (0x00000008)
/* Bit definitions and macros for SDRAMC_DMRn */
#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)
#define SDRAMC_DMRn_WP (0x00000100)
#define SDRAMC_DMRn_V (0x00000001)
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
/* Bit definitions and macros for FBCS_CSMR */
#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
#define FBCS_CSMR_BAM_128M (0x07FF0000)
#define FBCS_CSMR_BAM_64M (0x03FF0000)
#define FBCS_CSMR_BAM_32M (0x01FF0000)
#define FBCS_CSMR_BAM_16M (0x00FF0000)
#define FBCS_CSMR_BAM_8M (0x007F0000)
#define FBCS_CSMR_BAM_4M (0x003F0000)
#define FBCS_CSMR_BAM_2M (0x001F0000)
#define FBCS_CSMR_BAM_1M (0x000F0000)
#define FBCS_CSMR_BAM_1024K (0x000F0000)
#define FBCS_CSMR_BAM_512K (0x00070000)
#define FBCS_CSMR_BAM_256K (0x00030000)
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
#define FBCS_CSMR_WP (0x00000100)
#define FBCS_CSMR_V (0x00000001)
/* Bit definitions and macros for FBCS_CSCR */
#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
#define FBCS_CSCR_AA (0x0100)
#define FBCS_CSCR_PS_MASK (0x00C0)
#define FBCS_CSCR_PS_32 (0x0000)
#define FBCS_CSCR_PS_16 (0x0080)
#define FBCS_CSCR_PS_8 (0x0040)
#define FBCS_CSCR_BEM (0x0020)
#define FBCS_CSCR_BSTR (0x0010)
#define FBCS_CSCR_BSTW (0x0008)
#define FBCS_CSCR_SWWS(x) ((x)&0x07)
/*********************************************************************
* Queued Serial Peripheral Interface (QSPI)
*********************************************************************/
/* Bit definitions and macros for QSPI_QMR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QDLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QWR */
#define QSPI_QWR_HALT (0x8000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
/* Bit definitions and macros for QSPI_QIR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* Bit definitions and macros for QSPI_QAR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
/* Bit definitions and macros for QSPI_QDR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_SCM (8)
#define INT0_LO_DMA0 (9)
#define INT0_LO_DMA1 (10)
#define INT0_LO_DMA2 (11)
#define INT0_LO_DMA3 (12)
#define INT0_LO_UART0 (13)
#define INT0_LO_UART1 (14)
#define INT0_LO_UART2 (15)
#define INT0_LO_RSVD1 (16)
#define INT0_LO_I2C (17)
#define INT0_LO_QSPI (18)
#define INT0_LO_DTMR0 (19)
#define INT0_LO_DTMR1 (20)
#define INT0_LO_DTMR2 (21)
#define INT0_LO_DTMR3 (22)
#define INT0_LO_FEC_TXF (23)
#define INT0_LO_FEC_TXB (24)
#define INT0_LO_FEC_UN (25)
#define INT0_LO_FEC_RL (26)
#define INT0_LO_FEC_RXF (27)
#define INT0_LO_FEC_RXB (28)
#define INT0_LO_FEC_MII (29)
#define INT0_LO_FEC_LC (30)
#define INT0_LO_FEC_HBERR (31)
#define INT0_HI_FEC_GRA (32)
#define INT0_HI_FEC_EBERR (33)
#define INT0_HI_FEC_BABT (34)
#define INT0_HI_FEC_BABR (35)
#define INT0_HI_PIT0 (36)
#define INT0_HI_PIT1 (37)
#define INT0_HI_PIT2 (38)
#define INT0_HI_PIT3 (39)
#define INT0_HI_RNG (40)
#define INT0_HI_SKHA (41)
#define INT0_HI_MDHA (42)
#define INT0_HI_CAN1_BUF0I (43)
#define INT0_HI_CAN1_BUF1I (44)
#define INT0_HI_CAN1_BUF2I (45)
#define INT0_HI_CAN1_BUF3I (46)
#define INT0_HI_CAN1_BUF4I (47)
#define INT0_HI_CAN1_BUF5I (48)
#define INT0_HI_CAN1_BUF6I (49)
#define INT0_HI_CAN1_BUF7I (50)
#define INT0_HI_CAN1_BUF8I (51)
#define INT0_HI_CAN1_BUF9I (52)
#define INT0_HI_CAN1_BUF10I (53)
#define INT0_HI_CAN1_BUF11I (54)
#define INT0_HI_CAN1_BUF12I (55)
#define INT0_HI_CAN1_BUF13I (56)
#define INT0_HI_CAN1_BUF14I (57)
#define INT0_HI_CAN1_BUF15I (58)
#define INT0_HI_CAN1_ERRINT (59)
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
/* 0 - 7 Reserved */
#define INT1_LO_CAN1_BUF0I (8)
#define INT1_LO_CAN1_BUF1I (9)
#define INT1_LO_CAN1_BUF2I (10)
#define INT1_LO_CAN1_BUF3I (11)
#define INT1_LO_CAN1_BUF4I (12)
#define INT1_LO_CAN1_BUF5I (13)
#define INT1_LO_CAN1_BUF6I (14)
#define INT1_LO_CAN1_BUF7I (15)
#define INT1_LO_CAN1_BUF8I (16)
#define INT1_LO_CAN1_BUF9I (17)
#define INT1_LO_CAN1_BUF10I (18)
#define INT1_LO_CAN1_BUF11I (19)
#define INT1_LO_CAN1_BUF12I (20)
#define INT1_LO_CAN1_BUF13I (21)
#define INT1_LO_CAN1_BUF14I (22)
#define INT1_LO_CAN1_BUF15I (23)
#define INT1_LO_CAN1_ERRINT (24)
#define INT1_LO_CAN1_BOFFINT (25)
/* 26 Reserved */
#define INT1_LO_ETPU_TC0F (27)
#define INT1_LO_ETPU_TC1F (28)
#define INT1_LO_ETPU_TC2F (29)
#define INT1_LO_ETPU_TC3F (30)
#define INT1_LO_ETPU_TC4F (31)
#define INT1_HI_ETPU_TC5F (32)
#define INT1_HI_ETPU_TC6F (33)
#define INT1_HI_ETPU_TC7F (34)
#define INT1_HI_ETPU_TC8F (35)
#define INT1_HI_ETPU_TC9F (36)
#define INT1_HI_ETPU_TC10F (37)
#define INT1_HI_ETPU_TC11F (38)
#define INT1_HI_ETPU_TC12F (39)
#define INT1_HI_ETPU_TC13F (40)
#define INT1_HI_ETPU_TC14F (41)
#define INT1_HI_ETPU_TC15F (42)
#define INT1_HI_ETPU_TC16F (43)
#define INT1_HI_ETPU_TC17F (44)
#define INT1_HI_ETPU_TC18F (45)
#define INT1_HI_ETPU_TC19F (46)
#define INT1_HI_ETPU_TC20F (47)
#define INT1_HI_ETPU_TC21F (48)
#define INT1_HI_ETPU_TC22F (49)
#define INT1_HI_ETPU_TC23F (50)
#define INT1_HI_ETPU_TC24F (51)
#define INT1_HI_ETPU_TC25F (52)
#define INT1_HI_ETPU_TC26F (53)
#define INT1_HI_ETPU_TC27F (54)
#define INT1_HI_ETPU_TC28F (55)
#define INT1_HI_ETPU_TC29F (56)
#define INT1_HI_ETPU_TC30F (57)
#define INT1_HI_ETPU_TC31F (58)
#define INT1_HI_ETPU_TGIF (59)
/* Bit definitions and macros for INTC_IPRH */
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for INTC_IRLR */
#define INTC_IRLRn(x) (((x)&0x7F)<<1)
/* Bit definitions and macros for INTC_IACKLPRn */
#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_ICRnx */
#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
#define INTC_ICRnx_IP(x) ((x)&0x07)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
/* Bit definitions and macros for GPIO_PODR */
#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
#define GPIO_PODR_ADDR_MASK (0xE0)
#define GPIO_PODR_BS(x) ((x)&0x0F)
#define GPIO_PODR_BS_MASK (0x0F)
#define GPIO_PODR_CS(x) (((x)&0x7F)<<1)
#define GPIO_PODR_CS_MASK (0xFE)
#define GPIO_PODR_SDRAM(X) ((x)&0x3F)
#define GPIO_PODR_SDRAM_MASK (0x3F)
#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x)
#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK
#define GPIO_PODR_UARTH(x) ((x)&0x03)
#define GPIO_PODR_UARTH_MASK (0x03)
#define GPIO_PODR_QSPI(x) ((x)&0x1F)
#define GPIO_PODR_QSPI_MASK (0x1F)
#define GPIO_PODR_ETPU(x) ((x)&0x07)
#define GPIO_PODR_ETPU_MASK (0x07)
/* Bit definitions and macros for GPIO_PDDR */
#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x)
#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK
#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PPDSDR */
#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x)
#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK
#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PCLRR */
#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)
#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK
#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x)
#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK
#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x)
#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK
#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X)
#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x)
#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK
#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x)
#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK
#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x)
#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK
#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x)
#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK
/* Bit definitions and macros for GPIO_PAR */
#define GPIO_PAR_AD_ADDR23 (0x80)
#define GPIO_PAR_AD_ADDR22 (0x40)
#define GPIO_PAR_AD_ADDR21 (0x20)
#define GPIO_PAR_AD_DATAL (0x01)
#define GPIO_PAR_BUSCTL_OE (0x4000)
#define GPIO_PAR_BUSCTL_TA (0x1000)
#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)
#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)
#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)
#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)
#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)
#define GPIO_PAR_BUSCTL_RWB (0x0100)
#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)
#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)
#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)
#define GPIO_PAR_BUSCTL_TS_MASK (0x0C)
#define GPIO_PAR_BUSCTL_TS_GPIO (0x04)
#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)
#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)
#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)
#define GPIO_PAR_BUSCTL_TIP_MASK (0x03)
#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)
#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)
#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)
#define GPIO_PAR_BS(x) ((x)&0x0F)
#define GPIO_PAR_BS_MASK (0x0F)
#define GPIO_PAR_CS(x) (((x)&0x7F)<<1)
#define GPIO_PAR_CS_MASK (0xFE)
#define GPIO_PAR_CS_CS7 (0x80)
#define GPIO_PAR_CS_CS6 (0x40)
#define GPIO_PAR_CS_CS5 (0x20)
#define GPIO_PAR_CS_CS4 (0x10)
#define GPIO_PAR_CS_CS3 (0x08)
#define GPIO_PAR_CS_CS2 (0x04)
#define GPIO_PAR_CS_CS1 (0x02)
#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3
#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2
#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)
#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)
#define GPIO_PAR_SDRAM_SDWE (0x20)
#define GPIO_PAR_SDRAM_SCAS (0x10)
#define GPIO_PAR_SDRAM_SRAS (0x08)
#define GPIO_PAR_SDRAM_SCKE (0x04)
#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)
#define GPIO_PAR_SDRAM_SDCS_MASK (0x03)
#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)
#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)
#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)
#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)
#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)
#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)
#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)
#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)
#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)
#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)
#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
#define GPIO_PAR_FECI2C_SCL_MASK (0x0C)
#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)
#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)
#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)
#define GPIO_PAR_FECI2C_SDA_MASK (0x03)
#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)
#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)
#define GPIO_PAR_UART_DREQ2 (0x8000)
#define GPIO_PAR_UART_CAN1EN (0x4000)
#define GPIO_PAR_UART_U2RXD (0x2000)
#define GPIO_PAR_UART_U2TXD (0x1000)
#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)
#define GPIO_PAR_UART_U1RXD_MASK (0x0C00)
#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)
#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)
#define GPIO_PAR_UART_U1TXD_MASK (0x0300)
#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)
#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART_U1CTS_MASK (0x00C0)
#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)
#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)
#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART_U1RTS_MASK (0x0030)
#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)
#define GPIO_PAR_UART_U0RXD (0x0008)
#define GPIO_PAR_UART_U0TXD (0x0004)
#define GPIO_PAR_UART_U0CTS (0x0002)
#define GPIO_PAR_UART_U0RTS (0x0001)
#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)
#define GPIO_PAR_QSPI_CS1_MASK (0xC0)
#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)
#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)
#define GPIO_PAR_QSPI_CS0 (0x20)
#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)
#define GPIO_PAR_QSPI_DIN_MASK (0x18)
#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)
#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)
#define GPIO_PAR_QSPI_DOUT (0x04)
#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)
#define GPIO_PAR_QSPI_SCK_MASK (0x03)
#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)
#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)
#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)
#define GPIO_PAR_DT3IN_MASK (0xC000)
#define GPIO_PAR_DT3IN_QSPICS2 (0x4000)
#define GPIO_PAR_DT3IN_U2CTS (0x8000)
#define GPIO_PAR_DT3IN_DT3IN (0xC000)
#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)
#define GPIO_PAR_DT2IN_MASK (0x3000)
#define GPIO_PAR_DT2IN_DT2OUT (0x1000)
#define GPIO_PAR_DT2IN_DREQ2 (0x2000)
#define GPIO_PAR_DT2IN_DT2IN (0x3000)
#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)
#define GPIO_PAR_DT1IN_MASK (0x0C00)
#define GPIO_PAR_DT1IN_DT1OUT (0x0400)
#define GPIO_PAR_DT1IN_DREQ1 (0x0800)
#define GPIO_PAR_DT1IN_DT1IN (0x0C00)
#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)
#define GPIO_PAR_DT0IN_MASK (0x0300)
#define GPIO_PAR_DT0IN_DREQ0 (0x0200)
#define GPIO_PAR_DT0IN_DT0IN (0x0300)
#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)
#define GPIO_PAR_DT3OUT_MASK (0x00C0)
#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)
#define GPIO_PAR_DT3OUT_U2RTS (0x0080)
#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)
#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)
#define GPIO_PAR_DT2OUT_MASK (0x0030)
#define GPIO_PAR_DT2OUT_DACK2 (0x0020)
#define GPIO_PAR_DT2OUT_DT2OUT (0x0030)
#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)
#define GPIO_PAR_DT1OUT_MASK (0x000C)
#define GPIO_PAR_DT1OUT_DACK1 (0x0008)
#define GPIO_PAR_DT1OUT_DT1OUT (0x000C)
#define GPIO_PAR_DT0OUT(x) ((x)&0x03)
#define GPIO_PAR_DT0OUT_MASK (0x0003)
#define GPIO_PAR_DT0OUT_DACK0 (0x0002)
#define GPIO_PAR_DT0OUT_DT0OUT (0x0003)
#define GPIO_PAR_ETPU_TCRCLK (0x04)
#define GPIO_PAR_ETPU_UTPU_ODIS (0x02)
#define GPIO_PAR_ETPU_LTPU_ODIS (0x01)
/* Bit definitions and macros for GPIO_DSCR */
#define GPIO_DSCR_EIM_EIM1 (0x10)
#define GPIO_DSCR_EIM_EIM0 (0x01)
#define GPIO_DSCR_ETPU_ETPU31_24 (0x40)
#define GPIO_DSCR_ETPU_ETPU23_16 (0x10)
#define GPIO_DSCR_ETPU_ETPU15_8 (0x04)
#define GPIO_DSCR_ETPU_ETPU7_0 (0x01)
#define GPIO_DSCR_FECI2C_FEC (0x10)
#define GPIO_DSCR_FECI2C_I2C (0x01)
#define GPIO_DSCR_UART_IRQ (0x40)
#define GPIO_DSCR_UART_UART2 (0x10)
#define GPIO_DSCR_UART_UART1 (0x04)
#define GPIO_DSCR_UART_UART0 (0x01)
#define GPIO_DSCR_QSPI_QSPI (0x01)
#define GPIO_DSCR_TIMER (0x01)
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
/* Bit definitions and macros for CCM_RCR */
#define CCM_RCR_SOFTRST (0x80)
#define CCM_RCR_FRCRSTOUT (0x40)
/* Bit definitions and macros for CCM_RSR */
#define CCM_RSR_SOFT (0x20)
#define CCM_RSR_WDR (0x10)
#define CCM_RSR_POR (0x08)
#define CCM_RSR_EXT (0x04)
#define CCM_RSR_LOC (0x02)
#define CCM_RSR_LOL (0x01)
/* Bit definitions and macros for CCM_CCR */
#define CCM_CCR_LOAD (0x8000)
#define CCM_CCR_SZEN (0x0040)
#define CCM_CCR_PSTEN (0x0020)
#define CCM_CCR_BME (0x0008)
#define CCM_CCR_BMT(x) ((x)&0x07)
#define CCM_CCR_BMT_MASK (0x0007)
#define CCM_CCR_BMT_64K (0x0000)
#define CCM_CCR_BMT_32K (0x0001)
#define CCM_CCR_BMT_16K (0x0002)
#define CCM_CCR_BMT_8K (0x0003)
#define CCM_CCR_BMT_4K (0x0004)
#define CCM_CCR_BMT_2K (0x0005)
#define CCM_CCR_BMT_1K (0x0006)
#define CCM_CCR_BMT_512 (0x0007)
/* Bit definitions and macros for CCM_RCON */
#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
#define CCM_RCON_RLOAD (0x0020)
#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
#define CCM_RCON_BOOTPS_MASK (0x0018)
#define CCM_RCON_BOOTPS_32 (0x0018)
#define CCM_RCON_BOOTPS_16 (0x0008)
#define CCM_RCON_BOOTPS_8 (0x0010)
#define CCM_RCON_MODE (0x0001)
/* Bit definitions and macros for CCM_CIR */
#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
#define CCM_CIR_PRN(x) ((x)&0x003F)
/*********************************************************************
* PLL Clock Module
*********************************************************************/
/* Bit definitions and macros for PLL_SYNCR */
#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)
#define PLL_SYNCR_MFD_MASK (0x07000000)
#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)
#define PLL_SYNCR_RFC_MASK (0x00380000)
#define PLL_SYNCR_LOCEN (0x00040000)
#define PLL_SYNCR_LOLRE (0x00020000)
#define PLL_SYNCR_LOCRE (0x00010000)
#define PLL_SYNCR_DISCLK (0x00008000)
#define PLL_SYNCR_LOLIRQ (0x00004000)
#define PLL_SYNCR_LOCIRQ (0x00002000)
#define PLL_SYNCR_RATE (0x00001000)
#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)
#define PLL_SYNCR_EXP(x) ((x)&0x03FF)
/* Bit definitions and macros for PLL_SYNSR */
#define PLL_SYNSR_LOLF (0x00000200)
#define PLL_SYNSR_LOC (0x00000100)
#define PLL_SYNSR_MODE (0x00000080)
#define PLL_SYNSR_PLLSEL (0x00000040)
#define PLL_SYNSR_PLLREF (0x00000020)
#define PLL_SYNSR_LOCKS (0x00000010)
#define PLL_SYNSR_LOCK (0x00000008)
#define PLL_SYNSR_LOCF (0x00000004)
#define PLL_SYNSR_CALDONE (0x00000002)
#define PLL_SYNSR_CALPASS (0x00000001)
/*********************************************************************
* Edge Port
*********************************************************************/
#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
#define EPORT_EPIER_EPIE7 (0x80)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
/* Bit definitions and macros for WTM_WCR */
#define WTM_WCR_WAIT (0x0008)
#define WTM_WCR_DOZE (0x0004)
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_EN (0x0001)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/
/* Bit definitions and macros for CAN_CANMCR */
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_NORDY (0x08000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_LPMACK (0x00100000)
#define CANMCR_MAXMB(x) (((x)&0x0F))
/* Bit definitions and macros for CAN_CANCTRL */
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SMP (0x00000080)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) (((x)&0x07))
/* Bit definitions and macros for CAN_TIMER */
#define TIMER_TIMER(x) ((x)&0xFFFF)
/* Bit definitions and macros for CAN_RXGMASK */
#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
/* Bit definitions and macros for CAN_ERRCNT */
#define ERRCNT_TXECTR(x) (((x)&0xFF))
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for CAN_ERRSTAT */
#define ERRSTAT_BITERR1 (0x00008000)
#define ERRSTAT_BITERR0 (0x00004000)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLT_BUSOFF (0x00000020)
#define ERRSTAT_FLT_PASSIVE (0x00000010)
#define ERRSTAT_FLT_ACTIVE (0x00000000)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
/* Bit definitions and macros for CAN_IMASK */
#define IMASK_BUF15M (0x00008000)
#define IMASK_BUF14M (0x00004000)
#define IMASK_BUF13M (0x00002000)
#define IMASK_BUF12M (0x00001000)
#define IMASK_BUF11M (0x00000800)
#define IMASK_BUF10M (0x00000400)
#define IMASK_BUF9M (0x00000200)
#define IMASK_BUF8M (0x00000100)
#define IMASK_BUF7M (0x00000080)
#define IMASK_BUF6M (0x00000040)
#define IMASK_BUF5M (0x00000020)
#define IMASK_BUF4M (0x00000010)
#define IMASK_BUF3M (0x00000008)
#define IMASK_BUF2M (0x00000004)
#define IMASK_BUF1M (0x00000002)
#define IMASK_BUF0M (0x00000001)
/* Bit definitions and macros for CAN_IFLAG */
#define IFLAG_BUF15I (0x00008000)
#define IFLAG_BUF14I (0x00004000)
#define IFLAG_BUF13I (0x00002000)
#define IFLAG_BUF12I (0x00001000)
#define IFLAG_BUF11I (0x00000800)
#define IFLAG_BUF10I (0x00000400)
#define IFLAG_BUF9I (0x00000200)
#define IFLAG_BUF8I (0x00000100)
#define IFLAG_BUF7I (0x00000080)
#define IFLAG_BUF6I (0x00000040)
#define IFLAG_BUF5I (0x00000020)
#define IFLAG_BUF4I (0x00000010)
#define IFLAG_BUF3I (0x00000008)
#define IFLAG_BUF2I (0x00000004)
#define IFLAG_BUF1I (0x00000002)
#define IFLAG_BUF0I (0x00000001)
#endif /* mcf5235_h */

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/*
* Configuation settings for the Freescale MCF5329 FireEngine board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5235EVB_H
#define _M5235EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF523x /* define processor family */
#define CONFIG_M5235 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_BOOTFILE "u-boot.bin"
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5235EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe3ffff;" \
"era ffe00000 ffe3ffff;" \
"cp.b ${loadaddr} ffe00000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000)
#define CFG_HZ 1000
#define CFG_CLK 75000000
#define CFG_CPU_CLK CFG_CLK * 2
#define CFG_MBAR 0x40000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x21
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
#ifdef NORFLASH_PS32BIT
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
#else
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#endif
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
#ifdef NORFLASH_PS32BIT
# define CFG_ENV_OFFSET (0x8000)
# define CFG_ENV_SIZE 0x4000
# define CFG_ENV_SECT_SIZE 0x4000
#else
# define CFG_ENV_OFFSET (0x4000)
# define CFG_ENV_SIZE 0x2000
# define CFG_ENV_SECT_SIZE 0x2000
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - Available
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
* CS6 - Available
* CS7 - Available
*/
#ifdef NORFLASH_PS32BIT
# define CFG_CS0_BASE 0xFFC0
# define CFG_CS0_MASK 0x003f0001
# define CFG_CS0_CTRL 0x1D00
#else
# define CFG_CS0_BASE 0xFFE0
# define CFG_CS0_MASK 0x001f0001
# define CFG_CS0_CTRL 0x1D80
#endif
#endif /* _M5329EVB_H */