Merge with /home/wd/git/u-boot/custodian/u-boot-mpc85xx
This commit is contained in:
commit
46919751ea
61
CHANGELOG
61
CHANGELOG
|
@ -440,6 +440,14 @@ Date: Tue Jul 3 00:32:53 2007 -0600
|
||||||
|
|
||||||
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
|
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
|
||||||
|
|
||||||
|
commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f
|
||||||
|
Author: Wolfgang Denk <wd@denx.de>
|
||||||
|
Date: Fri Jul 6 02:50:19 2007 +0200
|
||||||
|
|
||||||
|
Code cleanup and default config update for STC GP3 SSA board.
|
||||||
|
|
||||||
|
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||||
|
|
||||||
commit 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd
|
commit 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd
|
||||||
Author: Wolfgang Denk <wd@denx.de>
|
Author: Wolfgang Denk <wd@denx.de>
|
||||||
Date: Wed Jul 4 00:43:53 2007 +0200
|
Date: Wed Jul 4 00:43:53 2007 +0200
|
||||||
|
@ -448,6 +456,14 @@ Date: Wed Jul 4 00:43:53 2007 +0200
|
||||||
|
|
||||||
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||||
|
|
||||||
|
commit b44896215a09c60fa40cae906f7ed207bbc2c492
|
||||||
|
Author: Sergei Poselenov <sposelenov@emcraft.com>
|
||||||
|
Date: Thu Jul 5 08:17:37 2007 +0200
|
||||||
|
|
||||||
|
Merged POST framework with the current TOT.
|
||||||
|
|
||||||
|
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
|
||||||
|
|
||||||
commit 78e0cf2de7be7f1eaeeb622eb61fd50e4d5e205c
|
commit 78e0cf2de7be7f1eaeeb622eb61fd50e4d5e205c
|
||||||
Author: Wolfgang Denk <wd@denx.de>
|
Author: Wolfgang Denk <wd@denx.de>
|
||||||
Date: Wed Jul 4 00:38:38 2007 +0200
|
Date: Wed Jul 4 00:38:38 2007 +0200
|
||||||
|
@ -462,6 +478,14 @@ Date: Mon Jun 11 19:03:44 2007 -0500
|
||||||
|
|
||||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||||
|
|
||||||
|
commit f780b83316d9af1f61d71cc88b1917b387b9b995
|
||||||
|
Author: Niklaus Giger <niklausgiger@gmx.ch>
|
||||||
|
Date: Wed Jun 27 18:11:38 2007 +0200
|
||||||
|
|
||||||
|
resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX
|
||||||
|
|
||||||
|
Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
|
||||||
|
|
||||||
commit 602ad3b33d9ceef83dbab46be68646d645d637ee
|
commit 602ad3b33d9ceef83dbab46be68646d645d637ee
|
||||||
Author: Jon Loeliger <jdl@jdl.com>
|
Author: Jon Loeliger <jdl@jdl.com>
|
||||||
Date: Mon Jun 11 19:03:39 2007 -0500
|
Date: Mon Jun 11 19:03:39 2007 -0500
|
||||||
|
@ -470,6 +494,20 @@ Date: Mon Jun 11 19:03:39 2007 -0500
|
||||||
|
|
||||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||||
|
|
||||||
|
commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4
|
||||||
|
Author: Stefan Roese <sr@denx.de>
|
||||||
|
Date: Wed Jul 4 10:06:30 2007 +0200
|
||||||
|
|
||||||
|
ppc4xx: Update lwmon5 board
|
||||||
|
|
||||||
|
- Add optional ECC generation routine to preserve existing
|
||||||
|
RAM values. This is needed for the Linux log-buffer support
|
||||||
|
- Add optional DDR2 setup with CL=4
|
||||||
|
- GPIO50 not used anymore
|
||||||
|
- Lime register setup added
|
||||||
|
|
||||||
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||||
|
|
||||||
commit 72a074cec68e5bad60d63206c050974e08afd804
|
commit 72a074cec68e5bad60d63206c050974e08afd804
|
||||||
Author: Jon Loeliger <jdl@jdl.com>
|
Author: Jon Loeliger <jdl@jdl.com>
|
||||||
Date: Mon Jun 11 19:03:34 2007 -0500
|
Date: Mon Jun 11 19:03:34 2007 -0500
|
||||||
|
@ -782,6 +820,14 @@ Date: Sat Jun 30 18:50:48 2007 +0200
|
||||||
|
|
||||||
Signed-off-by: mushtaq khan <mushtaqk_921@yahoo.co.in>
|
Signed-off-by: mushtaq khan <mushtaqk_921@yahoo.co.in>
|
||||||
|
|
||||||
|
commit a5d71e290f3673269be8eefb4ec44f53412f9461
|
||||||
|
Author: Heiko Schocher <hs@pollux.denx.de>
|
||||||
|
Date: Mon Jun 25 19:11:37 2007 +0200
|
||||||
|
|
||||||
|
[PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG
|
||||||
|
|
||||||
|
Signed-off-by: Heiko Schocher <hs@denx.de>
|
||||||
|
|
||||||
commit a1bd6200eccd3a02040a955d5f43d3ee1fc9f93b
|
commit a1bd6200eccd3a02040a955d5f43d3ee1fc9f93b
|
||||||
Author: Niklaus Giger <niklaus.giger@nestal.com>
|
Author: Niklaus Giger <niklaus.giger@nestal.com>
|
||||||
Date: Mon Jun 25 17:03:13 2007 +0200
|
Date: Mon Jun 25 17:03:13 2007 +0200
|
||||||
|
@ -882,6 +928,21 @@ Date: Wed Mar 28 19:06:19 2007 +0400
|
||||||
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
|
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
|
||||||
--
|
--
|
||||||
|
|
||||||
|
commit 566a494f592ae3b3c0785d90d4e1ba45574880c4
|
||||||
|
Author: Heiko Schocher <hs@pollux.denx.de>
|
||||||
|
Date: Fri Jun 22 19:11:54 2007 +0200
|
||||||
|
|
||||||
|
[PCS440EP] upgrade the PCS440EP board:
|
||||||
|
- Show on the Status LEDs, some States of the board.
|
||||||
|
- Get the MAC addresses from the EEProm
|
||||||
|
- use PREBOOT
|
||||||
|
- use the CF on the board.
|
||||||
|
- check the U-Boot image in the Flash with a SHA1
|
||||||
|
checksum.
|
||||||
|
- use dynamic TLB entries generation for the SDRAM
|
||||||
|
|
||||||
|
Signed-off-by: Heiko Schocher <hs@denx.de>
|
||||||
|
|
||||||
commit 3a1f5c81b0b9557817a789bece839905581c2205
|
commit 3a1f5c81b0b9557817a789bece839905581c2205
|
||||||
Author: Stefan Roese <sr@denx.de>
|
Author: Stefan Roese <sr@denx.de>
|
||||||
Date: Fri Jun 22 16:58:40 2007 +0200
|
Date: Fri Jun 22 16:58:40 2007 +0200
|
||||||
|
|
11
Makefile
11
Makefile
|
@ -214,6 +214,8 @@ LIBS += drivers/sk98lin/libsk98lin.a
|
||||||
LIBS += post/libpost.a post/drivers/libpostdrivers.a
|
LIBS += post/libpost.a post/drivers/libpostdrivers.a
|
||||||
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
|
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
|
||||||
"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
|
"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
|
||||||
|
LIBS += $(shell if [ -d post/lib_$(ARCH)/fpu ]; then echo \
|
||||||
|
"post/lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
|
||||||
LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
|
LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
|
||||||
"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
|
"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
|
||||||
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
|
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
|
||||||
|
@ -245,7 +247,7 @@ __LIBS := $(subst $(obj),,$(LIBS))
|
||||||
#########################################################################
|
#########################################################################
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
|
ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
|
||||||
|
|
||||||
all: $(ALL)
|
all: $(ALL)
|
||||||
|
|
||||||
|
@ -265,6 +267,9 @@ $(obj)u-boot.img: $(obj)u-boot.bin
|
||||||
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
|
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
|
||||||
-d $< $@
|
-d $< $@
|
||||||
|
|
||||||
|
$(obj)u-boot.sha1: $(obj)u-boot.bin
|
||||||
|
./tools/ubsha1 $(obj)u-boot.bin
|
||||||
|
|
||||||
$(obj)u-boot.dis: $(obj)u-boot
|
$(obj)u-boot.dis: $(obj)u-boot
|
||||||
$(OBJDUMP) -d $< > $@
|
$(OBJDUMP) -d $< > $@
|
||||||
|
|
||||||
|
@ -2461,7 +2466,7 @@ clean:
|
||||||
$(obj)examples/smc91111_eeprom $(obj)examples/interrupt \
|
$(obj)examples/smc91111_eeprom $(obj)examples/interrupt \
|
||||||
$(obj)examples/test_burst
|
$(obj)examples/test_burst
|
||||||
rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \
|
rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \
|
||||||
$(obj)tools/gen_eth_addr
|
$(obj)tools/gen_eth_addr $(obj)tools/ubsha1
|
||||||
rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb
|
rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb
|
||||||
rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo
|
rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo
|
||||||
rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend
|
rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend
|
||||||
|
@ -2484,7 +2489,7 @@ clobber: clean
|
||||||
rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS $(obj)include/version_autogenerated.h
|
rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS $(obj)include/version_autogenerated.h
|
||||||
rm -fr $(obj)*.*~
|
rm -fr $(obj)*.*~
|
||||||
rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
|
rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
|
||||||
rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
|
rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c $(obj)tools/sha1.c
|
||||||
rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
|
rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
|
||||||
rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
|
rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
|
||||||
[ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
|
[ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
|
||||||
|
|
79
README
79
README
|
@ -1702,28 +1702,69 @@ The following options need to be configured:
|
||||||
-31 post/post.c POST test failed, detected by post_output_backlog()
|
-31 post/post.c POST test failed, detected by post_output_backlog()
|
||||||
-32 post/post.c POST test failed, detected by post_run_single()
|
-32 post/post.c POST test failed, detected by post_run_single()
|
||||||
|
|
||||||
-1 common/cmd_doc.c Bad usage of "doc" command
|
34 common/cmd_doc.c before loading a Image from a DOC device
|
||||||
-1 common/cmd_doc.c No boot device
|
-35 common/cmd_doc.c Bad usage of "doc" command
|
||||||
-1 common/cmd_doc.c Unknown Chip ID on boot device
|
35 common/cmd_doc.c correct usage of "doc" command
|
||||||
-1 common/cmd_doc.c Read Error on boot device
|
-36 common/cmd_doc.c No boot device
|
||||||
-1 common/cmd_doc.c Image header has bad magic number
|
36 common/cmd_doc.c correct boot device
|
||||||
|
-37 common/cmd_doc.c Unknown Chip ID on boot device
|
||||||
|
37 common/cmd_doc.c correct chip ID found, device available
|
||||||
|
-38 common/cmd_doc.c Read Error on boot device
|
||||||
|
38 common/cmd_doc.c reading Image header from DOC device OK
|
||||||
|
-39 common/cmd_doc.c Image header has bad magic number
|
||||||
|
39 common/cmd_doc.c Image header has correct magic number
|
||||||
|
-40 common/cmd_doc.c Error reading Image from DOC device
|
||||||
|
40 common/cmd_doc.c Image header has correct magic number
|
||||||
|
41 common/cmd_ide.c before loading a Image from a IDE device
|
||||||
|
-42 common/cmd_ide.c Bad usage of "ide" command
|
||||||
|
42 common/cmd_ide.c correct usage of "ide" command
|
||||||
|
-43 common/cmd_ide.c No boot device
|
||||||
|
43 common/cmd_ide.c boot device found
|
||||||
|
-44 common/cmd_ide.c Device not available
|
||||||
|
44 common/cmd_ide.c Device available
|
||||||
|
-45 common/cmd_ide.c wrong partition selected
|
||||||
|
45 common/cmd_ide.c partition selected
|
||||||
|
-46 common/cmd_ide.c Unknown partition table
|
||||||
|
46 common/cmd_ide.c valid partition table found
|
||||||
|
-47 common/cmd_ide.c Invalid partition type
|
||||||
|
47 common/cmd_ide.c correct partition type
|
||||||
|
-48 common/cmd_ide.c Error reading Image Header on boot device
|
||||||
|
48 common/cmd_ide.c reading Image Header from IDE device OK
|
||||||
|
-49 common/cmd_ide.c Image header has bad magic number
|
||||||
|
49 common/cmd_ide.c Image header has correct magic number
|
||||||
|
-50 common/cmd_ide.c Image header has bad checksum
|
||||||
|
50 common/cmd_ide.c Image header has correct checksum
|
||||||
|
-51 common/cmd_ide.c Error reading Image from IDE device
|
||||||
|
51 common/cmd_ide.c reading Image from IDE device OK
|
||||||
|
52 common/cmd_nand.c before loading a Image from a NAND device
|
||||||
|
-53 common/cmd_nand.c Bad usage of "nand" command
|
||||||
|
53 common/cmd_nand.c correct usage of "nand" command
|
||||||
|
-54 common/cmd_nand.c No boot device
|
||||||
|
54 common/cmd_nand.c boot device found
|
||||||
|
-55 common/cmd_nand.c Unknown Chip ID on boot device
|
||||||
|
55 common/cmd_nand.c correct chip ID found, device available
|
||||||
|
-56 common/cmd_nand.c Error reading Image Header on boot device
|
||||||
|
56 common/cmd_nand.c reading Image Header from NAND device OK
|
||||||
|
-57 common/cmd_nand.c Image header has bad magic number
|
||||||
|
57 common/cmd_nand.c Image header has correct magic number
|
||||||
|
-58 common/cmd_nand.c Error reading Image from NAND device
|
||||||
|
58 common/cmd_nand.c reading Image from NAND device OK
|
||||||
|
|
||||||
-1 common/cmd_ide.c Bad usage of "ide" command
|
-60 common/env_common.c Environment has a bad CRC, using default
|
||||||
-1 common/cmd_ide.c No boot device
|
|
||||||
-1 common/cmd_ide.c Unknown boot device
|
|
||||||
-1 common/cmd_ide.c Unknown partition table
|
|
||||||
-1 common/cmd_ide.c Invalid partition type
|
|
||||||
-1 common/cmd_ide.c Read Error on boot device
|
|
||||||
-1 common/cmd_ide.c Image header has bad magic number
|
|
||||||
|
|
||||||
-1 common/cmd_nand.c Bad usage of "nand" command
|
64 net/eth.c starting with Ethernetconfiguration.
|
||||||
-1 common/cmd_nand.c No boot device
|
-64 net/eth.c no Ethernet found.
|
||||||
-1 common/cmd_nand.c Unknown Chip ID on boot device
|
65 net/eth.c Ethernet found.
|
||||||
-1 common/cmd_nand.c Read Error on boot device
|
|
||||||
-1 common/cmd_nand.c Image header has bad magic number
|
|
||||||
|
|
||||||
-1 common/env_common.c Environment has a bad CRC, using default
|
|
||||||
|
|
||||||
|
-80 common/cmd_net.c usage wrong
|
||||||
|
80 common/cmd_net.c before calling NetLoop()
|
||||||
|
-81 common/cmd_net.c some error in NetLoop() occured
|
||||||
|
81 common/cmd_net.c NetLoop() back without error
|
||||||
|
-82 common/cmd_net.c size == 0 (File with size 0 loaded)
|
||||||
|
82 common/cmd_net.c trying automatic boot
|
||||||
|
83 common/cmd_net.c running autoscript
|
||||||
|
-83 common/cmd_net.c some error in automatic boot or autoscript
|
||||||
|
84 common/cmd_net.c end without errors
|
||||||
|
|
||||||
Modem Support:
|
Modem Support:
|
||||||
--------------
|
--------------
|
||||||
|
|
|
@ -25,7 +25,6 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <ppc440.h>
|
#include <ppc440.h>
|
||||||
#include "sequoia.h"
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
@ -226,7 +225,7 @@ int misc_init_r(void)
|
||||||
if (act == NULL || strcmp(act, "hostdev") == 0) {
|
if (act == NULL || strcmp(act, "hostdev") == 0) {
|
||||||
/* SDR Setting */
|
/* SDR Setting */
|
||||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
mfsdr(SDR0_USB0, usb2d0cr);
|
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
|
||||||
|
@ -254,7 +253,7 @@ int misc_init_r(void)
|
||||||
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
|
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
|
||||||
|
|
||||||
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
mtsdr(SDR0_USB0, usb2d0cr);
|
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
|
||||||
|
@ -298,7 +297,7 @@ int misc_init_r(void)
|
||||||
/* SDR Setting */
|
/* SDR Setting */
|
||||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
mfsdr(SDR0_USB0, usb2d0cr);
|
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
||||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||||
|
@ -323,7 +322,7 @@ int misc_init_r(void)
|
||||||
|
|
||||||
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
mtsdr(SDR0_USB0, usb2d0cr);
|
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
||||||
/*clear resets*/
|
/*clear resets*/
|
||||||
|
|
|
@ -1,67 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2006
|
|
||||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2006
|
|
||||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
|
||||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------+
|
|
||||||
| EBC Configuration Register - EBC0_CFG
|
|
||||||
+----------------------------------------------------------------------------*/
|
|
||||||
/* External Bus Three-State Control */
|
|
||||||
#define EBC0_CFG_EBTC_DRIVEN 0x80000000
|
|
||||||
/* Device-Paced Time-out Disable */
|
|
||||||
#define EBC0_CFG_PTD_ENABLED 0x00000000
|
|
||||||
/* Ready Timeout Count */
|
|
||||||
#define EBC0_CFG_RTC_MASK 0x38000000
|
|
||||||
#define EBC0_CFG_RTC_16PERCLK 0x00000000
|
|
||||||
#define EBC0_CFG_RTC_32PERCLK 0x08000000
|
|
||||||
#define EBC0_CFG_RTC_64PERCLK 0x10000000
|
|
||||||
#define EBC0_CFG_RTC_128PERCLK 0x18000000
|
|
||||||
#define EBC0_CFG_RTC_256PERCLK 0x20000000
|
|
||||||
#define EBC0_CFG_RTC_512PERCLK 0x28000000
|
|
||||||
#define EBC0_CFG_RTC_1024PERCLK 0x30000000
|
|
||||||
#define EBC0_CFG_RTC_2048PERCLK 0x38000000
|
|
||||||
/* External Master Priority Low */
|
|
||||||
#define EBC0_CFG_EMPL_LOW 0x00000000
|
|
||||||
#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
|
|
||||||
#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
|
|
||||||
#define EBC0_CFG_EMPL_HIGH 0x06000000
|
|
||||||
/* External Master Priority High */
|
|
||||||
#define EBC0_CFG_EMPH_LOW 0x00000000
|
|
||||||
#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
|
|
||||||
#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
|
|
||||||
#define EBC0_CFG_EMPH_HIGH 0x01800000
|
|
||||||
/* Chip Select Three-State Control */
|
|
||||||
#define EBC0_CFG_CSTC_DRIVEN 0x00400000
|
|
||||||
/* Burst Prefetch */
|
|
||||||
#define EBC0_CFG_BPF_ONEDW 0x00000000
|
|
||||||
#define EBC0_CFG_BPF_TWODW 0x00100000
|
|
||||||
#define EBC0_CFG_BPF_FOURDW 0x00200000
|
|
||||||
/* External Master Size */
|
|
||||||
#define EBC0_CFG_EMS_8BIT 0x00000000
|
|
||||||
/* Power Management Enable */
|
|
||||||
#define EBC0_CFG_PME_DISABLED 0x00000000
|
|
||||||
#define EBC0_CFG_PME_ENABLED 0x00020000
|
|
||||||
/* Power Management Timer */
|
|
||||||
#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
|
|
||||||
|
|
||||||
#define SDR0_USB0 0x0320 /* USB Control Register */
|
|
|
@ -31,7 +31,7 @@
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
|
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
|
||||||
#if 0
|
#if 0
|
||||||
#define FPGA_DEBUG
|
#define FPGA_DEBUG
|
||||||
#endif
|
#endif
|
||||||
|
@ -109,10 +109,10 @@ int board_early_init_f (void)
|
||||||
/*
|
/*
|
||||||
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
|
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
|
||||||
*/
|
*/
|
||||||
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
|
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||||
out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
|
out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
|
||||||
out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
|
out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
|
||||||
out32(GPIO0_OR, 0); /* pull prg low */
|
out32(GPIO0_OR, 0); /* pull prg low */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Boot onboard FPGA
|
* Boot onboard FPGA
|
||||||
|
@ -174,21 +174,21 @@ int board_early_init_f (void)
|
||||||
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
|
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
|
||||||
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
|
||||||
*/
|
*/
|
||||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||||
mtdcr(uicer, 0x00000000); /* disable all ints */
|
mtdcr(uicer, 0x00000000); /* disable all ints */
|
||||||
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
|
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
|
||||||
#ifdef CONFIG_CPCI405_6U
|
#ifdef CONFIG_CPCI405_6U
|
||||||
if (cpci405_version() == 3) {
|
if (cpci405_version() == 3) {
|
||||||
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
|
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
|
||||||
} else {
|
} else {
|
||||||
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
|
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
|
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
|
||||||
#endif
|
#endif
|
||||||
mtdcr(uictr, 0x10000000); /* set int trigger levels */
|
mtdcr(uictr, 0x10000000); /* set int trigger levels */
|
||||||
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
|
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
|
||||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -198,22 +198,22 @@ int board_early_init_f (void)
|
||||||
int ctermm2(void)
|
int ctermm2(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_CPCI405_VER2
|
#ifdef CONFIG_CPCI405_VER2
|
||||||
return 0; /* no, board is cpci405 */
|
return 0; /* no, board is cpci405 */
|
||||||
#else
|
#else
|
||||||
if ((*(unsigned char *)0xf0000400 == 0x00) &&
|
if ((*(unsigned char *)0xf0000400 == 0x00) &&
|
||||||
(*(unsigned char *)0xf0000401 == 0x01))
|
(*(unsigned char *)0xf0000401 == 0x01))
|
||||||
return 0; /* no, board is cpci405 */
|
return 0; /* no, board is cpci405 */
|
||||||
else
|
else
|
||||||
return -1; /* yes, board is cterm-m2 */
|
return -1; /* yes, board is cterm-m2 */
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
int cpci405_host(void)
|
int cpci405_host(void)
|
||||||
{
|
{
|
||||||
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
|
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
|
||||||
return -1; /* yes, board is cpci405 host */
|
return -1; /* yes, board is cpci405 host */
|
||||||
else
|
else
|
||||||
return 0; /* no, board is cpci405 adapter */
|
return 0; /* no, board is cpci405 adapter */
|
||||||
}
|
}
|
||||||
|
|
||||||
int cpci405_version(void)
|
int cpci405_version(void)
|
||||||
|
@ -228,8 +228,8 @@ int cpci405_version(void)
|
||||||
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
|
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
|
||||||
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
|
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
|
||||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
|
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
|
||||||
udelay(1000); /* wait some time before reading input */
|
udelay(1000); /* wait some time before reading input */
|
||||||
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
|
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Restore GPIO settings
|
* Restore GPIO settings
|
||||||
|
@ -478,7 +478,7 @@ int checkboard (void)
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifndef CONFIG_CPCI405_VER2
|
#ifndef CONFIG_CPCI405_VER2
|
||||||
puts ("\nFPGA: ");
|
puts ("\nFPGA: ");
|
||||||
|
|
||||||
/* display infos on fpgaimage */
|
/* display infos on fpgaimage */
|
||||||
index = 15;
|
index = 15;
|
||||||
|
@ -574,11 +574,11 @@ int pci_pre_init(struct pci_controller *hose)
|
||||||
|
|
||||||
#ifdef CONFIG_CPCI405AB
|
#ifdef CONFIG_CPCI405AB
|
||||||
|
|
||||||
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|
||||||
|= CFG_FPGA_MODE_1WIRE_DIR)
|
|= CFG_FPGA_MODE_1WIRE_DIR)
|
||||||
#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|
#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|
||||||
&= ~CFG_FPGA_MODE_1WIRE_DIR)
|
&= ~CFG_FPGA_MODE_1WIRE_DIR)
|
||||||
#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
|
#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
|
||||||
& CFG_FPGA_MODE_1WIRE)
|
& CFG_FPGA_MODE_1WIRE)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -24,9 +24,9 @@
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
# ifneq ($(OBJTREE),$(SRCTREE))
|
ifneq ($(OBJTREE),$(SRCTREE))
|
||||||
# $(shell mkdir -p $(obj)./common)
|
$(shell mkdir -p $(obj)../common)
|
||||||
# endif
|
endif
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
|
|
|
@ -597,6 +597,7 @@ void show_boot_progress (int status)
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
|
|
||||||
|
if (status < -32) status = -1; /* let things compatible */
|
||||||
status ^= 0x0F;
|
status ^= 0x0F;
|
||||||
status = (status & 0x0F) << 14;
|
status = (status & 0x0F) << 14;
|
||||||
immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
|
immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
|
||||||
|
|
|
@ -107,6 +107,7 @@ void logodl_set_led(int led, int state)
|
||||||
|
|
||||||
void show_boot_progress (int status)
|
void show_boot_progress (int status)
|
||||||
{
|
{
|
||||||
|
if (status < -32) status = -1; /* let things compatible */
|
||||||
/*
|
/*
|
||||||
switch(status) {
|
switch(status) {
|
||||||
case 1: logodl_set_led(0,1); break;
|
case 1: logodl_set_led(0,1); break;
|
||||||
|
|
|
@ -19,9 +19,10 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <ppc440.h>
|
#include <ppc440.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
#include <asm/gpio.h>
|
#include <asm/gpio.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
@ -220,6 +221,13 @@ int misc_init_r(void)
|
||||||
udelay(500);
|
udelay(500);
|
||||||
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
|
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
|
||||||
|
|
||||||
|
/* Lime memory clock adjusted to 133MHz */
|
||||||
|
out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
|
||||||
|
/* Wait untill time expired. Because of requirements in lime manual */
|
||||||
|
udelay(300);
|
||||||
|
/* Write lime controller memory parameters */
|
||||||
|
out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset PHY's
|
* Reset PHY's
|
||||||
*/
|
*/
|
||||||
|
@ -229,13 +237,6 @@ int misc_init_r(void)
|
||||||
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
|
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
|
||||||
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
|
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
|
||||||
|
|
||||||
/*
|
|
||||||
* Reset USB hub
|
|
||||||
*/
|
|
||||||
gpio_write_bit(CFG_GPIO_HUB_RST, 0);
|
|
||||||
udelay(100);
|
|
||||||
gpio_write_bit(CFG_GPIO_HUB_RST, 1);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -474,8 +474,27 @@ static void program_ecc(u32 start_address,
|
||||||
blank_string(strlen(str));
|
blank_string(strlen(str));
|
||||||
} else {
|
} else {
|
||||||
/* ECC bit set method for cached memory */
|
/* ECC bit set method for cached memory */
|
||||||
|
#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
|
||||||
|
/*
|
||||||
|
* Some boards (like lwmon5) need to preserve the memory
|
||||||
|
* content upon ECC generation (for the log-buffer).
|
||||||
|
* Therefore we don't fill the memory with a pattern or
|
||||||
|
* just zero it, but write the same values back that are
|
||||||
|
* already in the memory cells.
|
||||||
|
*/
|
||||||
|
address_increment = CFG_CACHELINE_SIZE;
|
||||||
|
end_address = current_address + num_bytes;
|
||||||
|
|
||||||
|
current_address = start_address;
|
||||||
|
while (current_address < end_address) {
|
||||||
|
ppcDcbi(current_address);
|
||||||
|
ppcDcbf(current_address);
|
||||||
|
current_address += CFG_CACHELINE_SIZE;
|
||||||
|
}
|
||||||
|
#else
|
||||||
dcbz_area(start_address, num_bytes);
|
dcbz_area(start_address, num_bytes);
|
||||||
dflush();
|
dflush();
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
sync();
|
sync();
|
||||||
|
@ -518,6 +537,8 @@ long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
u32 val;
|
u32 val;
|
||||||
|
|
||||||
|
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
|
||||||
|
/* CL=3 */
|
||||||
mtsdram(DDR0_02, 0x00000000);
|
mtsdram(DDR0_02, 0x00000000);
|
||||||
|
|
||||||
mtsdram(DDR0_00, 0x0000190A);
|
mtsdram(DDR0_00, 0x0000190A);
|
||||||
|
@ -558,6 +579,49 @@ long int initdram (int board_type)
|
||||||
mtsdram(DDR0_43, 0x030A0200);
|
mtsdram(DDR0_43, 0x030A0200);
|
||||||
mtsdram(DDR0_44, 0x00000003);
|
mtsdram(DDR0_44, 0x00000003);
|
||||||
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
|
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
|
||||||
|
#else
|
||||||
|
/* CL=4 */
|
||||||
|
mtsdram(DDR0_02, 0x00000000);
|
||||||
|
|
||||||
|
mtsdram(DDR0_00, 0x0000190A);
|
||||||
|
mtsdram(DDR0_01, 0x01000000);
|
||||||
|
mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
|
||||||
|
|
||||||
|
mtsdram(DDR0_04, 0x0B030300);
|
||||||
|
mtsdram(DDR0_05, 0x02020308);
|
||||||
|
mtsdram(DDR0_06, 0x0003C812);
|
||||||
|
mtsdram(DDR0_07, 0x00090100);
|
||||||
|
mtsdram(DDR0_08, 0x03c80001);
|
||||||
|
mtsdram(DDR0_09, 0x00011D5F);
|
||||||
|
mtsdram(DDR0_10, 0x00000300);
|
||||||
|
mtsdram(DDR0_11, 0x000CC800);
|
||||||
|
mtsdram(DDR0_12, 0x00000003);
|
||||||
|
mtsdram(DDR0_14, 0x00000000);
|
||||||
|
mtsdram(DDR0_17, 0x1e000000);
|
||||||
|
mtsdram(DDR0_18, 0x1e1e1e1e);
|
||||||
|
mtsdram(DDR0_19, 0x1e1e1e1e);
|
||||||
|
mtsdram(DDR0_20, 0x0B0B0B0B);
|
||||||
|
mtsdram(DDR0_21, 0x0B0B0B0B);
|
||||||
|
#ifdef CONFIG_DDR_ECC
|
||||||
|
mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
|
||||||
|
#else
|
||||||
|
mtsdram(DDR0_22, 0x00267F0B);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
mtsdram(DDR0_23, 0x01000000);
|
||||||
|
mtsdram(DDR0_24, 0x01010001);
|
||||||
|
|
||||||
|
mtsdram(DDR0_26, 0x2D93028A);
|
||||||
|
mtsdram(DDR0_27, 0x0784682B);
|
||||||
|
|
||||||
|
mtsdram(DDR0_28, 0x00000080);
|
||||||
|
mtsdram(DDR0_31, 0x00000000);
|
||||||
|
mtsdram(DDR0_42, 0x01000008);
|
||||||
|
|
||||||
|
mtsdram(DDR0_43, 0x050A0200);
|
||||||
|
mtsdram(DDR0_44, 0x00000005);
|
||||||
|
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
|
||||||
|
#endif
|
||||||
|
|
||||||
wait_for_dlllock();
|
wait_for_dlllock();
|
||||||
|
|
||||||
|
|
|
@ -549,9 +549,35 @@ pci_init_board(void)
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||||
|
void
|
||||||
|
ft_soc_setup(void *blob, bd_t *bd)
|
||||||
|
{
|
||||||
|
u32 *p;
|
||||||
|
int len;
|
||||||
|
ulong data;
|
||||||
|
|
||||||
|
p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
|
||||||
|
|
||||||
|
if (p != NULL)
|
||||||
|
*p = cpu_to_be32(bd->bi_brgfreq);
|
||||||
|
|
||||||
|
p = ft_get_prop(blob,
|
||||||
|
"/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed",
|
||||||
|
&len);
|
||||||
|
if (p != NULL)
|
||||||
|
*p = cpu_to_be32(bd->bi_baudrate);
|
||||||
|
|
||||||
|
p = ft_get_prop(blob,
|
||||||
|
"/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed",
|
||||||
|
&len);
|
||||||
|
if (p != NULL)
|
||||||
|
*p = cpu_to_be32(bd->bi_baudrate);
|
||||||
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
ft_board_setup(void *blob, bd_t *bd)
|
ft_board_setup(void *blob, bd_t *bd)
|
||||||
{
|
{
|
||||||
ft_cpu_setup(blob, bd);
|
ft_cpu_setup(blob, bd);
|
||||||
|
ft_soc_setup(blob, bd);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -25,6 +25,9 @@
|
||||||
# PCS440EP board
|
# PCS440EP board
|
||||||
#
|
#
|
||||||
|
|
||||||
|
# Check the U-Boot Image with a SHA1 checksum
|
||||||
|
ALL += $(obj)u-boot.sha1
|
||||||
|
|
||||||
#TEXT_BASE = 0x00001000
|
#TEXT_BASE = 0x00001000
|
||||||
|
|
||||||
ifeq ($(ramsym),1)
|
ifeq ($(ramsym),1)
|
||||||
|
|
|
@ -83,6 +83,7 @@ void flash_print_info(flash_info_t *info)
|
||||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||||
case FLASH_MAN_SST: printf ("SST "); break;
|
case FLASH_MAN_SST: printf ("SST "); break;
|
||||||
case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
|
case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
|
||||||
|
case FLASH_MAN_MX: printf ("MXIC "); break;
|
||||||
default: printf ("Unknown Vendor "); break;
|
default: printf ("Unknown Vendor "); break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -195,6 +196,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info)
|
||||||
case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
|
case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
|
||||||
info->flash_id = FLASH_MAN_EXCEL;
|
info->flash_id = FLASH_MAN_EXCEL;
|
||||||
break;
|
break;
|
||||||
|
case (CFG_FLASH_WORD_SIZE)MX_MANUFACT:
|
||||||
|
info->flash_id = FLASH_MAN_MX;
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
info->flash_id = FLASH_UNKNOWN;
|
info->flash_id = FLASH_UNKNOWN;
|
||||||
info->sector_count = 0;
|
info->sector_count = 0;
|
||||||
|
|
|
@ -87,27 +87,32 @@
|
||||||
.globl tlbtab
|
.globl tlbtab
|
||||||
|
|
||||||
tlbtab:
|
tlbtab:
|
||||||
tlbtab_start
|
tlbtab_start
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||||
* speed up boot process. It is patched after relocation to enable SA_I
|
* speed up boot process. It is patched after relocation to enable SA_I
|
||||||
*/
|
*/
|
||||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
|
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
|
||||||
|
|
||||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||||
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||||
|
|
||||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
/*
|
||||||
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
|
* TLB entries for SDRAM are not needed on this platform.
|
||||||
|
* They are dynamically generated in the SPD DDR detection
|
||||||
|
* routine.
|
||||||
|
*/
|
||||||
|
|
||||||
/* PCI */
|
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
|
|
||||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
|
|
||||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
|
|
||||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
|
|
||||||
|
|
||||||
/* USB 2.0 Device */
|
/* PCI */
|
||||||
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
|
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
|
||||||
tlbtab_end
|
/* USB 2.0 Device */
|
||||||
|
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
|
||||||
|
tlbtab_end
|
||||||
|
|
|
@ -23,20 +23,112 @@
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <ppc4xx.h>
|
#include <ppc4xx.h>
|
||||||
|
#include <malloc.h>
|
||||||
|
#include <command.h>
|
||||||
|
#include <crc.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <spd_sdram.h>
|
#include <spd_sdram.h>
|
||||||
|
#include <status_led.h>
|
||||||
|
#include <sha1.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||||
|
|
||||||
static void set_leds(int val)
|
unsigned char sha1_checksum[SHA1_SUM_LEN];
|
||||||
|
|
||||||
|
/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
|
||||||
|
unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
|
||||||
|
0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
|
||||||
|
|
||||||
|
static void set_leds (int val)
|
||||||
{
|
{
|
||||||
unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
|
out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
|
||||||
0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
|
|
||||||
out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
|
||||||
|
|
||||||
|
void __led_init (led_id_t mask, int state)
|
||||||
|
{
|
||||||
|
int val = GET_LEDS;
|
||||||
|
|
||||||
|
if (state == STATUS_LED_ON)
|
||||||
|
val |= mask;
|
||||||
|
else
|
||||||
|
val &= ~mask;
|
||||||
|
set_leds (val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void __led_set (led_id_t mask, int state)
|
||||||
|
{
|
||||||
|
int val = GET_LEDS;
|
||||||
|
|
||||||
|
if (state == STATUS_LED_ON)
|
||||||
|
val |= mask;
|
||||||
|
else if (state == STATUS_LED_OFF)
|
||||||
|
val &= ~mask;
|
||||||
|
set_leds (val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void __led_toggle (led_id_t mask)
|
||||||
|
{
|
||||||
|
int val = GET_LEDS;
|
||||||
|
|
||||||
|
val ^= mask;
|
||||||
|
set_leds (val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void status_led_blink (void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
int val = GET_LEDS;
|
||||||
|
|
||||||
|
/* set all LED which are on, to state BLINKING */
|
||||||
|
for (i = 0; i < 4; i++) {
|
||||||
|
if (val & 0x08) status_led_set (i, STATUS_LED_BLINKING);
|
||||||
|
val = val << 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
|
||||||
|
void show_boot_progress (int val)
|
||||||
|
{
|
||||||
|
/* find all valid Codes for val in README */
|
||||||
|
if (val == -30) return;
|
||||||
|
if (val < 0) {
|
||||||
|
/* smthing goes wrong */
|
||||||
|
status_led_blink ();
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
switch (val) {
|
||||||
|
case 1:
|
||||||
|
/* validating Image */
|
||||||
|
status_led_set (0, STATUS_LED_OFF);
|
||||||
|
status_led_set (1, STATUS_LED_ON);
|
||||||
|
status_led_set (2, STATUS_LED_ON);
|
||||||
|
break;
|
||||||
|
case 15:
|
||||||
|
/* booting */
|
||||||
|
status_led_set (0, STATUS_LED_ON);
|
||||||
|
status_led_set (1, STATUS_LED_ON);
|
||||||
|
status_led_set (2, STATUS_LED_ON);
|
||||||
|
break;
|
||||||
|
case 64:
|
||||||
|
/* starting Ethernet configuration */
|
||||||
|
status_led_set (0, STATUS_LED_OFF);
|
||||||
|
status_led_set (1, STATUS_LED_OFF);
|
||||||
|
status_led_set (2, STATUS_LED_ON);
|
||||||
|
break;
|
||||||
|
case 80:
|
||||||
|
/* loading Image */
|
||||||
|
status_led_set (0, STATUS_LED_ON);
|
||||||
|
status_led_set (1, STATUS_LED_OFF);
|
||||||
|
status_led_set (2, STATUS_LED_ON);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int board_early_init_f(void)
|
int board_early_init_f(void)
|
||||||
{
|
{
|
||||||
register uint reg;
|
register uint reg;
|
||||||
|
@ -85,6 +177,251 @@ int board_early_init_f(void)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define EEPROM_LEN 256
|
||||||
|
void load_sernum_ethaddr (void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
char buf[EEPROM_LEN];
|
||||||
|
char mac[32];
|
||||||
|
char *use_eeprom;
|
||||||
|
u16 checksumcrc16 = 0;
|
||||||
|
|
||||||
|
/* read the MACs from EEprom */
|
||||||
|
status_led_set (0, STATUS_LED_ON);
|
||||||
|
status_led_set (1, STATUS_LED_ON);
|
||||||
|
ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN);
|
||||||
|
if (ret == 0) {
|
||||||
|
checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2);
|
||||||
|
/* check, if the EEprom is programmed:
|
||||||
|
* - The Prefix(Byte 0,1,2) is equal to "ATR"
|
||||||
|
* - The checksum, stored in the last 2 Bytes, is correct
|
||||||
|
*/
|
||||||
|
if ((strncmp (buf,"ATR",3) != 0) ||
|
||||||
|
((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
|
||||||
|
((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
|
||||||
|
/* EEprom is not programmed */
|
||||||
|
printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
|
||||||
|
} else {
|
||||||
|
/* get the MACs */
|
||||||
|
sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||||
|
buf[3],
|
||||||
|
buf[4],
|
||||||
|
buf[5],
|
||||||
|
buf[6],
|
||||||
|
buf[7],
|
||||||
|
buf[8]);
|
||||||
|
setenv ("ethaddr", (char *) mac);
|
||||||
|
sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||||
|
buf[9],
|
||||||
|
buf[10],
|
||||||
|
buf[11],
|
||||||
|
buf[12],
|
||||||
|
buf[13],
|
||||||
|
buf[14]);
|
||||||
|
setenv ("eth1addr", (char *) mac);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* some error reading the EEprom */
|
||||||
|
if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
|
||||||
|
/* dont use bootcmd */
|
||||||
|
setenv("bootdelay", "-1");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
/* == default ? use standard */
|
||||||
|
if (strncmp (use_eeprom, "default", 7) == 0) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
/* Env doesnt exist -> hang */
|
||||||
|
status_led_blink ();
|
||||||
|
hang ();
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_PREBOOT
|
||||||
|
|
||||||
|
static uchar kbd_magic_prefix[] = "key_magic";
|
||||||
|
static uchar kbd_command_prefix[] = "key_cmd";
|
||||||
|
|
||||||
|
struct kbd_data_t {
|
||||||
|
char s1;
|
||||||
|
char s2;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
|
||||||
|
{
|
||||||
|
char *val;
|
||||||
|
unsigned long tmp;
|
||||||
|
|
||||||
|
/* use the DIPs for some bootoptions */
|
||||||
|
val = getenv (ENV_NAME_DIP);
|
||||||
|
tmp = simple_strtoul (val, NULL, 16);
|
||||||
|
|
||||||
|
kbd_data->s2 = (tmp & 0x0f);
|
||||||
|
kbd_data->s1 = (tmp & 0xf0) >> 4;
|
||||||
|
return kbd_data;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
|
||||||
|
{
|
||||||
|
char s1 = str[0];
|
||||||
|
|
||||||
|
if (s1 >= '0' && s1 <= '9')
|
||||||
|
s1 -= '0';
|
||||||
|
else if (s1 >= 'a' && s1 <= 'f')
|
||||||
|
s1 = s1 - 'a' + 10;
|
||||||
|
else if (s1 >= 'A' && s1 <= 'F')
|
||||||
|
s1 = s1 - 'A' + 10;
|
||||||
|
else
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
if (s1 != kbd_data->s1) return -1;
|
||||||
|
|
||||||
|
s1 = str[1];
|
||||||
|
if (s1 >= '0' && s1 <= '9')
|
||||||
|
s1 -= '0';
|
||||||
|
else if (s1 >= 'a' && s1 <= 'f')
|
||||||
|
s1 = s1 - 'a' + 10;
|
||||||
|
else if (s1 >= 'A' && s1 <= 'F')
|
||||||
|
s1 = s1 - 'A' + 10;
|
||||||
|
else
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
if (s1 != kbd_data->s2) return -1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static char *key_match (const struct kbd_data_t *kbd_data)
|
||||||
|
{
|
||||||
|
char magic[sizeof (kbd_magic_prefix) + 1];
|
||||||
|
char *suffix;
|
||||||
|
char *kbd_magic_keys;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The following string defines the characters that can be appended
|
||||||
|
* to "key_magic" to form the names of environment variables that
|
||||||
|
* hold "magic" key codes, i. e. such key codes that can cause
|
||||||
|
* pre-boot actions. If the string is empty (""), then only
|
||||||
|
* "key_magic" is checked (old behaviour); the string "125" causes
|
||||||
|
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
|
||||||
|
*/
|
||||||
|
if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
|
||||||
|
kbd_magic_keys = "";
|
||||||
|
|
||||||
|
/* loop over all magic keys;
|
||||||
|
* use '\0' suffix in case of empty string
|
||||||
|
*/
|
||||||
|
for (suffix = kbd_magic_keys; *suffix ||
|
||||||
|
suffix == kbd_magic_keys; ++suffix) {
|
||||||
|
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
|
||||||
|
if (compare_magic (kbd_data, getenv (magic)) == 0) {
|
||||||
|
char cmd_name[sizeof (kbd_command_prefix) + 1];
|
||||||
|
char *cmd;
|
||||||
|
|
||||||
|
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
|
||||||
|
cmd = getenv (cmd_name);
|
||||||
|
|
||||||
|
return (cmd);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_PREBOOT */
|
||||||
|
|
||||||
|
static int pcs440ep_readinputs (void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
char value[20];
|
||||||
|
|
||||||
|
/* read the inputs and set the Envvars */
|
||||||
|
/* Revision Level Bit 26 - 29 */
|
||||||
|
i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
|
||||||
|
i = swapbits[i];
|
||||||
|
sprintf (value, "%02x", i);
|
||||||
|
setenv (ENV_NAME_REVLEV, value);
|
||||||
|
/* Solder Switch Bit 30 - 33 */
|
||||||
|
i = (in32 (GPIO0_IR) & 0x00000003) << 2;
|
||||||
|
i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
|
||||||
|
i = swapbits[i];
|
||||||
|
sprintf (value, "%02x", i);
|
||||||
|
setenv (ENV_NAME_SOLDER, value);
|
||||||
|
/* DIP Switch Bit 49 - 56 */
|
||||||
|
i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
|
||||||
|
i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
|
||||||
|
sprintf (value, "%02x", i);
|
||||||
|
setenv (ENV_NAME_DIP, value);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(CONFIG_SHA1_CHECK_UB_IMG)
|
||||||
|
/*************************************************************************
|
||||||
|
* calculate a SHA1 sum for the U-Boot image in Flash.
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
static int pcs440ep_sha1 (int docheck)
|
||||||
|
{
|
||||||
|
unsigned char *data;
|
||||||
|
unsigned char *ptroff;
|
||||||
|
unsigned char output[20];
|
||||||
|
unsigned char org[20];
|
||||||
|
int i, len = CONFIG_SHA1_LEN;
|
||||||
|
|
||||||
|
memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
|
||||||
|
data = (unsigned char *)CFG_LOAD_ADDR;
|
||||||
|
ptroff = &data[len + SHA1_SUM_POS];
|
||||||
|
|
||||||
|
for (i = 0; i < SHA1_SUM_LEN; i++) {
|
||||||
|
org[i] = ptroff[i];
|
||||||
|
ptroff[i] = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
|
||||||
|
|
||||||
|
if (docheck == 2) {
|
||||||
|
for (i = 0; i < 20 ; i++) {
|
||||||
|
printf("%02X ", output[i]);
|
||||||
|
}
|
||||||
|
printf("\n");
|
||||||
|
}
|
||||||
|
if (docheck == 1) {
|
||||||
|
for (i = 0; i < 20 ; i++) {
|
||||||
|
if (org[i] != output[i]) return 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* do some checks after the SHA1 checksum from the U-Boot Image was
|
||||||
|
* calculated.
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
static void pcs440ep_checksha1 (void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
char *cs_test;
|
||||||
|
|
||||||
|
ret = pcs440ep_sha1 (1);
|
||||||
|
if (ret == 0) return;
|
||||||
|
|
||||||
|
if ((cs_test = getenv ("cs_test")) == NULL) {
|
||||||
|
/* Env doesnt exist -> hang */
|
||||||
|
status_led_blink ();
|
||||||
|
hang ();
|
||||||
|
}
|
||||||
|
|
||||||
|
if (strncmp (cs_test, "off", 3) == 0) {
|
||||||
|
printf ("SHA1 U-Boot sum NOT ok!\n");
|
||||||
|
setenv ("bootdelay", "-1");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
|
||||||
|
#endif
|
||||||
|
|
||||||
int misc_init_r (void)
|
int misc_init_r (void)
|
||||||
{
|
{
|
||||||
uint pbcr;
|
uint pbcr;
|
||||||
|
@ -139,6 +476,18 @@ int misc_init_r (void)
|
||||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||||
&flash_info[1]);
|
&flash_info[1]);
|
||||||
|
|
||||||
|
pcs440ep_readinputs ();
|
||||||
|
pcs440ep_checksha1 ();
|
||||||
|
#ifdef CONFIG_PREBOOT
|
||||||
|
{
|
||||||
|
struct kbd_data_t kbd_data;
|
||||||
|
/* Decode keys */
|
||||||
|
char *str = strdup (key_match (get_keys (&kbd_data)));
|
||||||
|
/* Set or delete definition */
|
||||||
|
setenv ("preboot", str);
|
||||||
|
free (str);
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_PREBOOT */
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -156,13 +505,31 @@ int checkboard(void)
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void spd_ddr_init_hang (void)
|
||||||
|
{
|
||||||
|
status_led_set (0, STATUS_LED_OFF);
|
||||||
|
status_led_set (1, STATUS_LED_ON);
|
||||||
|
/* we cannot use hang() because we are still running from
|
||||||
|
Flash, and so the status_led driver is not initialized */
|
||||||
|
puts ("### ERROR ### Please RESET the board ###\n");
|
||||||
|
for (;;) {
|
||||||
|
__led_toggle (4);
|
||||||
|
udelay (100000);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
|
|
||||||
set_leds(1); /* display boot info counter */
|
status_led_set (0, STATUS_LED_ON);
|
||||||
|
status_led_set (1, STATUS_LED_OFF);
|
||||||
dram_size = spd_sdram();
|
dram_size = spd_sdram();
|
||||||
set_leds(2); /* display boot info counter */
|
status_led_set (0, STATUS_LED_OFF);
|
||||||
|
status_led_set (1, STATUS_LED_ON);
|
||||||
|
if (dram_size == 0) {
|
||||||
|
hang();
|
||||||
|
}
|
||||||
|
|
||||||
return dram_size;
|
return dram_size;
|
||||||
}
|
}
|
||||||
|
@ -377,3 +744,119 @@ void hw_watchdog_reset(void)
|
||||||
|
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* "led" Commando for the U-Boot shell
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
int rcode = 0;
|
||||||
|
ulong pattern = 0;
|
||||||
|
|
||||||
|
pattern = simple_strtoul (argv[1], NULL, 10);
|
||||||
|
if (pattern > 200) {
|
||||||
|
status_led_blink ();
|
||||||
|
hang ();
|
||||||
|
return rcode;
|
||||||
|
}
|
||||||
|
if (pattern > 100) {
|
||||||
|
status_led_blink ();
|
||||||
|
return rcode;
|
||||||
|
}
|
||||||
|
pattern &= 0x0f;
|
||||||
|
set_leds (pattern);
|
||||||
|
return rcode;
|
||||||
|
}
|
||||||
|
|
||||||
|
U_BOOT_CMD(
|
||||||
|
led, 2, 1, do_led,
|
||||||
|
"led - set the led\n",
|
||||||
|
NULL
|
||||||
|
);
|
||||||
|
|
||||||
|
#if defined(CONFIG_SHA1_CHECK_UB_IMG)
|
||||||
|
/*************************************************************************
|
||||||
|
* "sha1" Commando for the U-Boot shell
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
int rcode = -1;
|
||||||
|
|
||||||
|
if (argc < 2) {
|
||||||
|
usage:
|
||||||
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (argc >= 3) {
|
||||||
|
unsigned char *data;
|
||||||
|
unsigned char output[20];
|
||||||
|
int len;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
|
||||||
|
len = simple_strtoul (argv[2], NULL, 16);
|
||||||
|
sha1_csum (data, len, (unsigned char *)output);
|
||||||
|
printf ("U-Boot sum:\n");
|
||||||
|
for (i = 0; i < 20 ; i++) {
|
||||||
|
printf ("%02X ", output[i]);
|
||||||
|
}
|
||||||
|
printf ("\n");
|
||||||
|
if (argc == 4) {
|
||||||
|
data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
|
||||||
|
memcpy (data, output, 20);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
if (argc == 2) {
|
||||||
|
char *ptr = argv[1];
|
||||||
|
if (*ptr != '-') goto usage;
|
||||||
|
ptr++;
|
||||||
|
if ((*ptr == 'c') || (*ptr == 'C')) {
|
||||||
|
rcode = pcs440ep_sha1 (1);
|
||||||
|
printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
|
||||||
|
} else if ((*ptr == 'p') || (*ptr == 'P')) {
|
||||||
|
rcode = pcs440ep_sha1 (2);
|
||||||
|
} else {
|
||||||
|
rcode = pcs440ep_sha1 (0);
|
||||||
|
}
|
||||||
|
return rcode;
|
||||||
|
}
|
||||||
|
return rcode;
|
||||||
|
}
|
||||||
|
|
||||||
|
U_BOOT_CMD(
|
||||||
|
sha1, 4, 1, do_sha1,
|
||||||
|
"sha1 - calculate the SHA1 Sum\n",
|
||||||
|
"address len [addr] calculate the SHA1 sum [save at addr]\n"
|
||||||
|
" -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
|
||||||
|
" -c check the U-Boot image in flash\n"
|
||||||
|
);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_IDE_PREINIT
|
||||||
|
int ide_preinit (void)
|
||||||
|
{
|
||||||
|
/* Set True IDE Mode */
|
||||||
|
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
|
||||||
|
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
|
||||||
|
out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
|
||||||
|
udelay (100000);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
|
||||||
|
void ide_set_reset (int idereset)
|
||||||
|
{
|
||||||
|
debug ("ide_reset(%d)\n", idereset);
|
||||||
|
if (idereset == 0) {
|
||||||
|
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
|
||||||
|
} else {
|
||||||
|
out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
|
||||||
|
}
|
||||||
|
udelay (10000);
|
||||||
|
}
|
||||||
|
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
|
||||||
|
|
|
@ -65,6 +65,7 @@ SECTIONS
|
||||||
{
|
{
|
||||||
cpu/ppc4xx/start.o (.text)
|
cpu/ppc4xx/start.o (.text)
|
||||||
board/pcs440ep/init.o (.text)
|
board/pcs440ep/init.o (.text)
|
||||||
|
lib_generic/sha1.o (.text)
|
||||||
|
|
||||||
*(.text)
|
*(.text)
|
||||||
*(.fixup)
|
*(.fixup)
|
||||||
|
|
|
@ -507,6 +507,7 @@ int dram_init(void)
|
||||||
|
|
||||||
void show_boot_progress(int val)
|
void show_boot_progress(int val)
|
||||||
{
|
{
|
||||||
|
if (val < -32) val = -1; /* let things compatible */
|
||||||
outb(val&0xff, 0x80);
|
outb(val&0xff, 0x80);
|
||||||
outb((val&0xff00)>>8, 0x680);
|
outb((val&0xff00)>>8, 0x680);
|
||||||
}
|
}
|
||||||
|
|
|
@ -507,6 +507,7 @@ void show_boot_progress(int val)
|
||||||
{
|
{
|
||||||
int version = read_mmcr_byte(SC520_SYSINFO);
|
int version = read_mmcr_byte(SC520_SYSINFO);
|
||||||
|
|
||||||
|
if (val < -32) val = -1; /* let things compatible */
|
||||||
if (version == 0) {
|
if (version == 0) {
|
||||||
/* PIO31-PIO16 Data */
|
/* PIO31-PIO16 Data */
|
||||||
write_mmcr_word(SC520_PIODATA31_16,
|
write_mmcr_word(SC520_PIODATA31_16,
|
||||||
|
|
|
@ -52,147 +52,147 @@ long int fixed_sdram (void);
|
||||||
const iop_conf_t iop_conf_tab[4][32] = {
|
const iop_conf_t iop_conf_tab[4][32] = {
|
||||||
|
|
||||||
/* Port A configuration */
|
/* Port A configuration */
|
||||||
{ /* conf ppar psor pdir podr pdat */
|
{ /* conf ppar psor pdir podr pdat */
|
||||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
|
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
|
||||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
|
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
|
||||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
|
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
|
||||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
|
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
|
||||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
|
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
|
||||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
|
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
|
||||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
|
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
|
||||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
|
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
|
||||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
|
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
|
||||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
|
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
|
||||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
|
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
|
||||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
|
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
|
||||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
|
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
|
||||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
|
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
|
||||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
|
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
|
||||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
|
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
|
||||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
|
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
|
||||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
|
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
|
||||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
|
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
|
||||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
|
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
|
||||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
|
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
|
||||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
|
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
|
||||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
|
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
|
||||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
|
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
|
||||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
|
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
|
||||||
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
|
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
|
||||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
|
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
|
||||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
|
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
|
||||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
|
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
|
||||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
|
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
|
||||||
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
|
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
|
||||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
|
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
|
||||||
},
|
},
|
||||||
|
|
||||||
/* Port B configuration */
|
/* Port B configuration */
|
||||||
{ /* conf ppar psor pdir podr pdat */
|
{ /* conf ppar psor pdir podr pdat */
|
||||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
||||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
||||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
||||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
||||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
||||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
||||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
||||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
||||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
||||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
||||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
||||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
||||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
||||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
||||||
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
|
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
|
||||||
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
|
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
|
||||||
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
|
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
|
||||||
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
|
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
|
||||||
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
|
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
|
||||||
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
|
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
|
||||||
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
||||||
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
||||||
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
||||||
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
||||||
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
||||||
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
||||||
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
||||||
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
||||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||||
},
|
},
|
||||||
|
|
||||||
/* Port C */
|
/* Port C */
|
||||||
{ /* conf ppar psor pdir podr pdat */
|
{ /* conf ppar psor pdir podr pdat */
|
||||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
|
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
|
||||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
|
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
|
||||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
||||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
|
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
|
||||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
|
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
|
||||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
|
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
|
||||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
|
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
|
||||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
||||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
||||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
||||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
||||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
||||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
|
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
|
||||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
|
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
|
||||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
|
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
|
||||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
|
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
|
||||||
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
|
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
|
||||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
||||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
|
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
|
||||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
|
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
|
||||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
|
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
|
||||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
|
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
|
||||||
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
|
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
|
||||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
|
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
|
||||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
||||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
||||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
||||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
||||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
||||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
||||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
||||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
||||||
},
|
},
|
||||||
|
|
||||||
/* Port D */
|
/* Port D */
|
||||||
{ /* conf ppar psor pdir podr pdat */
|
{ /* conf ppar psor pdir podr pdat */
|
||||||
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
||||||
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
||||||
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
|
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
|
||||||
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
|
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
|
||||||
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
|
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
|
||||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
|
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
|
||||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
||||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
||||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
|
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
|
||||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
|
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
|
||||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
|
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
|
||||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
|
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
|
||||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
||||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
|
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
|
||||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
||||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
||||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||||
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
|
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
|
||||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
||||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
||||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
||||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
|
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
|
||||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -227,12 +227,12 @@ reset_phy(void)
|
||||||
#if (CONFIG_ETHER_INDEX == 2)
|
#if (CONFIG_ETHER_INDEX == 2)
|
||||||
bcsr->bcsr2 &= ~FETH2_RST;
|
bcsr->bcsr2 &= ~FETH2_RST;
|
||||||
udelay(2);
|
udelay(2);
|
||||||
bcsr->bcsr2 |= FETH2_RST;
|
bcsr->bcsr2 |= FETH2_RST;
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
#elif (CONFIG_ETHER_INDEX == 3)
|
#elif (CONFIG_ETHER_INDEX == 3)
|
||||||
bcsr->bcsr3 &= ~FETH3_RST;
|
bcsr->bcsr3 &= ~FETH3_RST;
|
||||||
udelay(2);
|
udelay(2);
|
||||||
bcsr->bcsr3 |= FETH3_RST;
|
bcsr->bcsr3 |= FETH3_RST;
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
|
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
|
||||||
|
@ -252,10 +252,10 @@ int
|
||||||
board_early_init_f(void)
|
board_early_init_f(void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
||||||
volatile ccsr_pcix_t *pci = &immr->im_pcix;
|
volatile ccsr_pcix_t *pci = &immr->im_pcix;
|
||||||
|
|
||||||
pci->peer &= 0xfffffffdf; /* disable master abort */
|
pci->peer &= 0xffffffdf; /* disable master abort */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Why is the phy reset done _after_ the ethernet
|
/* Why is the phy reset done _after_ the ethernet
|
||||||
|
|
|
@ -216,6 +216,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
image_header_t *hdr;
|
image_header_t *hdr;
|
||||||
int rcode = 0;
|
int rcode = 0;
|
||||||
|
|
||||||
|
SHOW_BOOT_PROGRESS (34);
|
||||||
switch (argc) {
|
switch (argc) {
|
||||||
case 1:
|
case 1:
|
||||||
addr = CFG_LOAD_ADDR;
|
addr = CFG_LOAD_ADDR;
|
||||||
|
@ -236,24 +237,27 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-35);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
SHOW_BOOT_PROGRESS (35);
|
||||||
if (!boot_device) {
|
if (!boot_device) {
|
||||||
puts ("\n** No boot device **\n");
|
puts ("\n** No boot device **\n");
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-36);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (36);
|
||||||
|
|
||||||
dev = simple_strtoul(boot_device, &ep, 16);
|
dev = simple_strtoul(boot_device, &ep, 16);
|
||||||
|
|
||||||
if ((dev >= CFG_MAX_DOC_DEVICE) ||
|
if ((dev >= CFG_MAX_DOC_DEVICE) ||
|
||||||
(doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) {
|
(doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) {
|
||||||
printf ("\n** Device %d not available\n", dev);
|
printf ("\n** Device %d not available\n", dev);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-37);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (37);
|
||||||
|
|
||||||
printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n",
|
printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n",
|
||||||
dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr,
|
dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr,
|
||||||
|
@ -262,9 +266,10 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
if (doc_rw (doc_dev_desc + dev, 1, offset,
|
if (doc_rw (doc_dev_desc + dev, 1, offset,
|
||||||
SECTORSIZE, NULL, (u_char *)addr)) {
|
SECTORSIZE, NULL, (u_char *)addr)) {
|
||||||
printf ("** Read error on %d\n", dev);
|
printf ("** Read error on %d\n", dev);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-38);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (38);
|
||||||
|
|
||||||
hdr = (image_header_t *)addr;
|
hdr = (image_header_t *)addr;
|
||||||
|
|
||||||
|
@ -276,16 +281,18 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
cnt -= SECTORSIZE;
|
cnt -= SECTORSIZE;
|
||||||
} else {
|
} else {
|
||||||
puts ("\n** Bad Magic Number **\n");
|
puts ("\n** Bad Magic Number **\n");
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-39);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (39);
|
||||||
|
|
||||||
if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt,
|
if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt,
|
||||||
NULL, (u_char *)(addr+SECTORSIZE))) {
|
NULL, (u_char *)(addr+SECTORSIZE))) {
|
||||||
printf ("** Read error on %d\n", dev);
|
printf ("** Read error on %d\n", dev);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-40);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (40);
|
||||||
|
|
||||||
/* Loading ok, update default load address */
|
/* Loading ok, update default load address */
|
||||||
|
|
||||||
|
|
|
@ -185,6 +185,9 @@ static void input_data(int dev, ulong *sect_buf, int words);
|
||||||
static void output_data(int dev, ulong *sect_buf, int words);
|
static void output_data(int dev, ulong *sect_buf, int words);
|
||||||
static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
|
static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
|
||||||
|
|
||||||
|
#ifndef CFG_ATA_PORT_ADDR
|
||||||
|
#define CFG_ATA_PORT_ADDR(port) (port)
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ATAPI
|
#ifdef CONFIG_ATAPI
|
||||||
static void atapi_inquiry(block_dev_desc_t *dev_desc);
|
static void atapi_inquiry(block_dev_desc_t *dev_desc);
|
||||||
|
@ -382,6 +385,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
image_header_t *hdr;
|
image_header_t *hdr;
|
||||||
int rcode = 0;
|
int rcode = 0;
|
||||||
|
|
||||||
|
SHOW_BOOT_PROGRESS (41);
|
||||||
switch (argc) {
|
switch (argc) {
|
||||||
case 1:
|
case 1:
|
||||||
addr = CFG_LOAD_ADDR;
|
addr = CFG_LOAD_ADDR;
|
||||||
|
@ -397,44 +401,50 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-42);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (42);
|
||||||
|
|
||||||
if (!boot_device) {
|
if (!boot_device) {
|
||||||
puts ("\n** No boot device **\n");
|
puts ("\n** No boot device **\n");
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-43);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (43);
|
||||||
|
|
||||||
dev = simple_strtoul(boot_device, &ep, 16);
|
dev = simple_strtoul(boot_device, &ep, 16);
|
||||||
|
|
||||||
if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) {
|
if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) {
|
||||||
printf ("\n** Device %d not available\n", dev);
|
printf ("\n** Device %d not available\n", dev);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-44);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (44);
|
||||||
|
|
||||||
if (*ep) {
|
if (*ep) {
|
||||||
if (*ep != ':') {
|
if (*ep != ':') {
|
||||||
puts ("\n** Invalid boot device, use `dev[:part]' **\n");
|
puts ("\n** Invalid boot device, use `dev[:part]' **\n");
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-45);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
part = simple_strtoul(++ep, NULL, 16);
|
part = simple_strtoul(++ep, NULL, 16);
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (45);
|
||||||
if (get_partition_info (&ide_dev_desc[dev], part, &info)) {
|
if (get_partition_info (&ide_dev_desc[dev], part, &info)) {
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-46);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (46);
|
||||||
if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
|
if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
|
||||||
(strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
|
(strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
|
||||||
printf ("\n** Invalid partition type \"%.32s\""
|
printf ("\n** Invalid partition type \"%.32s\""
|
||||||
" (expect \"" BOOT_PART_TYPE "\")\n",
|
" (expect \"" BOOT_PART_TYPE "\")\n",
|
||||||
info.type);
|
info.type);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-47);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (47);
|
||||||
|
|
||||||
printf ("\nLoading from IDE device %d, partition %d: "
|
printf ("\nLoading from IDE device %d, partition %d: "
|
||||||
"Name: %.32s Type: %.32s\n",
|
"Name: %.32s Type: %.32s\n",
|
||||||
|
@ -445,26 +455,29 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
|
||||||
if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) {
|
if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) {
|
||||||
printf ("** Read error on %d:%d\n", dev, part);
|
printf ("** Read error on %d:%d\n", dev, part);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-48);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (48);
|
||||||
|
|
||||||
hdr = (image_header_t *)addr;
|
hdr = (image_header_t *)addr;
|
||||||
|
|
||||||
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
|
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
|
||||||
printf("\n** Bad Magic Number **\n");
|
printf("\n** Bad Magic Number **\n");
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-49);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (49);
|
||||||
|
|
||||||
checksum = ntohl(hdr->ih_hcrc);
|
checksum = ntohl(hdr->ih_hcrc);
|
||||||
hdr->ih_hcrc = 0;
|
hdr->ih_hcrc = 0;
|
||||||
|
|
||||||
if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
|
if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
|
||||||
puts ("\n** Bad Header Checksum **\n");
|
puts ("\n** Bad Header Checksum **\n");
|
||||||
SHOW_BOOT_PROGRESS (-2);
|
SHOW_BOOT_PROGRESS (-50);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (50);
|
||||||
hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */
|
hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */
|
||||||
|
|
||||||
print_image_hdr (hdr);
|
print_image_hdr (hdr);
|
||||||
|
@ -477,9 +490,10 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt,
|
if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt,
|
||||||
(ulong *)(addr+info.blksz)) != cnt) {
|
(ulong *)(addr+info.blksz)) != cnt) {
|
||||||
printf ("** Read error on %d:%d\n", dev, part);
|
printf ("** Read error on %d:%d\n", dev, part);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-51);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS (51);
|
||||||
|
|
||||||
|
|
||||||
/* Loading ok, update default load address */
|
/* Loading ok, update default load address */
|
||||||
|
@ -807,13 +821,13 @@ ide_outb(int dev, int port, unsigned char val)
|
||||||
|
|
||||||
/* Ensure I/O operations complete */
|
/* Ensure I/O operations complete */
|
||||||
EIEIO;
|
EIEIO;
|
||||||
*((uchar *)(ATA_CURR_BASE(dev)+port)) = val;
|
*((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))) = val;
|
||||||
}
|
}
|
||||||
#else /* ! __PPC__ */
|
#else /* ! __PPC__ */
|
||||||
static void __inline__
|
static void __inline__
|
||||||
ide_outb(int dev, int port, unsigned char val)
|
ide_outb(int dev, int port, unsigned char val)
|
||||||
{
|
{
|
||||||
outb(val, ATA_CURR_BASE(dev)+port);
|
outb(val, ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port));
|
||||||
}
|
}
|
||||||
#endif /* __PPC__ */
|
#endif /* __PPC__ */
|
||||||
|
|
||||||
|
@ -825,7 +839,7 @@ ide_inb(int dev, int port)
|
||||||
uchar val;
|
uchar val;
|
||||||
/* Ensure I/O operations complete */
|
/* Ensure I/O operations complete */
|
||||||
EIEIO;
|
EIEIO;
|
||||||
val = *((uchar *)(ATA_CURR_BASE(dev)+port));
|
val = *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
|
||||||
debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
|
debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
|
||||||
dev, port, (ATA_CURR_BASE(dev)+port), val);
|
dev, port, (ATA_CURR_BASE(dev)+port), val);
|
||||||
return (val);
|
return (val);
|
||||||
|
@ -834,7 +848,7 @@ ide_inb(int dev, int port)
|
||||||
static unsigned char __inline__
|
static unsigned char __inline__
|
||||||
ide_inb(int dev, int port)
|
ide_inb(int dev, int port)
|
||||||
{
|
{
|
||||||
return inb(ATA_CURR_BASE(dev)+port);
|
return inb(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port));
|
||||||
}
|
}
|
||||||
#endif /* __PPC__ */
|
#endif /* __PPC__ */
|
||||||
|
|
||||||
|
@ -891,6 +905,9 @@ input_swap_data(int dev, ulong *sect_buf, int words)
|
||||||
#ifdef __MIPS__
|
#ifdef __MIPS__
|
||||||
*dbuf++ = swab16p((u16*)pbuf);
|
*dbuf++ = swab16p((u16*)pbuf);
|
||||||
*dbuf++ = swab16p((u16*)pbuf);
|
*dbuf++ = swab16p((u16*)pbuf);
|
||||||
|
#elif defined(CONFIG_PCS440EP)
|
||||||
|
*dbuf++ = *pbuf;
|
||||||
|
*dbuf++ = *pbuf;
|
||||||
#else
|
#else
|
||||||
*dbuf++ = ld_le16(pbuf);
|
*dbuf++ = ld_le16(pbuf);
|
||||||
*dbuf++ = ld_le16(pbuf);
|
*dbuf++ = ld_le16(pbuf);
|
||||||
|
@ -930,10 +947,18 @@ output_data(int dev, ulong *sect_buf, int words)
|
||||||
pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
|
pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
|
||||||
dbuf = (ushort *)sect_buf;
|
dbuf = (ushort *)sect_buf;
|
||||||
while (words--) {
|
while (words--) {
|
||||||
|
#if defined(CONFIG_PCS440EP)
|
||||||
|
/* not tested, because CF was write protected */
|
||||||
|
EIEIO;
|
||||||
|
*pbuf = ld_le16(dbuf++);
|
||||||
|
EIEIO;
|
||||||
|
*pbuf = ld_le16(dbuf++);
|
||||||
|
#else
|
||||||
EIEIO;
|
EIEIO;
|
||||||
*pbuf = *dbuf++;
|
*pbuf = *dbuf++;
|
||||||
EIEIO;
|
EIEIO;
|
||||||
*pbuf = *dbuf++;
|
*pbuf = *dbuf++;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -981,10 +1006,17 @@ input_data(int dev, ulong *sect_buf, int words)
|
||||||
debug("in input data base for read is %lx\n", (unsigned long) pbuf);
|
debug("in input data base for read is %lx\n", (unsigned long) pbuf);
|
||||||
|
|
||||||
while (words--) {
|
while (words--) {
|
||||||
|
#if defined(CONFIG_PCS440EP)
|
||||||
|
EIEIO;
|
||||||
|
*dbuf++ = ld_le16(pbuf);
|
||||||
|
EIEIO;
|
||||||
|
*dbuf++ = ld_le16(pbuf);
|
||||||
|
#else
|
||||||
EIEIO;
|
EIEIO;
|
||||||
*dbuf++ = *pbuf;
|
*dbuf++ = *pbuf;
|
||||||
EIEIO;
|
EIEIO;
|
||||||
*dbuf++ = *pbuf;
|
*dbuf++ = *pbuf;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
|
@ -486,17 +486,19 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
|
||||||
r = nand_read(nand, offset, &cnt, (u_char *) addr);
|
r = nand_read(nand, offset, &cnt, (u_char *) addr);
|
||||||
if (r) {
|
if (r) {
|
||||||
puts("** Read error\n");
|
puts("** Read error\n");
|
||||||
SHOW_BOOT_PROGRESS(-1);
|
SHOW_BOOT_PROGRESS(-56);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(56);
|
||||||
|
|
||||||
hdr = (image_header_t *) addr;
|
hdr = (image_header_t *) addr;
|
||||||
|
|
||||||
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
|
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
|
||||||
printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
|
printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
|
||||||
SHOW_BOOT_PROGRESS(-1);
|
SHOW_BOOT_PROGRESS(-57);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(57);
|
||||||
|
|
||||||
print_image_hdr(hdr);
|
print_image_hdr(hdr);
|
||||||
|
|
||||||
|
@ -505,9 +507,10 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
|
||||||
r = nand_read(nand, offset, &cnt, (u_char *) addr);
|
r = nand_read(nand, offset, &cnt, (u_char *) addr);
|
||||||
if (r) {
|
if (r) {
|
||||||
puts("** Read error\n");
|
puts("** Read error\n");
|
||||||
SHOW_BOOT_PROGRESS(-1);
|
SHOW_BOOT_PROGRESS(-58);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(58);
|
||||||
|
|
||||||
/* Loading ok, update default load address */
|
/* Loading ok, update default load address */
|
||||||
|
|
||||||
|
@ -559,6 +562,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
SHOW_BOOT_PROGRESS(52);
|
||||||
switch (argc) {
|
switch (argc) {
|
||||||
case 1:
|
case 1:
|
||||||
addr = CFG_LOAD_ADDR;
|
addr = CFG_LOAD_ADDR;
|
||||||
|
@ -582,23 +586,26 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||||
usage:
|
usage:
|
||||||
#endif
|
#endif
|
||||||
printf("Usage:\n%s\n", cmdtp->usage);
|
printf("Usage:\n%s\n", cmdtp->usage);
|
||||||
SHOW_BOOT_PROGRESS(-1);
|
SHOW_BOOT_PROGRESS(-53);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
SHOW_BOOT_PROGRESS(53);
|
||||||
if (!boot_device) {
|
if (!boot_device) {
|
||||||
puts("\n** No boot device **\n");
|
puts("\n** No boot device **\n");
|
||||||
SHOW_BOOT_PROGRESS(-1);
|
SHOW_BOOT_PROGRESS(-54);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(54);
|
||||||
|
|
||||||
idx = simple_strtoul(boot_device, NULL, 16);
|
idx = simple_strtoul(boot_device, NULL, 16);
|
||||||
|
|
||||||
if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) {
|
if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) {
|
||||||
printf("\n** Device %d not available\n", idx);
|
printf("\n** Device %d not available\n", idx);
|
||||||
SHOW_BOOT_PROGRESS(-1);
|
SHOW_BOOT_PROGRESS(-55);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(55);
|
||||||
|
|
||||||
return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
|
return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
|
||||||
}
|
}
|
||||||
|
@ -887,6 +894,7 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
ulong offset = 0;
|
ulong offset = 0;
|
||||||
image_header_t *hdr;
|
image_header_t *hdr;
|
||||||
int rcode = 0;
|
int rcode = 0;
|
||||||
|
SHOW_BOOT_PROGRESS(52);
|
||||||
switch (argc) {
|
switch (argc) {
|
||||||
case 1:
|
case 1:
|
||||||
addr = CFG_LOAD_ADDR;
|
addr = CFG_LOAD_ADDR;
|
||||||
|
@ -907,24 +915,27 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-53);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
SHOW_BOOT_PROGRESS(53);
|
||||||
if (!boot_device) {
|
if (!boot_device) {
|
||||||
puts ("\n** No boot device **\n");
|
puts ("\n** No boot device **\n");
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-54);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(54);
|
||||||
|
|
||||||
dev = simple_strtoul(boot_device, &ep, 16);
|
dev = simple_strtoul(boot_device, &ep, 16);
|
||||||
|
|
||||||
if ((dev >= CFG_MAX_NAND_DEVICE) ||
|
if ((dev >= CFG_MAX_NAND_DEVICE) ||
|
||||||
(nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
|
(nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
|
||||||
printf ("\n** Device %d not available\n", dev);
|
printf ("\n** Device %d not available\n", dev);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-55);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(55);
|
||||||
|
|
||||||
printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
|
printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
|
||||||
dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
|
dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
|
||||||
|
@ -933,9 +944,10 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset,
|
if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset,
|
||||||
SECTORSIZE, NULL, (u_char *)addr)) {
|
SECTORSIZE, NULL, (u_char *)addr)) {
|
||||||
printf ("** Read error on %d\n", dev);
|
printf ("** Read error on %d\n", dev);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-56);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(56);
|
||||||
|
|
||||||
hdr = (image_header_t *)addr;
|
hdr = (image_header_t *)addr;
|
||||||
|
|
||||||
|
@ -947,17 +959,19 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
cnt -= SECTORSIZE;
|
cnt -= SECTORSIZE;
|
||||||
} else {
|
} else {
|
||||||
printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic));
|
printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic));
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-57);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(57);
|
||||||
|
|
||||||
if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ,
|
if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ,
|
||||||
offset + SECTORSIZE, cnt, NULL,
|
offset + SECTORSIZE, cnt, NULL,
|
||||||
(u_char *)(addr+SECTORSIZE))) {
|
(u_char *)(addr+SECTORSIZE))) {
|
||||||
printf ("** Read error on %d\n", dev);
|
printf ("** Read error on %d\n", dev);
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-58);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
SHOW_BOOT_PROGRESS(58);
|
||||||
|
|
||||||
/* Loading ok, update default load address */
|
/* Loading ok, update default load address */
|
||||||
|
|
||||||
|
|
|
@ -30,6 +30,13 @@
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_NET)
|
#if defined(CONFIG_CMD_NET)
|
||||||
|
|
||||||
|
#ifdef CONFIG_SHOW_BOOT_PROGRESS
|
||||||
|
# include <status_led.h>
|
||||||
|
extern void show_boot_progress (int val);
|
||||||
|
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg)
|
||||||
|
#else
|
||||||
|
# define SHOW_BOOT_PROGRESS(arg)
|
||||||
|
#endif
|
||||||
|
|
||||||
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
|
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
|
||||||
|
|
||||||
|
@ -186,18 +193,25 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default: printf ("Usage:\n%s\n", cmdtp->usage);
|
default: printf ("Usage:\n%s\n", cmdtp->usage);
|
||||||
|
SHOW_BOOT_PROGRESS(-80);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((size = NetLoop(proto)) < 0)
|
SHOW_BOOT_PROGRESS(80);
|
||||||
|
if ((size = NetLoop(proto)) < 0) {
|
||||||
|
SHOW_BOOT_PROGRESS(-81);
|
||||||
return 1;
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
SHOW_BOOT_PROGRESS(81);
|
||||||
/* NetLoop ok, update environment */
|
/* NetLoop ok, update environment */
|
||||||
netboot_update_env();
|
netboot_update_env();
|
||||||
|
|
||||||
/* done if no file was loaded (no errors though) */
|
/* done if no file was loaded (no errors though) */
|
||||||
if (size == 0)
|
if (size == 0) {
|
||||||
|
SHOW_BOOT_PROGRESS(-82);
|
||||||
return 0;
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
/* flush cache */
|
/* flush cache */
|
||||||
flush_cache(load_addr, size);
|
flush_cache(load_addr, size);
|
||||||
|
@ -210,14 +224,22 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
|
||||||
|
|
||||||
printf ("Automatic boot of image at addr 0x%08lX ...\n",
|
printf ("Automatic boot of image at addr 0x%08lX ...\n",
|
||||||
load_addr);
|
load_addr);
|
||||||
|
SHOW_BOOT_PROGRESS(82);
|
||||||
rcode = do_bootm (cmdtp, 0, 1, local_args);
|
rcode = do_bootm (cmdtp, 0, 1, local_args);
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_AUTOSCRIPT
|
#ifdef CONFIG_AUTOSCRIPT
|
||||||
if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) {
|
if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) {
|
||||||
printf("Running autoscript at addr 0x%08lX ...\n", load_addr);
|
printf("Running autoscript at addr 0x%08lX ...\n", load_addr);
|
||||||
|
SHOW_BOOT_PROGRESS(83);
|
||||||
rcode = autoscript (load_addr);
|
rcode = autoscript (load_addr);
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
|
||||||
|
if (rcode < 0)
|
||||||
|
SHOW_BOOT_PROGRESS(-83);
|
||||||
|
else
|
||||||
|
SHOW_BOOT_PROGRESS(84);
|
||||||
#endif
|
#endif
|
||||||
return rcode;
|
return rcode;
|
||||||
}
|
}
|
||||||
|
|
|
@ -90,7 +90,7 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!reiserfs_mount(part_length)) {
|
if (!reiserfs_mount(part_length)) {
|
||||||
printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part);
|
printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -183,7 +183,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
|
if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
|
||||||
printf ("\n** Invalid partition type \"%.32s\""
|
printf ("\n** Invalid partition type \"%.32s\""
|
||||||
" (expect \"" BOOT_PART_TYPE "\")\n",
|
" (expect \"" BOOT_PART_TYPE "\")\n",
|
||||||
info.type);
|
info.type);
|
||||||
|
@ -204,7 +204,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!reiserfs_mount(part_length)) {
|
if (!reiserfs_mount(part_length)) {
|
||||||
printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part);
|
printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -232,7 +232,7 @@ void env_relocate (void)
|
||||||
puts ("Using default environment\n\n");
|
puts ("Using default environment\n\n");
|
||||||
#else
|
#else
|
||||||
puts ("*** Warning - bad CRC, using default environment\n\n");
|
puts ("*** Warning - bad CRC, using default environment\n\n");
|
||||||
SHOW_BOOT_PROGRESS (-1);
|
SHOW_BOOT_PROGRESS (-60);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
if (sizeof(default_environment) > ENV_SIZE)
|
if (sizeof(default_environment) > ENV_SIZE)
|
||||||
|
|
|
@ -70,6 +70,15 @@
|
||||||
|
|
||||||
#define ONE_BILLION 1000000000
|
#define ONE_BILLION 1000000000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
|
||||||
|
*/
|
||||||
|
void __spd_ddr_init_hang (void)
|
||||||
|
{
|
||||||
|
hang ();
|
||||||
|
}
|
||||||
|
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------
|
||||||
| Memory Controller Options 0
|
| Memory Controller Options 0
|
||||||
+-----------------------------------------------------------------------------*/
|
+-----------------------------------------------------------------------------*/
|
||||||
|
@ -467,7 +476,7 @@ static void get_spd_info(unsigned long *dimm_populated,
|
||||||
|
|
||||||
if (dimm_found == FALSE) {
|
if (dimm_found == FALSE) {
|
||||||
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
|
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -490,7 +499,7 @@ static void check_mem_type(unsigned long *dimm_populated,
|
||||||
dimm_num);
|
dimm_num);
|
||||||
printf("Only DDR SDRAM DIMMs are supported.\n");
|
printf("Only DDR SDRAM DIMMs are supported.\n");
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -510,7 +519,7 @@ static void check_volt_type(unsigned long *dimm_populated,
|
||||||
if (voltage_type != 0x04) {
|
if (voltage_type != 0x04) {
|
||||||
printf("ERROR: DIMM %lu with unsupported voltage level.\n",
|
printf("ERROR: DIMM %lu with unsupported voltage level.\n",
|
||||||
dimm_num);
|
dimm_num);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
} else {
|
} else {
|
||||||
debug("DIMM %lu voltage level supported.\n", dimm_num);
|
debug("DIMM %lu voltage level supported.\n", dimm_num);
|
||||||
}
|
}
|
||||||
|
@ -581,7 +590,7 @@ static void program_cfg0(unsigned long *dimm_populated,
|
||||||
printf("WARNING: DIMM with datawidth of %lu bits.\n",
|
printf("WARNING: DIMM with datawidth of %lu bits.\n",
|
||||||
data_width);
|
data_width);
|
||||||
printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
|
printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -769,7 +778,7 @@ static void program_tr0(unsigned long *dimm_populated,
|
||||||
if ((tcyc_reg & 0x0F) >= 10) {
|
if ((tcyc_reg & 0x0F) >= 10) {
|
||||||
printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
|
printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
|
||||||
dimm_num);
|
dimm_num);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
cycle_time_ns_x_10[cas_index] =
|
cycle_time_ns_x_10[cas_index] =
|
||||||
|
@ -849,7 +858,7 @@ static void program_tr0(unsigned long *dimm_populated,
|
||||||
printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
|
printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
|
||||||
printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
|
printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
|
||||||
printf("Make sure the PLB speed is within the supported range.\n");
|
printf("Make sure the PLB speed is within the supported range.\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1008,6 +1017,7 @@ static int short_mem_test(void)
|
||||||
*/
|
*/
|
||||||
for (i = 0; i < NUMMEMTESTS; i++) {
|
for (i = 0; i < NUMMEMTESTS; i++) {
|
||||||
for (j = 0; j < NUMMEMWORDS; j++) {
|
for (j = 0; j < NUMMEMWORDS; j++) {
|
||||||
|
//printf("bank enabled base:%x\n", &membase[j]);
|
||||||
membase[j] = test[i][j];
|
membase[j] = test[i][j];
|
||||||
ppcDcbf((unsigned long)&(membase[j]));
|
ppcDcbf((unsigned long)&(membase[j]));
|
||||||
}
|
}
|
||||||
|
@ -1160,7 +1170,7 @@ static void program_tr1(void)
|
||||||
*/
|
*/
|
||||||
if (window_found == FALSE) {
|
if (window_found == FALSE) {
|
||||||
printf("ERROR: Cannot determine a common read delay.\n");
|
printf("ERROR: Cannot determine a common read delay.\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1310,7 +1320,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
|
||||||
printf("ERROR: Unsupported value for the banksize: %d.\n",
|
printf("ERROR: Unsupported value for the banksize: %d.\n",
|
||||||
bank_size_id);
|
bank_size_id);
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
switch (num_col_addr) {
|
switch (num_col_addr) {
|
||||||
|
@ -1332,7 +1342,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
|
||||||
printf("ERROR: Unsupported value for number of "
|
printf("ERROR: Unsupported value for number of "
|
||||||
"column addresses: %d.\n", num_col_addr);
|
"column addresses: %d.\n", num_col_addr);
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -129,6 +129,16 @@
|
||||||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
|
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
|
||||||
|
*/
|
||||||
|
void __spd_ddr_init_hang (void)
|
||||||
|
{
|
||||||
|
hang ();
|
||||||
|
}
|
||||||
|
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
|
||||||
|
|
||||||
|
|
||||||
/* Private Structure Definitions */
|
/* Private Structure Definitions */
|
||||||
|
|
||||||
/* enum only to ease code for cas latency setting */
|
/* enum only to ease code for cas latency setting */
|
||||||
|
@ -582,7 +592,7 @@ static void get_spd_info(unsigned long *dimm_populated,
|
||||||
|
|
||||||
if (dimm_found == FALSE) {
|
if (dimm_found == FALSE) {
|
||||||
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
|
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -629,42 +639,42 @@ static void check_mem_type(unsigned long *dimm_populated,
|
||||||
"slot %d.\n", (unsigned int)dimm_num);
|
"slot %d.\n", (unsigned int)dimm_num);
|
||||||
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
printf("ERROR: EDO DIMM detected in slot %d.\n",
|
printf("ERROR: EDO DIMM detected in slot %d.\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3:
|
||||||
printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
|
printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 4:
|
case 4:
|
||||||
printf("ERROR: SDRAM DIMM detected in slot %d.\n",
|
printf("ERROR: SDRAM DIMM detected in slot %d.\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 5:
|
case 5:
|
||||||
printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
|
printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 6:
|
case 6:
|
||||||
printf("ERROR: SGRAM DIMM detected in slot %d.\n",
|
printf("ERROR: SGRAM DIMM detected in slot %d.\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 7:
|
case 7:
|
||||||
debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
|
debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
|
||||||
|
@ -679,7 +689,7 @@ static void check_mem_type(unsigned long *dimm_populated,
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
|
printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -689,7 +699,7 @@ static void check_mem_type(unsigned long *dimm_populated,
|
||||||
&& (dimm_populated[dimm_num] != SDRAM_NONE)
|
&& (dimm_populated[dimm_num] != SDRAM_NONE)
|
||||||
&& (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
|
&& (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
|
||||||
printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
|
printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -764,7 +774,7 @@ static void check_frequency(unsigned long *dimm_populated,
|
||||||
(unsigned int)(calc_cycle_time*10));
|
(unsigned int)(calc_cycle_time*10));
|
||||||
printf("Replace the DIMM, or change DDR frequency via "
|
printf("Replace the DIMM, or change DDR frequency via "
|
||||||
"strapping bits.\n\n");
|
"strapping bits.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -796,7 +806,7 @@ static void check_rank_number(unsigned long *dimm_populated,
|
||||||
"slot %d is not supported.\n", dimm_rank, dimm_num);
|
"slot %d is not supported.\n", dimm_rank, dimm_num);
|
||||||
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
|
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
} else
|
} else
|
||||||
total_rank += dimm_rank;
|
total_rank += dimm_rank;
|
||||||
}
|
}
|
||||||
|
@ -805,7 +815,7 @@ static void check_rank_number(unsigned long *dimm_populated,
|
||||||
"for all slots.\n", (unsigned int)total_rank);
|
"for all slots.\n", (unsigned int)total_rank);
|
||||||
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
|
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
|
||||||
printf("Remove one of the DIMM modules.\n\n");
|
printf("Remove one of the DIMM modules.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -830,28 +840,28 @@ static void check_voltage_type(unsigned long *dimm_populated,
|
||||||
printf("This DIMM is 5.0 Volt/TTL.\n");
|
printf("This DIMM is 5.0 Volt/TTL.\n");
|
||||||
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 0x01:
|
case 0x01:
|
||||||
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
|
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
|
||||||
printf("This DIMM is LVTTL.\n");
|
printf("This DIMM is LVTTL.\n");
|
||||||
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 0x02:
|
case 0x02:
|
||||||
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
|
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
|
||||||
printf("This DIMM is 1.5 Volt.\n");
|
printf("This DIMM is 1.5 Volt.\n");
|
||||||
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 0x03:
|
case 0x03:
|
||||||
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
|
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
|
||||||
printf("This DIMM is 3.3 Volt/TTL.\n");
|
printf("This DIMM is 3.3 Volt/TTL.\n");
|
||||||
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
case 0x04:
|
case 0x04:
|
||||||
/* 2.5 Voltage only for DDR1 */
|
/* 2.5 Voltage only for DDR1 */
|
||||||
|
@ -863,7 +873,7 @@ static void check_voltage_type(unsigned long *dimm_populated,
|
||||||
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
|
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
|
||||||
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1006,13 +1016,13 @@ static void program_copt1(unsigned long *dimm_populated,
|
||||||
if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
|
if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
|
||||||
if (buf0 != buf1) {
|
if (buf0 != buf1) {
|
||||||
printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
|
printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
|
if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
|
||||||
printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
|
printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
|
else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
|
||||||
mcopt1 |= SDRAM_MCOPT1_DMWD_64;
|
mcopt1 |= SDRAM_MCOPT1_DMWD_64;
|
||||||
|
@ -1020,7 +1030,7 @@ static void program_copt1(unsigned long *dimm_populated,
|
||||||
mcopt1 |= SDRAM_MCOPT1_DMWD_32;
|
mcopt1 |= SDRAM_MCOPT1_DMWD_32;
|
||||||
} else {
|
} else {
|
||||||
printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
|
printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
if (ecc_enabled == TRUE)
|
if (ecc_enabled == TRUE)
|
||||||
|
@ -1209,7 +1219,7 @@ static void program_initplr(unsigned long *dimm_populated,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printf("ERROR: ucode error on selected_cas value %d", selected_cas);
|
printf("ERROR: ucode error on selected_cas value %d", selected_cas);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1241,7 +1251,7 @@ static void program_initplr(unsigned long *dimm_populated,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printf("ERROR: write recovery not support (%d)", write_recovery);
|
printf("ERROR: write recovery not support (%d)", write_recovery);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
@ -1259,7 +1269,7 @@ static void program_initplr(unsigned long *dimm_populated,
|
||||||
ods = ODS_REDUCED;
|
ods = ODS_REDUCED;
|
||||||
} else {
|
} else {
|
||||||
printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
|
printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
|
mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
|
||||||
|
@ -1284,7 +1294,7 @@ static void program_initplr(unsigned long *dimm_populated,
|
||||||
mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
|
mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
|
||||||
} else {
|
} else {
|
||||||
printf("ERROR: ucode error as unknown DDR type in program_initplr");
|
printf("ERROR: ucode error as unknown DDR type in program_initplr");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1389,7 +1399,7 @@ static void program_mode(unsigned long *dimm_populated,
|
||||||
} else {
|
} else {
|
||||||
printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
|
printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
|
||||||
"in slot %d\n", (unsigned int)dimm_num);
|
"in slot %d\n", (unsigned int)dimm_num);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
/* Convert from hex to decimal */
|
/* Convert from hex to decimal */
|
||||||
|
@ -1526,7 +1536,7 @@ static void program_mode(unsigned long *dimm_populated,
|
||||||
printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
|
printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
|
||||||
printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
|
printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
|
||||||
printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
|
printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
} else { /* DDR2 */
|
} else { /* DDR2 */
|
||||||
debug("cas_3_0_available=%d\n", cas_3_0_available);
|
debug("cas_3_0_available=%d\n", cas_3_0_available);
|
||||||
|
@ -1549,7 +1559,7 @@ static void program_mode(unsigned long *dimm_populated,
|
||||||
cas_3_0_available, cas_4_0_available, cas_5_0_available);
|
cas_3_0_available, cas_4_0_available, cas_5_0_available);
|
||||||
printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
|
printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
|
||||||
sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
|
sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1658,7 +1668,7 @@ static void program_rtr(unsigned long *dimm_populated,
|
||||||
printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
|
printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
|
||||||
(unsigned int)dimm_num);
|
(unsigned int)dimm_num);
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2066,7 +2076,7 @@ static void program_bxcf(unsigned long *dimm_populated,
|
||||||
printf("ERROR: Unsupported value for number of "
|
printf("ERROR: Unsupported value for number of "
|
||||||
"column addresses: %d.\n", (unsigned int)num_col_addr);
|
"column addresses: %d.\n", (unsigned int)num_col_addr);
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2148,7 +2158,7 @@ static void program_memory_queue(unsigned long *dimm_populated,
|
||||||
printf("ERROR: Unsupported value for the banksize: %d.\n",
|
printf("ERROR: Unsupported value for the banksize: %d.\n",
|
||||||
(unsigned int)rank_size_id);
|
(unsigned int)rank_size_id);
|
||||||
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
printf("Replace the DIMM module with a supported DIMM.\n\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
|
if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
|
||||||
|
@ -2693,7 +2703,7 @@ calibration_loop:
|
||||||
printf("\nERROR: Cannot determine a common read delay for the "
|
printf("\nERROR: Cannot determine a common read delay for the "
|
||||||
"DIMM(s) installed.\n");
|
"DIMM(s) installed.\n");
|
||||||
debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
|
debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
blank_string(strlen(str));
|
blank_string(strlen(str));
|
||||||
|
@ -2849,7 +2859,7 @@ static void test(void)
|
||||||
if (window_found == FALSE) {
|
if (window_found == FALSE) {
|
||||||
printf("ERROR: Cannot determine a common read delay for the "
|
printf("ERROR: Cannot determine a common read delay for the "
|
||||||
"DIMM(s) installed.\n");
|
"DIMM(s) installed.\n");
|
||||||
hang();
|
spd_ddr_init_hang ();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*------------------------------------------------------------------
|
/*------------------------------------------------------------------
|
||||||
|
|
|
@ -1217,15 +1217,23 @@ mck_return:
|
||||||
* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
|
* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
|
||||||
* although for some cache-ralated calls stubs have to be provided to satisfy
|
* although for some cache-ralated calls stubs have to be provided to satisfy
|
||||||
* symbols resolution.
|
* symbols resolution.
|
||||||
|
* Icache-related functions are used in POST framework.
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_440
|
#ifdef CONFIG_440
|
||||||
.globl dcache_disable
|
.globl dcache_disable
|
||||||
|
.globl icache_disable
|
||||||
|
.globl icache_enable
|
||||||
dcache_disable:
|
dcache_disable:
|
||||||
|
icache_disable:
|
||||||
|
icache_enable:
|
||||||
blr
|
blr
|
||||||
|
|
||||||
.globl dcache_status
|
.globl dcache_status
|
||||||
|
.globl icache_status
|
||||||
dcache_status:
|
dcache_status:
|
||||||
|
icache_status:
|
||||||
|
mr r3, 0
|
||||||
blr
|
blr
|
||||||
#else
|
#else
|
||||||
flush_dcache:
|
flush_dcache:
|
||||||
|
|
|
@ -180,7 +180,6 @@ void dev_print (block_dev_desc_t *dev_desc)
|
||||||
defined(CONFIG_CMD_SCSI) || \
|
defined(CONFIG_CMD_SCSI) || \
|
||||||
defined(CONFIG_CMD_USB) || \
|
defined(CONFIG_CMD_USB) || \
|
||||||
defined(CONFIG_MMC) || \
|
defined(CONFIG_MMC) || \
|
||||||
(defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
|
|
||||||
defined(CONFIG_SYSTEMACE) )
|
defined(CONFIG_SYSTEMACE) )
|
||||||
|
|
||||||
#if defined(CONFIG_MAC_PARTITION) || \
|
#if defined(CONFIG_MAC_PARTITION) || \
|
||||||
|
@ -223,7 +222,7 @@ void init_part (block_dev_desc_t * dev_desc)
|
||||||
int get_partition_info (block_dev_desc_t *dev_desc, int part
|
int get_partition_info (block_dev_desc_t *dev_desc, int part
|
||||||
, disk_partition_t *info)
|
, disk_partition_t *info)
|
||||||
{
|
{
|
||||||
switch (dev_desc->part_type) {
|
switch (dev_desc->part_type) {
|
||||||
#ifdef CONFIG_MAC_PARTITION
|
#ifdef CONFIG_MAC_PARTITION
|
||||||
case PART_TYPE_MAC:
|
case PART_TYPE_MAC:
|
||||||
if (get_partition_info_mac(dev_desc,part,info) == 0) {
|
if (get_partition_info_mac(dev_desc,part,info) == 0) {
|
||||||
|
|
|
@ -898,6 +898,39 @@ static void tsec_halt(struct eth_device *dev)
|
||||||
phy_run_commands(priv, priv->phyinfo->shutdown);
|
phy_run_commands(priv, priv->phyinfo->shutdown);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
struct phy_info phy_info_M88E1149S = {
|
||||||
|
0x1410ca,
|
||||||
|
"Marvell 88E1149S",
|
||||||
|
4,
|
||||||
|
(struct phy_cmd[]){ /* config */
|
||||||
|
/* Reset and configure the PHY */
|
||||||
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
||||||
|
{0x1d, 0x1f, NULL},
|
||||||
|
{0x1e, 0x200c, NULL},
|
||||||
|
{0x1d, 0x5, NULL},
|
||||||
|
{0x1e, 0x0, NULL},
|
||||||
|
{0x1e, 0x100, NULL},
|
||||||
|
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
||||||
|
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
||||||
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
||||||
|
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
|
||||||
|
{miim_end,}
|
||||||
|
},
|
||||||
|
(struct phy_cmd[]){ /* startup */
|
||||||
|
/* Status is read once to clear old link state */
|
||||||
|
{MIIM_STATUS, miim_read, NULL},
|
||||||
|
/* Auto-negotiate */
|
||||||
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
||||||
|
/* Read the status */
|
||||||
|
{MIIM_88E1011_PHY_STATUS, miim_read,
|
||||||
|
&mii_parse_88E1011_psr},
|
||||||
|
{miim_end,}
|
||||||
|
},
|
||||||
|
(struct phy_cmd[]){ /* shutdown */
|
||||||
|
{miim_end,}
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
|
/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
|
||||||
struct phy_info phy_info_BCM5461S = {
|
struct phy_info phy_info_BCM5461S = {
|
||||||
0x02060c1, /* 5461 ID */
|
0x02060c1, /* 5461 ID */
|
||||||
|
@ -993,11 +1026,6 @@ struct phy_info phy_info_M88E1111S = {
|
||||||
(struct phy_cmd[]){ /* config */
|
(struct phy_cmd[]){ /* config */
|
||||||
/* Reset and configure the PHY */
|
/* Reset and configure the PHY */
|
||||||
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
||||||
{0x1d, 0x1f, NULL},
|
|
||||||
{0x1e, 0x200c, NULL},
|
|
||||||
{0x1d, 0x5, NULL},
|
|
||||||
{0x1e, 0x0, NULL},
|
|
||||||
{0x1e, 0x100, NULL},
|
|
||||||
{0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
|
{0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
|
||||||
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
||||||
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
||||||
|
@ -1037,14 +1065,16 @@ static struct phy_info phy_info_M88E1145 = {
|
||||||
"Marvell 88E1145",
|
"Marvell 88E1145",
|
||||||
4,
|
4,
|
||||||
(struct phy_cmd[]){ /* config */
|
(struct phy_cmd[]){ /* config */
|
||||||
|
/* Reset the PHY */
|
||||||
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
||||||
|
|
||||||
/* Errata E0, E1 */
|
/* Errata E0, E1 */
|
||||||
{29, 0x001b, NULL},
|
{29, 0x001b, NULL},
|
||||||
{30, 0x418f, NULL},
|
{30, 0x418f, NULL},
|
||||||
{29, 0x0016, NULL},
|
{29, 0x0016, NULL},
|
||||||
{30, 0xa2da, NULL},
|
{30, 0xa2da, NULL},
|
||||||
|
|
||||||
/* Reset and configure the PHY */
|
/* Configure the PHY */
|
||||||
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
|
||||||
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
||||||
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
||||||
{MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
|
{MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
|
||||||
|
@ -1321,6 +1351,7 @@ struct phy_info *phy_info[] = {
|
||||||
&phy_info_M88E1011S,
|
&phy_info_M88E1011S,
|
||||||
&phy_info_M88E1111S,
|
&phy_info_M88E1111S,
|
||||||
&phy_info_M88E1145,
|
&phy_info_M88E1145,
|
||||||
|
&phy_info_M88E1149S,
|
||||||
&phy_info_dm9161,
|
&phy_info_dm9161,
|
||||||
&phy_info_lxt971,
|
&phy_info_lxt971,
|
||||||
&phy_info_VSC8244,
|
&phy_info_VSC8244,
|
||||||
|
@ -1351,8 +1382,10 @@ struct phy_info *get_phy_info(struct eth_device *dev)
|
||||||
/* loop through all the known PHY types, and find one that */
|
/* loop through all the known PHY types, and find one that */
|
||||||
/* matches the ID we read from the PHY. */
|
/* matches the ID we read from the PHY. */
|
||||||
for (i = 0; phy_info[i]; i++) {
|
for (i = 0; phy_info[i]; i++) {
|
||||||
if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
|
if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
|
||||||
theInfo = phy_info[i];
|
theInfo = phy_info[i];
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (theInfo == NULL) {
|
if (theInfo == NULL) {
|
||||||
|
|
34
fs/fat/fat.c
34
fs/fat/fat.c
|
@ -70,10 +70,11 @@ int
|
||||||
fat_register_device(block_dev_desc_t *dev_desc, int part_no)
|
fat_register_device(block_dev_desc_t *dev_desc, int part_no)
|
||||||
{
|
{
|
||||||
unsigned char buffer[SECTOR_SIZE];
|
unsigned char buffer[SECTOR_SIZE];
|
||||||
|
disk_partition_t info;
|
||||||
|
|
||||||
if (!dev_desc->block_read)
|
if (!dev_desc->block_read)
|
||||||
return -1;
|
return -1;
|
||||||
cur_dev=dev_desc;
|
cur_dev = dev_desc;
|
||||||
/* check if we have a MBR (on floppies we have only a PBR) */
|
/* check if we have a MBR (on floppies we have only a PBR) */
|
||||||
if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) {
|
if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) {
|
||||||
printf ("** Can't read from device %d **\n", dev_desc->dev);
|
printf ("** Can't read from device %d **\n", dev_desc->dev);
|
||||||
|
@ -95,25 +96,34 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no)
|
||||||
defined(CONFIG_CMD_USB) || \
|
defined(CONFIG_CMD_USB) || \
|
||||||
(defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
|
(defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
|
||||||
defined(CONFIG_SYSTEMACE) )
|
defined(CONFIG_SYSTEMACE) )
|
||||||
disk_partition_t info;
|
/* First we assume, there is a MBR */
|
||||||
if(!get_partition_info(dev_desc, part_no, &info)) {
|
if (!get_partition_info (dev_desc, part_no, &info)) {
|
||||||
part_offset = info.start;
|
part_offset = info.start;
|
||||||
cur_part = part_no;
|
cur_part = part_no;
|
||||||
}
|
} else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) {
|
||||||
else {
|
/* ok, we assume we are on a PBR only */
|
||||||
printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev);
|
cur_part = 1;
|
||||||
return -1;
|
part_offset = 0;
|
||||||
}
|
} else {
|
||||||
|
printf ("** Partition %d not valid on device %d **\n", part_no, dev_desc->dev);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
#else
|
#else
|
||||||
|
if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
|
||||||
|
/* ok, we assume we are on a PBR only */
|
||||||
|
cur_part = 1;
|
||||||
|
part_offset = 0;
|
||||||
|
info.start = part_offset;
|
||||||
|
} else {
|
||||||
/* FIXME we need to determine the start block of the
|
/* FIXME we need to determine the start block of the
|
||||||
* partition where the DOS FS resides. This can be done
|
* partition where the DOS FS resides. This can be done
|
||||||
* by using the get_partition_info routine. For this
|
* by using the get_partition_info routine. For this
|
||||||
* purpose the libpart must be included.
|
* purpose the libpart must be included.
|
||||||
*/
|
*/
|
||||||
part_offset=32;
|
part_offset = 32;
|
||||||
cur_part = 1;
|
cur_part = 1;
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1548,7 +1548,9 @@ typedef struct ccsr_gur {
|
||||||
char res9[12];
|
char res9[12];
|
||||||
uint pvr; /* 0xe00a0 - Processor version register */
|
uint pvr; /* 0xe00a0 - Processor version register */
|
||||||
uint svr; /* 0xe00a4 - System version register */
|
uint svr; /* 0xe00a4 - System version register */
|
||||||
char res10[3416];
|
char res10a[8];
|
||||||
|
uint rstcr; /* 0xe00b0 - Reset control register */
|
||||||
|
char res10b[3404];
|
||||||
uint clkocr; /* 0xe0e00 - Clock out select register */
|
uint clkocr; /* 0xe0e00 - Clock out select register */
|
||||||
char res11[12];
|
char res11[12];
|
||||||
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
|
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
|
||||||
|
|
|
@ -516,7 +516,7 @@
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
"netdev=eth0\0" \
|
"netdev=eth0\0" \
|
||||||
"consoledev=ttyS0\0" \
|
"consoledev=ttyS0\0" \
|
||||||
"ramdiskaddr=600000\0" \
|
"ramdiskaddr=1000000\0" \
|
||||||
"ramdiskfile=your.ramdisk.u-boot\0" \
|
"ramdiskfile=your.ramdisk.u-boot\0" \
|
||||||
"fdtaddr=400000\0" \
|
"fdtaddr=400000\0" \
|
||||||
"fdtfile=your.fdt.dtb\0"
|
"fdtfile=your.fdt.dtb\0"
|
||||||
|
@ -536,7 +536,7 @@
|
||||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||||
"tftp $loadaddr $bootfile;" \
|
"tftp $loadaddr $bootfile;" \
|
||||||
"tftp $fdtaddr $fdtfile;" \
|
"tftp $fdtaddr $fdtfile;" \
|
||||||
"bootm $loadaddr $ramdiskaddr"
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
||||||
|
|
||||||
|
|
|
@ -43,9 +43,7 @@
|
||||||
|
|
||||||
#define CONFIG_PCI
|
#define CONFIG_PCI
|
||||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||||
#undef CONFIG_TSEC_ENET /* tsec ethernet support */
|
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
|
||||||
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
|
|
||||||
#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
|
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
|
||||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */
|
#define CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||||
|
@ -349,13 +347,15 @@
|
||||||
#endif /* CONFIG_PCI */
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET)
|
#ifdef CONFIG_TSEC_ENET
|
||||||
|
|
||||||
#ifndef CONFIG_NET_MULTI
|
#ifndef CONFIG_NET_MULTI
|
||||||
#define CONFIG_NET_MULTI 1
|
#define CONFIG_NET_MULTI 1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_MII
|
||||||
#define CONFIG_MII 1 /* MII PHY management */
|
#define CONFIG_MII 1 /* MII PHY management */
|
||||||
|
#endif
|
||||||
#define CONFIG_TSEC1 1
|
#define CONFIG_TSEC1 1
|
||||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||||
#define CONFIG_TSEC2 1
|
#define CONFIG_TSEC2 1
|
||||||
|
@ -369,9 +369,10 @@
|
||||||
/* Options are: TSEC[0-1] */
|
/* Options are: TSEC[0-1] */
|
||||||
#define CONFIG_ETHPRIME "TSEC0"
|
#define CONFIG_ETHPRIME "TSEC0"
|
||||||
|
|
||||||
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
|
#endif /* CONFIG_TSEC_ENET */
|
||||||
|
|
||||||
|
#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
|
||||||
|
|
||||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
|
||||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
|
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
|
||||||
|
|
||||||
|
@ -392,7 +393,10 @@
|
||||||
#define FETH3_RST 0x80
|
#define FETH3_RST 0x80
|
||||||
#endif /* CONFIG_ETHER_INDEX */
|
#endif /* CONFIG_ETHER_INDEX */
|
||||||
|
|
||||||
#define CONFIG_MII /* MII PHY management */
|
#ifndef CONFIG_MII
|
||||||
|
#define CONFIG_MII 1 /* MII PHY management */
|
||||||
|
#endif
|
||||||
|
|
||||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
|
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -543,9 +547,11 @@
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
"netdev=eth0\0" \
|
"netdev=eth0\0" \
|
||||||
"consoledev=ttyS0\0" \
|
"consoledev=ttyCPM\0" \
|
||||||
"ramdiskaddr=400000\0" \
|
"ramdiskaddr=1000000\0" \
|
||||||
"ramdiskfile=your.ramdisk.u-boot\0"
|
"ramdiskfile=your.ramdisk.u-boot\0" \
|
||||||
|
"fdtaddr=400000\0" \
|
||||||
|
"fdtfile=mpc8560ads.dtb\0"
|
||||||
|
|
||||||
#define CONFIG_NFSBOOTCOMMAND \
|
#define CONFIG_NFSBOOTCOMMAND \
|
||||||
"setenv bootargs root=/dev/nfs rw " \
|
"setenv bootargs root=/dev/nfs rw " \
|
||||||
|
@ -553,14 +559,16 @@
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
"console=$consoledev,$baudrate $othbootargs;" \
|
||||||
"tftp $loadaddr $bootfile;" \
|
"tftp $loadaddr $bootfile;" \
|
||||||
"bootm $loadaddr"
|
"tftp $fdtaddr $fdtfile;" \
|
||||||
|
"bootm $loadaddr - $fdtaddr"
|
||||||
|
|
||||||
#define CONFIG_RAMBOOTCOMMAND \
|
#define CONFIG_RAMBOOTCOMMAND \
|
||||||
"setenv bootargs root=/dev/ram rw " \
|
"setenv bootargs root=/dev/ram rw " \
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
"console=$consoledev,$baudrate $othbootargs;" \
|
||||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||||
"tftp $loadaddr $bootfile;" \
|
"tftp $loadaddr $bootfile;" \
|
||||||
"bootm $loadaddr $ramdiskaddr"
|
"tftp $fdtaddr $fdtfile;" \
|
||||||
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
||||||
|
|
||||||
|
|
|
@ -338,13 +338,25 @@
|
||||||
|
|
||||||
#define CFG_EBC_CFG 0xb8400000
|
#define CFG_EBC_CFG 0xb8400000
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Graphics (Fujitsu Lime)
|
||||||
|
*----------------------------------------------------------------------*/
|
||||||
|
/* SDRAM Clock frequency adjustment register */
|
||||||
|
#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
|
||||||
|
/* Lime Clock frequency is to set 133MHz */
|
||||||
|
#define CFG_LIME_CLOCK_133MHZ 0x10000
|
||||||
|
|
||||||
|
/* SDRAM Parameter register */
|
||||||
|
#define CFG_LIME_MMR 0xC1FCFFFC
|
||||||
|
/* SDRAM parameter value */
|
||||||
|
#define CFG_LIME_MMR_VALUE 0x414FB7F2
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* GPIO Setup
|
* GPIO Setup
|
||||||
*----------------------------------------------------------------------*/
|
*----------------------------------------------------------------------*/
|
||||||
#define CFG_GPIO_PHY1_RST 12
|
#define CFG_GPIO_PHY1_RST 12
|
||||||
#define CFG_GPIO_FLASH_WP 14
|
#define CFG_GPIO_FLASH_WP 14
|
||||||
#define CFG_GPIO_PHY0_RST 22
|
#define CFG_GPIO_PHY0_RST 22
|
||||||
#define CFG_GPIO_HUB_RST 50
|
|
||||||
#define CFG_GPIO_WATCHDOG 58
|
#define CFG_GPIO_WATCHDOG 58
|
||||||
#define CFG_GPIO_LIME_S 59
|
#define CFG_GPIO_LIME_S 59
|
||||||
#define CFG_GPIO_LIME_RST 60
|
#define CFG_GPIO_LIME_RST 60
|
||||||
|
@ -408,7 +420,7 @@
|
||||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
|
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
|
||||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
|
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
|
||||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
|
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
|
||||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
|
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
|
||||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
|
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
|
||||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
|
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
|
||||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
|
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
|
||||||
|
|
|
@ -106,19 +106,26 @@
|
||||||
#ifdef CFG_ENV_IS_IN_FLASH
|
#ifdef CFG_ENV_IS_IN_FLASH
|
||||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||||
|
|
||||||
|
#define CONFIG_ENV_OVERWRITE 1
|
||||||
|
|
||||||
/* Address and size of Redundant Environment Sector */
|
/* Address and size of Redundant Environment Sector */
|
||||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||||
#endif /* CFG_ENV_IS_IN_FLASH */
|
#endif /* CFG_ENV_IS_IN_FLASH */
|
||||||
|
|
||||||
|
#define ENV_NAME_REVLEV "revision_level"
|
||||||
|
#define ENV_NAME_SOLDER "solder_switch"
|
||||||
|
#define ENV_NAME_DIP "dip"
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* DDR SDRAM
|
* DDR SDRAM
|
||||||
*----------------------------------------------------------------------*/
|
*----------------------------------------------------------------------*/
|
||||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
|
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
|
||||||
#undef CONFIG_DDR_ECC /* don't use ECC */
|
#undef CONFIG_DDR_ECC /* don't use ECC */
|
||||||
#define SPD_EEPROM_ADDRESS {0x50}
|
#define SPD_EEPROM_ADDRESS {0x50}
|
||||||
|
#define CONFIG_PROG_SDRAM_TLB 1
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* I2C
|
* I2C
|
||||||
|
@ -143,6 +150,8 @@
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
"netdev=eth0\0" \
|
"netdev=eth0\0" \
|
||||||
"hostname=pcs440ep\0" \
|
"hostname=pcs440ep\0" \
|
||||||
|
"use_eeprom_ethaddr=default\0" \
|
||||||
|
"cs_test=off\0" \
|
||||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||||
"nfsroot=${serverip}:${rootpath}\0" \
|
"nfsroot=${serverip}:${rootpath}\0" \
|
||||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||||
|
@ -173,6 +182,36 @@
|
||||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_PREBOOT "echo;" \
|
||||||
|
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||||
|
"echo"
|
||||||
|
|
||||||
|
/* check U-Boot image with SHA1 sum */
|
||||||
|
#define CONFIG_SHA1_CHECK_UB_IMG 1
|
||||||
|
#define CONFIG_SHA1_START CFG_MONITOR_BASE
|
||||||
|
#define CONFIG_SHA1_LEN CFG_MONITOR_LEN
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Definitions for status LED
|
||||||
|
*/
|
||||||
|
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||||
|
#define CONFIG_BOARD_SPECIFIC_LED 1
|
||||||
|
|
||||||
|
#define STATUS_LED_BIT 0x08 /* LED 1 is on GPIO_PPC_1 */
|
||||||
|
#define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
|
||||||
|
#define STATUS_LED_STATE STATUS_LED_OFF
|
||||||
|
#define STATUS_LED_BIT1 0x04 /* LED 2 is on GPIO_PPC_2 */
|
||||||
|
#define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
|
||||||
|
#define STATUS_LED_STATE1 STATUS_LED_ON
|
||||||
|
#define STATUS_LED_BIT2 0x02 /* LED 3 is on GPIO_PPC_3 */
|
||||||
|
#define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
|
||||||
|
#define STATUS_LED_STATE2 STATUS_LED_OFF
|
||||||
|
#define STATUS_LED_BIT3 0x01 /* LED 4 is on GPIO_PPC_4 */
|
||||||
|
#define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
|
||||||
|
#define STATUS_LED_STATE3 STATUS_LED_OFF
|
||||||
|
|
||||||
|
#define CONFIG_SHOW_BOOT_PROGRESS 1
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||||
|
@ -420,4 +459,39 @@
|
||||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* IDE/ATA stuff Supports IDE harddisk
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||||
|
|
||||||
|
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||||
|
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||||
|
|
||||||
|
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||||
|
#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
|
||||||
|
|
||||||
|
#define CONFIG_IDE_PREINIT 1
|
||||||
|
#define CONFIG_IDE_RESET 1
|
||||||
|
|
||||||
|
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||||
|
|
||||||
|
#define CFG_ATA_BASE_ADDR CFG_CF1
|
||||||
|
|
||||||
|
/* Offset for data I/O */
|
||||||
|
#define CFG_ATA_DATA_OFFSET 0
|
||||||
|
|
||||||
|
/* Offset for normal register accesses */
|
||||||
|
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
|
||||||
|
|
||||||
|
/* Offset for alternate registers */
|
||||||
|
#define CFG_ATA_ALT_OFFSET (0x0000)
|
||||||
|
|
||||||
|
/* These addresses need to be shifted one place to the left
|
||||||
|
* ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
|
||||||
|
* These values are shifted
|
||||||
|
*/
|
||||||
|
#define CFG_ATA_PORT_ADDR(port) ((port) << 1)
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
#endif /* __CONFIG_H */
|
||||||
|
|
|
@ -349,10 +349,14 @@
|
||||||
CFG_POST_CPU | \
|
CFG_POST_CPU | \
|
||||||
CFG_POST_UART | \
|
CFG_POST_UART | \
|
||||||
CFG_POST_I2C | \
|
CFG_POST_I2C | \
|
||||||
|
CFG_POST_CACHE | \
|
||||||
|
CFG_POST_FPU | \
|
||||||
|
CFG_POST_ETHER | \
|
||||||
CFG_POST_SPR)
|
CFG_POST_SPR)
|
||||||
|
|
||||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
|
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
|
||||||
#define CONFIG_LOGBUFFER
|
#define CONFIG_LOGBUFFER
|
||||||
|
#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
|
||||||
|
|
||||||
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
||||||
|
|
||||||
|
|
|
@ -42,20 +42,20 @@
|
||||||
#define CONFIG_CPM2 1 /* has CPM2 */
|
#define CONFIG_CPM2 1 /* has CPM2 */
|
||||||
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
|
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
|
||||||
|
|
||||||
#undef CONFIG_PCI /* pci ethernet support */
|
#define CONFIG_PCI /* PCI ethernet support */
|
||||||
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
|
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
|
||||||
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
|
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||||
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
|
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
|
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
|
||||||
|
|
||||||
|
|
||||||
/* sysclk for MPC85xx
|
/* sysclk for MPC85xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
|
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
|
||||||
|
|
||||||
/* Blinkin' LEDs for Robert :-)
|
/* Blinkin' LEDs for Robert :-)
|
||||||
*/
|
*/
|
||||||
|
@ -64,23 +64,23 @@
|
||||||
/*
|
/*
|
||||||
* These can be toggled for performance analysis, otherwise use default.
|
* These can be toggled for performance analysis, otherwise use default.
|
||||||
*/
|
*/
|
||||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||||
#define CONFIG_BTB /* toggle branch predition */
|
#define CONFIG_BTB /* toggle branch predition */
|
||||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||||
|
|
||||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||||
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
|
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
|
||||||
#define CFG_MEMTEST_END 0x00400000
|
#define CFG_MEMTEST_END 0x00400000
|
||||||
|
|
||||||
|
|
||||||
/* Localbus connector. There are many options that can be
|
/* Localbus connector. There are many options that can be
|
||||||
* connected here, including sdram or lots of flash.
|
* connected here, including sdram or lots of flash.
|
||||||
* This address, however, is used to configure a 256M local bus
|
* This address, however, is used to configure a 256M local bus
|
||||||
* window that includes the Config latch below.
|
* window that includes the Config latch below.
|
||||||
*/
|
*/
|
||||||
#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
|
#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
|
||||||
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
|
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
|
||||||
|
|
||||||
/* There are various flash options used, we configure for the largest,
|
/* There are various flash options used, we configure for the largest,
|
||||||
|
@ -88,16 +88,16 @@
|
||||||
* sizes.
|
* sizes.
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_STXSSA_4M
|
#ifdef CONFIG_STXSSA_4M
|
||||||
#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
|
#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
|
||||||
#else
|
#else
|
||||||
#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
|
#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
|
||||||
#endif
|
#endif
|
||||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
|
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
|
||||||
#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
|
#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
|
||||||
|
|
||||||
#define CFG_FLASH_CFI 1
|
#define CFG_FLASH_CFI 1
|
||||||
#define CFG_FLASH_CFI_DRIVER 1
|
#define CFG_FLASH_CFI_DRIVER 1
|
||||||
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
|
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
|
||||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||||
|
|
||||||
|
@ -110,22 +110,22 @@
|
||||||
*/
|
*/
|
||||||
#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
|
#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
|
||||||
#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
|
#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
|
||||||
#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
|
#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
|
||||||
|
|
||||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||||
|
|
||||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||||
#define CFG_RAMBOOT
|
#define CFG_RAMBOOT
|
||||||
#else
|
#else
|
||||||
#undef CFG_RAMBOOT
|
#undef CFG_RAMBOOT
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CFG_RAMBOOT
|
#ifdef CFG_RAMBOOT
|
||||||
#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
|
#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
|
||||||
#else
|
#else
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#endif
|
#endif
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
|
|
||||||
|
@ -140,14 +140,14 @@
|
||||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
|
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
|
||||||
|
|
||||||
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
|
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
|
||||||
|
|
||||||
#undef CONFIG_CLOCKS_IN_MHZ
|
#undef CONFIG_CLOCKS_IN_MHZ
|
||||||
|
|
||||||
/* local bus definitions */
|
/* local bus definitions */
|
||||||
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
|
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
|
||||||
#define CFG_OR2_PRELIM 0xfc006901
|
#define CFG_OR2_PRELIM 0xfc006901
|
||||||
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
|
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
|
||||||
#define CFG_LBC_LBCR 0x00000000
|
#define CFG_LBC_LBCR 0x00000000
|
||||||
#define CFG_LBC_LSRT 0x20000000
|
#define CFG_LBC_LSRT 0x20000000
|
||||||
#define CFG_LBC_MRTPR 0x20000000
|
#define CFG_LBC_MRTPR 0x20000000
|
||||||
|
@ -158,52 +158,52 @@
|
||||||
#define CFG_LBC_LSDMR_5 0x4061b723
|
#define CFG_LBC_LSDMR_5 0x4061b723
|
||||||
|
|
||||||
#define CONFIG_L1_INIT_RAM
|
#define CONFIG_L1_INIT_RAM
|
||||||
#define CFG_INIT_RAM_LOCK 1
|
#define CFG_INIT_RAM_LOCK 1
|
||||||
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
|
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
|
||||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
|
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
|
||||||
|
|
||||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||||
|
|
||||||
/* Serial Port */
|
/* Serial Port */
|
||||||
#define CONFIG_CONS_INDEX 2
|
#define CONFIG_CONS_INDEX 2
|
||||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||||
#define CFG_NS16550
|
#define CFG_NS16550
|
||||||
#define CFG_NS16550_SERIAL
|
#define CFG_NS16550_SERIAL
|
||||||
#define CFG_NS16550_REG_SIZE 1
|
#define CFG_NS16550_REG_SIZE 1
|
||||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||||
|
|
||||||
#define CFG_BAUDRATE_TABLE \
|
#define CFG_BAUDRATE_TABLE \
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||||
|
|
||||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
|
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
|
||||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
|
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||||
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
|
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
|
||||||
#ifdef CFG_HUSH_PARSER
|
#ifdef CFG_HUSH_PARSER
|
||||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* I2C */
|
/* I2C */
|
||||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||||
#define CFG_I2C_SLAVE 0x7F
|
#define CFG_I2C_SLAVE 0x7F
|
||||||
#if 0
|
#if 0
|
||||||
#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
|
#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
|
||||||
#else
|
#else
|
||||||
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
|
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
|
||||||
#undef CFG_I2C_NOPROBES
|
#undef CFG_I2C_NOPROBES
|
||||||
#endif
|
#endif
|
||||||
#define CFG_I2C_OFFSET 0x3000
|
#define CFG_I2C_OFFSET 0x3000
|
||||||
|
|
||||||
/* I2C EEPROM. AT24C32, we keep our environment in here.
|
/* I2C EEPROM. AT24C32, we keep our environment in here.
|
||||||
*/
|
*/
|
||||||
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
|
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
|
||||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||||
|
@ -232,26 +232,26 @@
|
||||||
#if defined(CONFIG_PCI) /* PCI Ethernet card */
|
#if defined(CONFIG_PCI) /* PCI Ethernet card */
|
||||||
|
|
||||||
#define CONFIG_NET_MULTI
|
#define CONFIG_NET_MULTI
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||||
|
|
||||||
#undef CONFIG_EEPRO100
|
#define CONFIG_EEPRO100
|
||||||
#undef CONFIG_TULIP
|
#define CONFIG_TULIP
|
||||||
|
|
||||||
#if !defined(CONFIG_PCI_PNP)
|
#if !defined(CONFIG_PCI_PNP)
|
||||||
#define PCI_ENET0_IOADDR 0xe0000000
|
#define PCI_ENET0_IOADDR 0xe0000000
|
||||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#undef CONFIG_PCI_SCAN_SHOW
|
#define CONFIG_PCI_SCAN_SHOW
|
||||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET)
|
#if defined(CONFIG_TSEC_ENET)
|
||||||
|
|
||||||
#ifndef CONFIG_NET_MULTI
|
#ifndef CONFIG_NET_MULTI
|
||||||
#define CONFIG_NET_MULTI 1
|
#define CONFIG_NET_MULTI 1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_MII 1 /* MII PHY management */
|
#define CONFIG_MII 1 /* MII PHY management */
|
||||||
|
@ -260,7 +260,7 @@
|
||||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||||
#define CONFIG_TSEC2 1
|
#define CONFIG_TSEC2 1
|
||||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
#define CONFIG_TSEC2_NAME "TSEC1"
|
||||||
#undef CONFIG_MPS85XX_FEC
|
#define CONFIG_MPS85XX_FEC
|
||||||
|
|
||||||
#define TSEC1_PHY_ADDR 2
|
#define TSEC1_PHY_ADDR 2
|
||||||
#define TSEC2_PHY_ADDR 4
|
#define TSEC2_PHY_ADDR 4
|
||||||
|
@ -270,9 +270,9 @@
|
||||||
|
|
||||||
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
|
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
|
||||||
|
|
||||||
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
|
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
|
||||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
|
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
|
||||||
|
|
||||||
#if (CONFIG_ETHER_INDEX == 2)
|
#if (CONFIG_ETHER_INDEX == 2)
|
||||||
/*
|
/*
|
||||||
|
@ -281,19 +281,19 @@
|
||||||
* - Select bus for bd/buffers
|
* - Select bus for bd/buffers
|
||||||
* - Full duplex
|
* - Full duplex
|
||||||
*/
|
*/
|
||||||
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||||
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||||
#define CFG_CPMFCR_RAMTYPE 0
|
#define CFG_CPMFCR_RAMTYPE 0
|
||||||
#if 0
|
#if 0
|
||||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE)
|
#define CFG_FCC_PSMR (FCC_PSMR_FDE)
|
||||||
#else
|
#else
|
||||||
#define CFG_FCC_PSMR 0
|
#define CFG_FCC_PSMR 0
|
||||||
#endif
|
#endif
|
||||||
#define FETH2_RST 0x01
|
#define FETH2_RST 0x01
|
||||||
#elif (CONFIG_ETHER_INDEX == 3)
|
#elif (CONFIG_ETHER_INDEX == 3)
|
||||||
/* need more definitions here for FE3 */
|
/* need more definitions here for FE3 */
|
||||||
#define FETH3_RST 0x80
|
#define FETH3_RST 0x80
|
||||||
#endif /* CONFIG_ETHER_INDEX */
|
#endif /* CONFIG_ETHER_INDEX */
|
||||||
|
|
||||||
/* MDIO is done through the TSEC0 control.
|
/* MDIO is done through the TSEC0 control.
|
||||||
*/
|
*/
|
||||||
|
@ -420,13 +420,13 @@
|
||||||
*/
|
*/
|
||||||
#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
|
#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 38400
|
#define CONFIG_BAUDRATE 38400
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
|
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
|
||||||
#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
|
#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
|
||||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
|
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
|
||||||
#define CONFIG_SERVERIP 192.168.85.1
|
#define CONFIG_SERVERIP 192.168.85.1
|
||||||
#define CONFIG_IPADDR 192.168.85.60
|
#define CONFIG_IPADDR 192.168.85.60
|
||||||
#define CONFIG_GATEWAYIP 192.168.85.1
|
#define CONFIG_GATEWAYIP 192.168.85.1
|
||||||
#define CONFIG_NETMASK 255.255.255.0
|
#define CONFIG_NETMASK 255.255.255.0
|
||||||
#define CONFIG_HOSTNAME STX_SSA
|
#define CONFIG_HOSTNAME STX_SSA
|
||||||
|
@ -436,7 +436,7 @@
|
||||||
|
|
||||||
#else /* ENV IS IN FLASH -- use a full-blown envionment */
|
#else /* ENV IS IN FLASH -- use a full-blown envionment */
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
|
#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
|
||||||
|
|
||||||
|
|
|
@ -282,7 +282,6 @@
|
||||||
#define sdr_sdstp3 0x4003
|
#define sdr_sdstp3 0x4003
|
||||||
#endif /* CONFIG_440GX */
|
#endif /* CONFIG_440GX */
|
||||||
|
|
||||||
#ifdef CONFIG_440
|
|
||||||
/*----------------------------------------------------------------------------+
|
/*----------------------------------------------------------------------------+
|
||||||
| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
|
| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
|
||||||
+----------------------------------------------------------------------------*/
|
+----------------------------------------------------------------------------*/
|
||||||
|
@ -306,7 +305,6 @@
|
||||||
#define MMUCR_IULXE 0x00400000
|
#define MMUCR_IULXE 0x00400000
|
||||||
#define MMUCR_STS 0x00100000
|
#define MMUCR_STS 0x00100000
|
||||||
#define MMUCR_STID_MASK 0x000000FF
|
#define MMUCR_STID_MASK 0x000000FF
|
||||||
#endif /* CONFIG_440 */
|
|
||||||
|
|
||||||
#ifdef CONFIG_440SPE
|
#ifdef CONFIG_440SPE
|
||||||
#undef sdr_sdstp2
|
#undef sdr_sdstp2
|
||||||
|
@ -1025,7 +1023,7 @@
|
||||||
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
|
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
|
||||||
|
|
||||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||||
#define SDR_USB2D0CR 0x0320
|
#define SDR0_USB2D0CR 0x0320
|
||||||
#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
|
#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
|
||||||
#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
|
#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
|
||||||
#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
|
#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
|
||||||
|
@ -1423,7 +1421,7 @@
|
||||||
#define uicvr uic0vr
|
#define uicvr uic0vr
|
||||||
#define uicvcr uic0vcr
|
#define uicvcr uic0vcr
|
||||||
|
|
||||||
#if defined(CONFIG_440SPE)
|
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
|
||||||
/*----------------------------------------------------------------------------+
|
/*----------------------------------------------------------------------------+
|
||||||
| Clock / Power-on-reset DCR's.
|
| Clock / Power-on-reset DCR's.
|
||||||
+----------------------------------------------------------------------------*/
|
+----------------------------------------------------------------------------*/
|
||||||
|
@ -1492,9 +1490,11 @@
|
||||||
#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
|
#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
|
||||||
|
|
||||||
#define CPR0_PERD 0xE0
|
#define CPR0_PERD 0xE0
|
||||||
|
#if !defined(CONFIG_440EPX)
|
||||||
#define CPR0_PERD_PERDV0_MASK 0x03000000
|
#define CPR0_PERD_PERDV0_MASK 0x03000000
|
||||||
#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
|
#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
|
||||||
#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
|
#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
|
||||||
|
#endif
|
||||||
|
|
||||||
#define CPR0_MALD 0x100
|
#define CPR0_MALD 0x100
|
||||||
#define CPR0_MALD_MALDV0_MASK 0x03000000
|
#define CPR0_MALD_MALDV0_MASK 0x03000000
|
||||||
|
|
|
@ -0,0 +1,115 @@
|
||||||
|
/**
|
||||||
|
* \file sha1.h
|
||||||
|
* based from http://xyssl.org/code/source/sha1/
|
||||||
|
* FIPS-180-1 compliant SHA-1 implementation
|
||||||
|
*
|
||||||
|
* Copyright (C) 2003-2006 Christophe Devine
|
||||||
|
*
|
||||||
|
* This library is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU Lesser General Public
|
||||||
|
* License, version 2.1 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||||
|
* Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public
|
||||||
|
* License along with this library; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* The SHA-1 standard was published by NIST in 1993.
|
||||||
|
*
|
||||||
|
* http://www.itl.nist.gov/fipspubs/fip180-1.htm
|
||||||
|
*/
|
||||||
|
#ifndef _SHA1_H
|
||||||
|
#define _SHA1_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define SHA1_SUM_POS -0x20
|
||||||
|
#define SHA1_SUM_LEN 20
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief SHA-1 context structure
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
unsigned long total[2]; /*!< number of bytes processed */
|
||||||
|
unsigned long state[5]; /*!< intermediate digest state */
|
||||||
|
unsigned char buffer[64]; /*!< data block being processed */
|
||||||
|
}
|
||||||
|
sha1_context;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief SHA-1 context setup
|
||||||
|
*
|
||||||
|
* \param ctx SHA-1 context to be initialized
|
||||||
|
*/
|
||||||
|
void sha1_starts( sha1_context *ctx );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief SHA-1 process buffer
|
||||||
|
*
|
||||||
|
* \param ctx SHA-1 context
|
||||||
|
* \param input buffer holding the data
|
||||||
|
* \param ilen length of the input data
|
||||||
|
*/
|
||||||
|
void sha1_update( sha1_context *ctx, unsigned char *input, int ilen );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief SHA-1 final digest
|
||||||
|
*
|
||||||
|
* \param ctx SHA-1 context
|
||||||
|
* \param output SHA-1 checksum result
|
||||||
|
*/
|
||||||
|
void sha1_finish( sha1_context *ctx, unsigned char output[20] );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief Output = SHA-1( input buffer )
|
||||||
|
*
|
||||||
|
* \param input buffer holding the data
|
||||||
|
* \param ilen length of the input data
|
||||||
|
* \param output SHA-1 checksum result
|
||||||
|
*/
|
||||||
|
void sha1_csum( unsigned char *input, int ilen,
|
||||||
|
unsigned char output[20] );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief Output = SHA-1( file contents )
|
||||||
|
*
|
||||||
|
* \param path input file name
|
||||||
|
* \param output SHA-1 checksum result
|
||||||
|
* \return 0 if successful, or 1 if fopen failed
|
||||||
|
*/
|
||||||
|
int sha1_file( char *path, unsigned char output[20] );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief Output = HMAC-SHA-1( input buffer, hmac key )
|
||||||
|
*
|
||||||
|
* \param key HMAC secret key
|
||||||
|
* \param keylen length of the HMAC key
|
||||||
|
* \param input buffer holding the data
|
||||||
|
* \param ilen length of the input data
|
||||||
|
* \param output HMAC-SHA-1 result
|
||||||
|
*/
|
||||||
|
void sha1_hmac( unsigned char *key, int keylen,
|
||||||
|
unsigned char *input, int ilen,
|
||||||
|
unsigned char output[20] );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief Checkup routine
|
||||||
|
*
|
||||||
|
* \return 0 if successful, or 1 if the test failed
|
||||||
|
*/
|
||||||
|
int sha1_self_test( void );
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* sha1.h */
|
|
@ -367,6 +367,13 @@ void status_led_set (int led, int state);
|
||||||
|
|
||||||
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||||
|
|
||||||
|
#elif defined(CONFIG_BOARD_SPECIFIC_LED)
|
||||||
|
/* led_id_t is unsigned long mask */
|
||||||
|
typedef unsigned long led_id_t;
|
||||||
|
|
||||||
|
extern void __led_toggle (led_id_t mask);
|
||||||
|
extern void __led_init (led_id_t mask, int state);
|
||||||
|
extern void __led_set (led_id_t mask, int state);
|
||||||
#else
|
#else
|
||||||
# error Status LED configuration missing
|
# error Status LED configuration missing
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -27,7 +27,7 @@ LIB = $(obj)libgeneric.a
|
||||||
|
|
||||||
COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \
|
COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \
|
||||||
bzlib_randtable.o bzlib_huffman.o \
|
bzlib_randtable.o bzlib_huffman.o \
|
||||||
crc32.o ctype.o display_options.o ldiv.o \
|
crc32.o ctype.o display_options.o ldiv.o sha1.o \
|
||||||
string.o vsprintf.o zlib.o
|
string.o vsprintf.o zlib.o
|
||||||
|
|
||||||
SRCS := $(COBJS:.o=.c)
|
SRCS := $(COBJS:.o=.c)
|
||||||
|
|
|
@ -0,0 +1,413 @@
|
||||||
|
/*
|
||||||
|
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||||
|
* based on:
|
||||||
|
* FIPS-180-1 compliant SHA-1 implementation
|
||||||
|
*
|
||||||
|
* Copyright (C) 2003-2006 Christophe Devine
|
||||||
|
*
|
||||||
|
* This library is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU Lesser General Public
|
||||||
|
* License, version 2.1 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||||
|
* Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public
|
||||||
|
* License along with this library; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* The SHA-1 standard was published by NIST in 1993.
|
||||||
|
*
|
||||||
|
* http://www.itl.nist.gov/fipspubs/fip180-1.htm
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CRT_SECURE_NO_DEPRECATE
|
||||||
|
#define _CRT_SECURE_NO_DEPRECATE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <linux/string.h>
|
||||||
|
#include "sha1.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 32-bit integer manipulation macros (big endian)
|
||||||
|
*/
|
||||||
|
#ifndef GET_UINT32_BE
|
||||||
|
#define GET_UINT32_BE(n,b,i) { \
|
||||||
|
(n) = ( (unsigned long) (b)[(i) ] << 24 ) \
|
||||||
|
| ( (unsigned long) (b)[(i) + 1] << 16 ) \
|
||||||
|
| ( (unsigned long) (b)[(i) + 2] << 8 ) \
|
||||||
|
| ( (unsigned long) (b)[(i) + 3] ); \
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#ifndef PUT_UINT32_BE
|
||||||
|
#define PUT_UINT32_BE(n,b,i) { \
|
||||||
|
(b)[(i) ] = (unsigned char) ( (n) >> 24 ); \
|
||||||
|
(b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \
|
||||||
|
(b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \
|
||||||
|
(b)[(i) + 3] = (unsigned char) ( (n) ); \
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SHA-1 context setup
|
||||||
|
*/
|
||||||
|
void sha1_starts (sha1_context * ctx)
|
||||||
|
{
|
||||||
|
ctx->total[0] = 0;
|
||||||
|
ctx->total[1] = 0;
|
||||||
|
|
||||||
|
ctx->state[0] = 0x67452301;
|
||||||
|
ctx->state[1] = 0xEFCDAB89;
|
||||||
|
ctx->state[2] = 0x98BADCFE;
|
||||||
|
ctx->state[3] = 0x10325476;
|
||||||
|
ctx->state[4] = 0xC3D2E1F0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sha1_process (sha1_context * ctx, unsigned char data[64])
|
||||||
|
{
|
||||||
|
unsigned long temp, W[16], A, B, C, D, E;
|
||||||
|
|
||||||
|
GET_UINT32_BE (W[0], data, 0);
|
||||||
|
GET_UINT32_BE (W[1], data, 4);
|
||||||
|
GET_UINT32_BE (W[2], data, 8);
|
||||||
|
GET_UINT32_BE (W[3], data, 12);
|
||||||
|
GET_UINT32_BE (W[4], data, 16);
|
||||||
|
GET_UINT32_BE (W[5], data, 20);
|
||||||
|
GET_UINT32_BE (W[6], data, 24);
|
||||||
|
GET_UINT32_BE (W[7], data, 28);
|
||||||
|
GET_UINT32_BE (W[8], data, 32);
|
||||||
|
GET_UINT32_BE (W[9], data, 36);
|
||||||
|
GET_UINT32_BE (W[10], data, 40);
|
||||||
|
GET_UINT32_BE (W[11], data, 44);
|
||||||
|
GET_UINT32_BE (W[12], data, 48);
|
||||||
|
GET_UINT32_BE (W[13], data, 52);
|
||||||
|
GET_UINT32_BE (W[14], data, 56);
|
||||||
|
GET_UINT32_BE (W[15], data, 60);
|
||||||
|
|
||||||
|
#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
|
||||||
|
|
||||||
|
#define R(t) ( \
|
||||||
|
temp = W[(t - 3) & 0x0F] ^ W[(t - 8) & 0x0F] ^ \
|
||||||
|
W[(t - 14) & 0x0F] ^ W[ t & 0x0F], \
|
||||||
|
( W[t & 0x0F] = S(temp,1) ) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define P(a,b,c,d,e,x) { \
|
||||||
|
e += S(a,5) + F(b,c,d) + K + x; b = S(b,30); \
|
||||||
|
}
|
||||||
|
|
||||||
|
A = ctx->state[0];
|
||||||
|
B = ctx->state[1];
|
||||||
|
C = ctx->state[2];
|
||||||
|
D = ctx->state[3];
|
||||||
|
E = ctx->state[4];
|
||||||
|
|
||||||
|
#define F(x,y,z) (z ^ (x & (y ^ z)))
|
||||||
|
#define K 0x5A827999
|
||||||
|
|
||||||
|
P (A, B, C, D, E, W[0]);
|
||||||
|
P (E, A, B, C, D, W[1]);
|
||||||
|
P (D, E, A, B, C, W[2]);
|
||||||
|
P (C, D, E, A, B, W[3]);
|
||||||
|
P (B, C, D, E, A, W[4]);
|
||||||
|
P (A, B, C, D, E, W[5]);
|
||||||
|
P (E, A, B, C, D, W[6]);
|
||||||
|
P (D, E, A, B, C, W[7]);
|
||||||
|
P (C, D, E, A, B, W[8]);
|
||||||
|
P (B, C, D, E, A, W[9]);
|
||||||
|
P (A, B, C, D, E, W[10]);
|
||||||
|
P (E, A, B, C, D, W[11]);
|
||||||
|
P (D, E, A, B, C, W[12]);
|
||||||
|
P (C, D, E, A, B, W[13]);
|
||||||
|
P (B, C, D, E, A, W[14]);
|
||||||
|
P (A, B, C, D, E, W[15]);
|
||||||
|
P (E, A, B, C, D, R (16));
|
||||||
|
P (D, E, A, B, C, R (17));
|
||||||
|
P (C, D, E, A, B, R (18));
|
||||||
|
P (B, C, D, E, A, R (19));
|
||||||
|
|
||||||
|
#undef K
|
||||||
|
#undef F
|
||||||
|
|
||||||
|
#define F(x,y,z) (x ^ y ^ z)
|
||||||
|
#define K 0x6ED9EBA1
|
||||||
|
|
||||||
|
P (A, B, C, D, E, R (20));
|
||||||
|
P (E, A, B, C, D, R (21));
|
||||||
|
P (D, E, A, B, C, R (22));
|
||||||
|
P (C, D, E, A, B, R (23));
|
||||||
|
P (B, C, D, E, A, R (24));
|
||||||
|
P (A, B, C, D, E, R (25));
|
||||||
|
P (E, A, B, C, D, R (26));
|
||||||
|
P (D, E, A, B, C, R (27));
|
||||||
|
P (C, D, E, A, B, R (28));
|
||||||
|
P (B, C, D, E, A, R (29));
|
||||||
|
P (A, B, C, D, E, R (30));
|
||||||
|
P (E, A, B, C, D, R (31));
|
||||||
|
P (D, E, A, B, C, R (32));
|
||||||
|
P (C, D, E, A, B, R (33));
|
||||||
|
P (B, C, D, E, A, R (34));
|
||||||
|
P (A, B, C, D, E, R (35));
|
||||||
|
P (E, A, B, C, D, R (36));
|
||||||
|
P (D, E, A, B, C, R (37));
|
||||||
|
P (C, D, E, A, B, R (38));
|
||||||
|
P (B, C, D, E, A, R (39));
|
||||||
|
|
||||||
|
#undef K
|
||||||
|
#undef F
|
||||||
|
|
||||||
|
#define F(x,y,z) ((x & y) | (z & (x | y)))
|
||||||
|
#define K 0x8F1BBCDC
|
||||||
|
|
||||||
|
P (A, B, C, D, E, R (40));
|
||||||
|
P (E, A, B, C, D, R (41));
|
||||||
|
P (D, E, A, B, C, R (42));
|
||||||
|
P (C, D, E, A, B, R (43));
|
||||||
|
P (B, C, D, E, A, R (44));
|
||||||
|
P (A, B, C, D, E, R (45));
|
||||||
|
P (E, A, B, C, D, R (46));
|
||||||
|
P (D, E, A, B, C, R (47));
|
||||||
|
P (C, D, E, A, B, R (48));
|
||||||
|
P (B, C, D, E, A, R (49));
|
||||||
|
P (A, B, C, D, E, R (50));
|
||||||
|
P (E, A, B, C, D, R (51));
|
||||||
|
P (D, E, A, B, C, R (52));
|
||||||
|
P (C, D, E, A, B, R (53));
|
||||||
|
P (B, C, D, E, A, R (54));
|
||||||
|
P (A, B, C, D, E, R (55));
|
||||||
|
P (E, A, B, C, D, R (56));
|
||||||
|
P (D, E, A, B, C, R (57));
|
||||||
|
P (C, D, E, A, B, R (58));
|
||||||
|
P (B, C, D, E, A, R (59));
|
||||||
|
|
||||||
|
#undef K
|
||||||
|
#undef F
|
||||||
|
|
||||||
|
#define F(x,y,z) (x ^ y ^ z)
|
||||||
|
#define K 0xCA62C1D6
|
||||||
|
|
||||||
|
P (A, B, C, D, E, R (60));
|
||||||
|
P (E, A, B, C, D, R (61));
|
||||||
|
P (D, E, A, B, C, R (62));
|
||||||
|
P (C, D, E, A, B, R (63));
|
||||||
|
P (B, C, D, E, A, R (64));
|
||||||
|
P (A, B, C, D, E, R (65));
|
||||||
|
P (E, A, B, C, D, R (66));
|
||||||
|
P (D, E, A, B, C, R (67));
|
||||||
|
P (C, D, E, A, B, R (68));
|
||||||
|
P (B, C, D, E, A, R (69));
|
||||||
|
P (A, B, C, D, E, R (70));
|
||||||
|
P (E, A, B, C, D, R (71));
|
||||||
|
P (D, E, A, B, C, R (72));
|
||||||
|
P (C, D, E, A, B, R (73));
|
||||||
|
P (B, C, D, E, A, R (74));
|
||||||
|
P (A, B, C, D, E, R (75));
|
||||||
|
P (E, A, B, C, D, R (76));
|
||||||
|
P (D, E, A, B, C, R (77));
|
||||||
|
P (C, D, E, A, B, R (78));
|
||||||
|
P (B, C, D, E, A, R (79));
|
||||||
|
|
||||||
|
#undef K
|
||||||
|
#undef F
|
||||||
|
|
||||||
|
ctx->state[0] += A;
|
||||||
|
ctx->state[1] += B;
|
||||||
|
ctx->state[2] += C;
|
||||||
|
ctx->state[3] += D;
|
||||||
|
ctx->state[4] += E;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SHA-1 process buffer
|
||||||
|
*/
|
||||||
|
void sha1_update (sha1_context * ctx, unsigned char *input, int ilen)
|
||||||
|
{
|
||||||
|
int fill;
|
||||||
|
unsigned long left;
|
||||||
|
|
||||||
|
if (ilen <= 0)
|
||||||
|
return;
|
||||||
|
|
||||||
|
left = ctx->total[0] & 0x3F;
|
||||||
|
fill = 64 - left;
|
||||||
|
|
||||||
|
ctx->total[0] += ilen;
|
||||||
|
ctx->total[0] &= 0xFFFFFFFF;
|
||||||
|
|
||||||
|
if (ctx->total[0] < (unsigned long) ilen)
|
||||||
|
ctx->total[1]++;
|
||||||
|
|
||||||
|
if (left && ilen >= fill) {
|
||||||
|
memcpy ((void *) (ctx->buffer + left), (void *) input, fill);
|
||||||
|
sha1_process (ctx, ctx->buffer);
|
||||||
|
input += fill;
|
||||||
|
ilen -= fill;
|
||||||
|
left = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
while (ilen >= 64) {
|
||||||
|
sha1_process (ctx, input);
|
||||||
|
input += 64;
|
||||||
|
ilen -= 64;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ilen > 0) {
|
||||||
|
memcpy ((void *) (ctx->buffer + left), (void *) input, ilen);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static const unsigned char sha1_padding[64] = {
|
||||||
|
0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||||
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||||
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||||
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SHA-1 final digest
|
||||||
|
*/
|
||||||
|
void sha1_finish (sha1_context * ctx, unsigned char output[20])
|
||||||
|
{
|
||||||
|
unsigned long last, padn;
|
||||||
|
unsigned long high, low;
|
||||||
|
unsigned char msglen[8];
|
||||||
|
|
||||||
|
high = (ctx->total[0] >> 29)
|
||||||
|
| (ctx->total[1] << 3);
|
||||||
|
low = (ctx->total[0] << 3);
|
||||||
|
|
||||||
|
PUT_UINT32_BE (high, msglen, 0);
|
||||||
|
PUT_UINT32_BE (low, msglen, 4);
|
||||||
|
|
||||||
|
last = ctx->total[0] & 0x3F;
|
||||||
|
padn = (last < 56) ? (56 - last) : (120 - last);
|
||||||
|
|
||||||
|
sha1_update (ctx, (unsigned char *) sha1_padding, padn);
|
||||||
|
sha1_update (ctx, msglen, 8);
|
||||||
|
|
||||||
|
PUT_UINT32_BE (ctx->state[0], output, 0);
|
||||||
|
PUT_UINT32_BE (ctx->state[1], output, 4);
|
||||||
|
PUT_UINT32_BE (ctx->state[2], output, 8);
|
||||||
|
PUT_UINT32_BE (ctx->state[3], output, 12);
|
||||||
|
PUT_UINT32_BE (ctx->state[4], output, 16);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Output = SHA-1( input buffer )
|
||||||
|
*/
|
||||||
|
void sha1_csum (unsigned char *input, int ilen, unsigned char output[20])
|
||||||
|
{
|
||||||
|
sha1_context ctx;
|
||||||
|
|
||||||
|
sha1_starts (&ctx);
|
||||||
|
sha1_update (&ctx, input, ilen);
|
||||||
|
sha1_finish (&ctx, output);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Output = HMAC-SHA-1( input buffer, hmac key )
|
||||||
|
*/
|
||||||
|
void sha1_hmac (unsigned char *key, int keylen,
|
||||||
|
unsigned char *input, int ilen, unsigned char output[20])
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
sha1_context ctx;
|
||||||
|
unsigned char k_ipad[64];
|
||||||
|
unsigned char k_opad[64];
|
||||||
|
unsigned char tmpbuf[20];
|
||||||
|
|
||||||
|
memset (k_ipad, 0x36, 64);
|
||||||
|
memset (k_opad, 0x5C, 64);
|
||||||
|
|
||||||
|
for (i = 0; i < keylen; i++) {
|
||||||
|
if (i >= 64)
|
||||||
|
break;
|
||||||
|
|
||||||
|
k_ipad[i] ^= key[i];
|
||||||
|
k_opad[i] ^= key[i];
|
||||||
|
}
|
||||||
|
|
||||||
|
sha1_starts (&ctx);
|
||||||
|
sha1_update (&ctx, k_ipad, 64);
|
||||||
|
sha1_update (&ctx, input, ilen);
|
||||||
|
sha1_finish (&ctx, tmpbuf);
|
||||||
|
|
||||||
|
sha1_starts (&ctx);
|
||||||
|
sha1_update (&ctx, k_opad, 64);
|
||||||
|
sha1_update (&ctx, tmpbuf, 20);
|
||||||
|
sha1_finish (&ctx, output);
|
||||||
|
|
||||||
|
memset (k_ipad, 0, 64);
|
||||||
|
memset (k_opad, 0, 64);
|
||||||
|
memset (tmpbuf, 0, 20);
|
||||||
|
memset (&ctx, 0, sizeof (sha1_context));
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char _sha1_src[] = "_sha1_src";
|
||||||
|
|
||||||
|
#ifdef SELF_TEST
|
||||||
|
/*
|
||||||
|
* FIPS-180-1 test vectors
|
||||||
|
*/
|
||||||
|
static const char sha1_test_str[3][57] = {
|
||||||
|
{"abc"},
|
||||||
|
{"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"},
|
||||||
|
{""}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const unsigned char sha1_test_sum[3][20] = {
|
||||||
|
{0xA9, 0x99, 0x3E, 0x36, 0x47, 0x06, 0x81, 0x6A, 0xBA, 0x3E,
|
||||||
|
0x25, 0x71, 0x78, 0x50, 0xC2, 0x6C, 0x9C, 0xD0, 0xD8, 0x9D},
|
||||||
|
{0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E, 0xBA, 0xAE,
|
||||||
|
0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5, 0xE5, 0x46, 0x70, 0xF1},
|
||||||
|
{0x34, 0xAA, 0x97, 0x3C, 0xD4, 0xC4, 0xDA, 0xA4, 0xF6, 0x1E,
|
||||||
|
0xEB, 0x2B, 0xDB, 0xAD, 0x27, 0x31, 0x65, 0x34, 0x01, 0x6F}
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Checkup routine
|
||||||
|
*/
|
||||||
|
int sha1_self_test (void)
|
||||||
|
{
|
||||||
|
int i, j;
|
||||||
|
unsigned char buf[1000];
|
||||||
|
unsigned char sha1sum[20];
|
||||||
|
sha1_context ctx;
|
||||||
|
|
||||||
|
for (i = 0; i < 3; i++) {
|
||||||
|
printf (" SHA-1 test #%d: ", i + 1);
|
||||||
|
|
||||||
|
sha1_starts (&ctx);
|
||||||
|
|
||||||
|
if (i < 2)
|
||||||
|
sha1_update (&ctx, (unsigned char *) sha1_test_str[i],
|
||||||
|
strlen (sha1_test_str[i]));
|
||||||
|
else {
|
||||||
|
memset (buf, 'a', 1000);
|
||||||
|
for (j = 0; j < 1000; j++)
|
||||||
|
sha1_update (&ctx, buf, 1000);
|
||||||
|
}
|
||||||
|
|
||||||
|
sha1_finish (&ctx, sha1sum);
|
||||||
|
|
||||||
|
if (memcmp (sha1sum, sha1_test_sum[i], 20) != 0) {
|
||||||
|
printf ("failed\n");
|
||||||
|
return (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
printf ("passed\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
printf ("\n");
|
||||||
|
return (0);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
int sha1_self_test (void)
|
||||||
|
{
|
||||||
|
return (0);
|
||||||
|
}
|
||||||
|
#endif
|
|
@ -902,7 +902,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
||||||
|
|
||||||
#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
|
#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
|
||||||
defined(CONFIG_TQM8272) || \
|
defined(CONFIG_TQM8272) || \
|
||||||
defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
|
defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || \
|
||||||
|
defined(CONFIG_KUP4X) || defined(CONFIG_PCS440EP)
|
||||||
load_sernum_ethaddr ();
|
load_sernum_ethaddr ();
|
||||||
#endif
|
#endif
|
||||||
/* IP Address */
|
/* IP Address */
|
||||||
|
@ -967,7 +968,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
||||||
serial_buffered_init();
|
serial_buffered_init();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_STATUS_LED
|
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
|
||||||
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
10
net/eth.c
10
net/eth.c
|
@ -28,6 +28,14 @@
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||||
|
|
||||||
|
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
|
||||||
|
# include <status_led.h>
|
||||||
|
extern void show_ethcfg_progress (int arg);
|
||||||
|
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg)
|
||||||
|
#else
|
||||||
|
# define SHOW_BOOT_PROGRESS(arg)
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef CFG_GT_6426x
|
#ifdef CFG_GT_6426x
|
||||||
extern int gt6426x_eth_initialize(bd_t *bis);
|
extern int gt6426x_eth_initialize(bd_t *bis);
|
||||||
#endif
|
#endif
|
||||||
|
@ -247,10 +255,12 @@ int eth_initialize(bd_t *bis)
|
||||||
|
|
||||||
if (!eth_devices) {
|
if (!eth_devices) {
|
||||||
puts ("No ethernet found.\n");
|
puts ("No ethernet found.\n");
|
||||||
|
SHOW_BOOT_PROGRESS(-64);
|
||||||
} else {
|
} else {
|
||||||
struct eth_device *dev = eth_devices;
|
struct eth_device *dev = eth_devices;
|
||||||
char *ethprime = getenv ("ethprime");
|
char *ethprime = getenv ("ethprime");
|
||||||
|
|
||||||
|
SHOW_BOOT_PROGRESS(65);
|
||||||
do {
|
do {
|
||||||
if (eth_number)
|
if (eth_number)
|
||||||
puts (", ");
|
puts (", ");
|
||||||
|
|
|
@ -24,6 +24,6 @@
|
||||||
LIB = libpostmpc8xx.a
|
LIB = libpostmpc8xx.a
|
||||||
|
|
||||||
AOBJS = cache_8xx.o
|
AOBJS = cache_8xx.o
|
||||||
COBJS = ether.o spr.o uart.o usb.o watchdog.o
|
COBJS = cache.o ether.o spr.o uart.o usb.o watchdog.o
|
||||||
|
|
||||||
include $(TOPDIR)/post/rules.mk
|
include $(TOPDIR)/post/rules.mk
|
||||||
|
|
|
@ -23,6 +23,7 @@
|
||||||
|
|
||||||
LIB = libpostppc4xx.a
|
LIB = libpostppc4xx.a
|
||||||
|
|
||||||
COBJS = fpu.o spr.o uart.o watchdog.o
|
AOBJS = cache_4xx.o
|
||||||
|
COBJS = cache.o ether.o fpu.o spr.o uart.o watchdog.o
|
||||||
|
|
||||||
include $(TOPDIR)/post/rules.mk
|
include $(TOPDIR)/post/rules.mk
|
||||||
|
|
|
@ -0,0 +1,114 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* Author: Igor Lisitsin <igor@emcraft.com>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
/* Cache test
|
||||||
|
*
|
||||||
|
* This test verifies the CPU data and instruction cache using
|
||||||
|
* several test scenarios.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_CACHE
|
||||||
|
|
||||||
|
#include <asm/mmu.h>
|
||||||
|
#include <watchdog.h>
|
||||||
|
|
||||||
|
#define CACHE_POST_SIZE 1024
|
||||||
|
|
||||||
|
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
|
||||||
|
|
||||||
|
int cache_post_test1 (int tlb, void *p, int size);
|
||||||
|
int cache_post_test2 (int tlb, void *p, int size);
|
||||||
|
int cache_post_test3 (int tlb, void *p, int size);
|
||||||
|
int cache_post_test4 (int tlb, void *p, int size);
|
||||||
|
int cache_post_test5 (int tlb, void *p, int size);
|
||||||
|
int cache_post_test6 (int tlb, void *p, int size);
|
||||||
|
|
||||||
|
static int tlb = -1; /* index to the victim TLB entry */
|
||||||
|
|
||||||
|
static unsigned char testarea[CACHE_POST_SIZE]
|
||||||
|
__attribute__((__aligned__(CACHE_POST_SIZE)));
|
||||||
|
|
||||||
|
int cache_post_test (int flags)
|
||||||
|
{
|
||||||
|
void* virt = (void*)CFG_POST_CACHE_ADDR;
|
||||||
|
int ints, i, res = 0;
|
||||||
|
u32 word0;
|
||||||
|
|
||||||
|
if (tlb < 0) {
|
||||||
|
/*
|
||||||
|
* Allocate a new TLB entry, since we are going to modify
|
||||||
|
* the write-through and caching inhibited storage attributes.
|
||||||
|
*/
|
||||||
|
program_tlb((u32)testarea, (u32)virt,
|
||||||
|
CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
|
||||||
|
|
||||||
|
/* Find the TLB entry */
|
||||||
|
for (i = 0;; i++) {
|
||||||
|
if (i >= PPC4XX_TLB_SIZE) {
|
||||||
|
printf ("Failed to program tlb entry\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
word0 = mftlb1(i);
|
||||||
|
if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
|
||||||
|
tlb = i;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ints = disable_interrupts ();
|
||||||
|
|
||||||
|
WATCHDOG_RESET ();
|
||||||
|
if (res == 0)
|
||||||
|
res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
|
||||||
|
WATCHDOG_RESET ();
|
||||||
|
if (res == 0)
|
||||||
|
res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
|
||||||
|
WATCHDOG_RESET ();
|
||||||
|
if (res == 0)
|
||||||
|
res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
|
||||||
|
WATCHDOG_RESET ();
|
||||||
|
if (res == 0)
|
||||||
|
res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
|
||||||
|
WATCHDOG_RESET ();
|
||||||
|
if (res == 0)
|
||||||
|
res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
|
||||||
|
WATCHDOG_RESET ();
|
||||||
|
if (res == 0)
|
||||||
|
res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
|
||||||
|
|
||||||
|
if (ints)
|
||||||
|
enable_interrupts ();
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_CACHE */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,448 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* Author: Igor Lisitsin <igor@emcraft.com>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
#include <ppc_asm.tmpl>
|
||||||
|
#include <ppc_defs.h>
|
||||||
|
#include <asm/cache.h>
|
||||||
|
#include <asm/mmu.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_CACHE
|
||||||
|
|
||||||
|
.text
|
||||||
|
|
||||||
|
/* void cache_post_disable (int tlb)
|
||||||
|
*/
|
||||||
|
cache_post_disable:
|
||||||
|
tlbre r0, r3, 0x0002
|
||||||
|
ori r0, r0, TLB_WORD2_I_ENABLE@l
|
||||||
|
tlbwe r0, r3, 0x0002
|
||||||
|
sync
|
||||||
|
isync
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* void cache_post_wt (int tlb)
|
||||||
|
*/
|
||||||
|
cache_post_wt:
|
||||||
|
tlbre r0, r3, 0x0002
|
||||||
|
ori r0, r0, TLB_WORD2_W_ENABLE@l
|
||||||
|
andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
|
||||||
|
tlbwe r0, r3, 0x0002
|
||||||
|
sync
|
||||||
|
isync
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* void cache_post_wb (int tlb)
|
||||||
|
*/
|
||||||
|
cache_post_wb:
|
||||||
|
tlbre r0, r3, 0x0002
|
||||||
|
andi. r0, r0, ~TLB_WORD2_W_ENABLE@l
|
||||||
|
andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
|
||||||
|
tlbwe r0, r3, 0x0002
|
||||||
|
sync
|
||||||
|
isync
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* void cache_post_dinvalidate (void *p, int size)
|
||||||
|
*/
|
||||||
|
cache_post_dinvalidate:
|
||||||
|
dcbi r0, r3
|
||||||
|
addi r3, r3, CFG_CACHELINE_SIZE
|
||||||
|
subic. r4, r4, CFG_CACHELINE_SIZE
|
||||||
|
bgt cache_post_dinvalidate
|
||||||
|
sync
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* void cache_post_dstore (void *p, int size)
|
||||||
|
*/
|
||||||
|
cache_post_dstore:
|
||||||
|
dcbst r0, r3
|
||||||
|
addi r3, r3, CFG_CACHELINE_SIZE
|
||||||
|
subic. r4, r4, CFG_CACHELINE_SIZE
|
||||||
|
bgt cache_post_dstore
|
||||||
|
sync
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* void cache_post_dtouch (void *p, int size)
|
||||||
|
*/
|
||||||
|
cache_post_dtouch:
|
||||||
|
dcbt r0, r3
|
||||||
|
addi r3, r3, CFG_CACHELINE_SIZE
|
||||||
|
subic. r4, r4, CFG_CACHELINE_SIZE
|
||||||
|
bgt cache_post_dtouch
|
||||||
|
sync
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* void cache_post_iinvalidate (void)
|
||||||
|
*/
|
||||||
|
cache_post_iinvalidate:
|
||||||
|
iccci r0, r0
|
||||||
|
sync
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* void cache_post_memset (void *p, int val, int size)
|
||||||
|
*/
|
||||||
|
cache_post_memset:
|
||||||
|
mtctr r5
|
||||||
|
1:
|
||||||
|
stb r4, 0(r3)
|
||||||
|
addi r3, r3, 1
|
||||||
|
bdnz 1b
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* int cache_post_check (void *p, int size)
|
||||||
|
*/
|
||||||
|
cache_post_check:
|
||||||
|
mtctr r4
|
||||||
|
1:
|
||||||
|
lbz r0, 0(r3)
|
||||||
|
addi r3, r3, 1
|
||||||
|
cmpwi r0, 0xff
|
||||||
|
bne 2f
|
||||||
|
bdnz 1b
|
||||||
|
li r3, 0
|
||||||
|
blr
|
||||||
|
2:
|
||||||
|
li r3, -1
|
||||||
|
blr
|
||||||
|
|
||||||
|
#define CACHE_POST_DISABLE() \
|
||||||
|
mr r3, r10; \
|
||||||
|
bl cache_post_disable
|
||||||
|
|
||||||
|
#define CACHE_POST_WT() \
|
||||||
|
mr r3, r10; \
|
||||||
|
bl cache_post_wt
|
||||||
|
|
||||||
|
#define CACHE_POST_WB() \
|
||||||
|
mr r3, r10; \
|
||||||
|
bl cache_post_wb
|
||||||
|
|
||||||
|
#define CACHE_POST_DINVALIDATE() \
|
||||||
|
mr r3, r11; \
|
||||||
|
mr r4, r12; \
|
||||||
|
bl cache_post_dinvalidate
|
||||||
|
|
||||||
|
#define CACHE_POST_DFLUSH() \
|
||||||
|
mr r3, r11; \
|
||||||
|
mr r4, r12; \
|
||||||
|
bl cache_post_dflush
|
||||||
|
|
||||||
|
#define CACHE_POST_DSTORE() \
|
||||||
|
mr r3, r11; \
|
||||||
|
mr r4, r12; \
|
||||||
|
bl cache_post_dstore
|
||||||
|
|
||||||
|
#define CACHE_POST_DTOUCH() \
|
||||||
|
mr r3, r11; \
|
||||||
|
mr r4, r12; \
|
||||||
|
bl cache_post_dtouch
|
||||||
|
|
||||||
|
#define CACHE_POST_IINVALIDATE() \
|
||||||
|
bl cache_post_iinvalidate
|
||||||
|
|
||||||
|
#define CACHE_POST_MEMSET(val) \
|
||||||
|
mr r3, r11; \
|
||||||
|
li r4, val; \
|
||||||
|
mr r5, r12; \
|
||||||
|
bl cache_post_memset
|
||||||
|
|
||||||
|
#define CACHE_POST_CHECK() \
|
||||||
|
mr r3, r11; \
|
||||||
|
mr r4, r12; \
|
||||||
|
bl cache_post_check; \
|
||||||
|
mr r13, r3
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Write and read 0xff pattern with caching enabled.
|
||||||
|
*/
|
||||||
|
.global cache_post_test1
|
||||||
|
cache_post_test1:
|
||||||
|
mflr r9
|
||||||
|
mr r10, r3 /* tlb */
|
||||||
|
mr r11, r4 /* p */
|
||||||
|
mr r12, r5 /* size */
|
||||||
|
|
||||||
|
CACHE_POST_WB()
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
|
||||||
|
/* Write the negative pattern to the test area */
|
||||||
|
CACHE_POST_MEMSET(0xff)
|
||||||
|
|
||||||
|
/* Read the test area */
|
||||||
|
CACHE_POST_CHECK()
|
||||||
|
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
CACHE_POST_DISABLE()
|
||||||
|
|
||||||
|
mr r3, r13
|
||||||
|
mtlr r9
|
||||||
|
blr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Write zeroes with caching enabled.
|
||||||
|
* Write 0xff pattern with caching disabled.
|
||||||
|
* Read 0xff pattern with caching enabled.
|
||||||
|
*/
|
||||||
|
.global cache_post_test2
|
||||||
|
cache_post_test2:
|
||||||
|
mflr r9
|
||||||
|
mr r10, r3 /* tlb */
|
||||||
|
mr r11, r4 /* p */
|
||||||
|
mr r12, r5 /* size */
|
||||||
|
|
||||||
|
CACHE_POST_WB()
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
|
||||||
|
/* Write the zero pattern to the test area */
|
||||||
|
CACHE_POST_MEMSET(0)
|
||||||
|
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
CACHE_POST_DISABLE()
|
||||||
|
|
||||||
|
/* Write the negative pattern to the test area */
|
||||||
|
CACHE_POST_MEMSET(0xff)
|
||||||
|
|
||||||
|
CACHE_POST_WB()
|
||||||
|
|
||||||
|
/* Read the test area */
|
||||||
|
CACHE_POST_CHECK()
|
||||||
|
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
CACHE_POST_DISABLE()
|
||||||
|
|
||||||
|
mr r3, r13
|
||||||
|
mtlr r9
|
||||||
|
blr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Write-through mode test.
|
||||||
|
* Write zeroes, store the cache, write 0xff pattern.
|
||||||
|
* Invalidate the cache.
|
||||||
|
* Check that 0xff pattern is read.
|
||||||
|
*/
|
||||||
|
.global cache_post_test3
|
||||||
|
cache_post_test3:
|
||||||
|
mflr r9
|
||||||
|
mr r10, r3 /* tlb */
|
||||||
|
mr r11, r4 /* p */
|
||||||
|
mr r12, r5 /* size */
|
||||||
|
|
||||||
|
CACHE_POST_WT()
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
|
||||||
|
/* Cache the test area */
|
||||||
|
CACHE_POST_DTOUCH()
|
||||||
|
|
||||||
|
/* Write the zero pattern to the test area */
|
||||||
|
CACHE_POST_MEMSET(0)
|
||||||
|
|
||||||
|
CACHE_POST_DSTORE()
|
||||||
|
|
||||||
|
/* Write the negative pattern to the test area */
|
||||||
|
CACHE_POST_MEMSET(0xff)
|
||||||
|
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
CACHE_POST_DISABLE()
|
||||||
|
|
||||||
|
/* Read the test area */
|
||||||
|
CACHE_POST_CHECK()
|
||||||
|
|
||||||
|
mr r3, r13
|
||||||
|
mtlr r9
|
||||||
|
blr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Write-back mode test.
|
||||||
|
* Write 0xff pattern, store the cache, write zeroes.
|
||||||
|
* Invalidate the cache.
|
||||||
|
* Check that 0xff pattern is read.
|
||||||
|
*/
|
||||||
|
.global cache_post_test4
|
||||||
|
cache_post_test4:
|
||||||
|
mflr r9
|
||||||
|
mr r10, r3 /* tlb */
|
||||||
|
mr r11, r4 /* p */
|
||||||
|
mr r12, r5 /* size */
|
||||||
|
|
||||||
|
CACHE_POST_WB()
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
|
||||||
|
/* Cache the test area */
|
||||||
|
CACHE_POST_DTOUCH()
|
||||||
|
|
||||||
|
/* Write the negative pattern to the test area */
|
||||||
|
CACHE_POST_MEMSET(0xff)
|
||||||
|
|
||||||
|
CACHE_POST_DSTORE()
|
||||||
|
|
||||||
|
/* Write the zero pattern to the test area */
|
||||||
|
CACHE_POST_MEMSET(0)
|
||||||
|
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
CACHE_POST_DISABLE()
|
||||||
|
|
||||||
|
/* Read the test area */
|
||||||
|
CACHE_POST_CHECK()
|
||||||
|
|
||||||
|
mr r3, r13
|
||||||
|
mtlr r9
|
||||||
|
blr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Load the test instructions into the instruction cache.
|
||||||
|
* Replace the test instructions.
|
||||||
|
* Check that the original instructions are executed.
|
||||||
|
*/
|
||||||
|
.global cache_post_test5
|
||||||
|
cache_post_test5:
|
||||||
|
mflr r9
|
||||||
|
mr r10, r3 /* tlb */
|
||||||
|
mr r11, r4 /* p */
|
||||||
|
mr r12, r5 /* size */
|
||||||
|
|
||||||
|
CACHE_POST_WT()
|
||||||
|
CACHE_POST_IINVALIDATE()
|
||||||
|
|
||||||
|
/* Compute r13 = cache_post_test_inst */
|
||||||
|
bl cache_post_test5_reloc
|
||||||
|
cache_post_test5_reloc:
|
||||||
|
mflr r13
|
||||||
|
lis r0, (cache_post_test_inst - cache_post_test5_reloc)@h
|
||||||
|
ori r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l
|
||||||
|
add r13, r13, r0
|
||||||
|
|
||||||
|
/* Copy the test instructions to the test area */
|
||||||
|
lwz r0, 0(r13)
|
||||||
|
stw r0, 0(r11)
|
||||||
|
lwz r0, 8(r13)
|
||||||
|
stw r0, 4(r11)
|
||||||
|
sync
|
||||||
|
|
||||||
|
/* Invalidate the cache line */
|
||||||
|
icbi r0, r11
|
||||||
|
sync
|
||||||
|
isync
|
||||||
|
|
||||||
|
/* Execute the test instructions */
|
||||||
|
mtlr r11
|
||||||
|
blrl
|
||||||
|
|
||||||
|
/* Replace the test instruction */
|
||||||
|
lwz r0, 4(r13)
|
||||||
|
stw r0, 0(r11)
|
||||||
|
sync
|
||||||
|
|
||||||
|
/* Do not invalidate the cache line */
|
||||||
|
isync
|
||||||
|
|
||||||
|
/* Execute the test instructions */
|
||||||
|
mtlr r11
|
||||||
|
blrl
|
||||||
|
mr r13, r3
|
||||||
|
|
||||||
|
CACHE_POST_IINVALIDATE()
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
CACHE_POST_DISABLE()
|
||||||
|
|
||||||
|
mr r3, r13
|
||||||
|
mtlr r9
|
||||||
|
blr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Load the test instructions into the instruction cache.
|
||||||
|
* Replace the test instructions and invalidate the cache.
|
||||||
|
* Check that the replaced instructions are executed.
|
||||||
|
*/
|
||||||
|
.global cache_post_test6
|
||||||
|
cache_post_test6:
|
||||||
|
mflr r9
|
||||||
|
mr r10, r3 /* tlb */
|
||||||
|
mr r11, r4 /* p */
|
||||||
|
mr r12, r5 /* size */
|
||||||
|
|
||||||
|
CACHE_POST_WT()
|
||||||
|
CACHE_POST_IINVALIDATE()
|
||||||
|
|
||||||
|
/* Compute r13 = cache_post_test_inst */
|
||||||
|
bl cache_post_test6_reloc
|
||||||
|
cache_post_test6_reloc:
|
||||||
|
mflr r13
|
||||||
|
lis r0, (cache_post_test_inst - cache_post_test6_reloc)@h
|
||||||
|
ori r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l
|
||||||
|
add r13, r13, r0
|
||||||
|
|
||||||
|
/* Copy the test instructions to the test area */
|
||||||
|
lwz r0, 4(r13)
|
||||||
|
stw r0, 0(r11)
|
||||||
|
lwz r0, 8(r13)
|
||||||
|
stw r0, 4(r11)
|
||||||
|
sync
|
||||||
|
|
||||||
|
/* Invalidate the cache line */
|
||||||
|
icbi r0, r11
|
||||||
|
sync
|
||||||
|
isync
|
||||||
|
|
||||||
|
/* Execute the test instructions */
|
||||||
|
mtlr r11
|
||||||
|
blrl
|
||||||
|
|
||||||
|
/* Replace the test instruction */
|
||||||
|
lwz r0, 0(r13)
|
||||||
|
stw r0, 0(r11)
|
||||||
|
sync
|
||||||
|
|
||||||
|
/* Invalidate the cache line */
|
||||||
|
icbi r0, r11
|
||||||
|
sync
|
||||||
|
isync
|
||||||
|
|
||||||
|
/* Execute the test instructions */
|
||||||
|
mtlr r11
|
||||||
|
blrl
|
||||||
|
mr r13, r3
|
||||||
|
|
||||||
|
CACHE_POST_IINVALIDATE()
|
||||||
|
CACHE_POST_DINVALIDATE()
|
||||||
|
CACHE_POST_DISABLE()
|
||||||
|
|
||||||
|
mr r3, r13
|
||||||
|
mtlr r9
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* Test instructions.
|
||||||
|
*/
|
||||||
|
cache_post_test_inst:
|
||||||
|
li r3, 0
|
||||||
|
li r3, -1
|
||||||
|
blr
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_CACHE */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,395 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* Author: Igor Lisitsin <igor@emcraft.com>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet test
|
||||||
|
*
|
||||||
|
* The Ethernet Media Access Controllers (EMAC) are tested in the
|
||||||
|
* internal loopback mode.
|
||||||
|
* The controllers are configured accordingly and several packets
|
||||||
|
* are transmitted. The configurable test parameters are:
|
||||||
|
* MIN_PACKET_LENGTH - minimum size of packet to transmit
|
||||||
|
* MAX_PACKET_LENGTH - maximum size of packet to transmit
|
||||||
|
* TEST_NUM - number of tests
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_ETHER
|
||||||
|
|
||||||
|
#include <asm/cache.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
#include <405_mal.h>
|
||||||
|
#include <ppc4xx_enet.h>
|
||||||
|
#include <malloc.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||||
|
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define MIN_PACKET_LENGTH 64
|
||||||
|
#define MAX_PACKET_LENGTH 256
|
||||||
|
#define TEST_NUM 1
|
||||||
|
|
||||||
|
static volatile mal_desc_t tx __cacheline_aligned;
|
||||||
|
static volatile mal_desc_t rx __cacheline_aligned;
|
||||||
|
static char *tx_buf;
|
||||||
|
static char *rx_buf;
|
||||||
|
|
||||||
|
static void ether_post_init (int devnum, int hw_addr)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
unsigned mode_reg;
|
||||||
|
#if defined(CONFIG_440GX) || \
|
||||||
|
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||||
|
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||||
|
sys_info_t sysinfo;
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
|
||||||
|
unsigned long mfr;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_440GX) || \
|
||||||
|
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||||
|
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||||
|
/* Need to get the OPB frequency so we can access the PHY */
|
||||||
|
get_sys_info (&sysinfo);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||||
|
/* provide clocks for EMAC internal loopback */
|
||||||
|
mfsdr (sdr_mfr, mfr);
|
||||||
|
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
|
||||||
|
mtsdr (sdr_mfr, mfr);
|
||||||
|
sync ();
|
||||||
|
#endif
|
||||||
|
/* reset emac */
|
||||||
|
out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
|
||||||
|
sync ();
|
||||||
|
|
||||||
|
for (i = 0;; i++) {
|
||||||
|
if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
|
||||||
|
break;
|
||||||
|
if (i >= 1000) {
|
||||||
|
printf ("Timeout resetting EMAC\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
udelay (1000);
|
||||||
|
}
|
||||||
|
#if defined(CONFIG_440GX) || \
|
||||||
|
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||||
|
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||||
|
/* Whack the M1 register */
|
||||||
|
mode_reg = 0x0;
|
||||||
|
if (sysinfo.freqOPB <= 50000000);
|
||||||
|
else if (sysinfo.freqOPB <= 66666667)
|
||||||
|
mode_reg |= EMAC_M1_OBCI_66;
|
||||||
|
else if (sysinfo.freqOPB <= 83333333)
|
||||||
|
mode_reg |= EMAC_M1_OBCI_83;
|
||||||
|
else if (sysinfo.freqOPB <= 100000000)
|
||||||
|
mode_reg |= EMAC_M1_OBCI_100;
|
||||||
|
else
|
||||||
|
mode_reg |= EMAC_M1_OBCI_GT100;
|
||||||
|
|
||||||
|
out32 (EMAC_M1 + hw_addr, mode_reg);
|
||||||
|
|
||||||
|
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
|
||||||
|
|
||||||
|
/* set the Mal configuration reg */
|
||||||
|
#if defined(CONFIG_440GX) || \
|
||||||
|
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||||
|
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||||
|
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
|
||||||
|
MAL_CR_PLBLT_DEFAULT | 0x00330000);
|
||||||
|
#else
|
||||||
|
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
|
||||||
|
/* Errata 1.12: MAL_1 -- Disable MAL bursting */
|
||||||
|
if (get_pvr() == PVR_440GP_RB) {
|
||||||
|
mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/* setup buffer descriptors */
|
||||||
|
tx.ctrl = MAL_TX_CTRL_WRAP;
|
||||||
|
tx.data_len = 0;
|
||||||
|
tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
|
||||||
|
|
||||||
|
rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
|
||||||
|
rx.data_len = 0;
|
||||||
|
rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
|
||||||
|
|
||||||
|
switch (devnum) {
|
||||||
|
case 1:
|
||||||
|
/* setup MAL tx & rx channel pointers */
|
||||||
|
#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
|
||||||
|
mtdcr (maltxctp2r, &tx);
|
||||||
|
#else
|
||||||
|
mtdcr (maltxctp1r, &tx);
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_440)
|
||||||
|
mtdcr (maltxbattr, 0x0);
|
||||||
|
mtdcr (malrxbattr, 0x0);
|
||||||
|
#endif
|
||||||
|
mtdcr (malrxctp1r, &rx);
|
||||||
|
/* set RX buffer size */
|
||||||
|
mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
|
||||||
|
break;
|
||||||
|
case 0:
|
||||||
|
default:
|
||||||
|
/* setup MAL tx & rx channel pointers */
|
||||||
|
#if defined(CONFIG_440)
|
||||||
|
mtdcr (maltxbattr, 0x0);
|
||||||
|
mtdcr (malrxbattr, 0x0);
|
||||||
|
#endif
|
||||||
|
mtdcr (maltxctp0r, &tx);
|
||||||
|
mtdcr (malrxctp0r, &rx);
|
||||||
|
/* set RX buffer size */
|
||||||
|
mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable MAL transmit and receive channels */
|
||||||
|
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||||
|
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
|
||||||
|
#else
|
||||||
|
mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
|
||||||
|
#endif
|
||||||
|
mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
|
||||||
|
|
||||||
|
/* set internal loopback mode */
|
||||||
|
out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
|
||||||
|
EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
|
||||||
|
EMAC_M1_MF_100MBPS | EMAC_M1_IST |
|
||||||
|
in32 (EMAC_M1));
|
||||||
|
|
||||||
|
/* set transmit enable & receive enable */
|
||||||
|
out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
|
||||||
|
|
||||||
|
/* enable broadcast address */
|
||||||
|
out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
|
||||||
|
|
||||||
|
/* set transmit request threshold register */
|
||||||
|
out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */
|
||||||
|
|
||||||
|
/* set receive low/high water mark register */
|
||||||
|
#if defined(CONFIG_440)
|
||||||
|
/* 440s has a 64 byte burst length */
|
||||||
|
out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
|
||||||
|
#else
|
||||||
|
/* 405s have a 16 byte burst length */
|
||||||
|
out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
|
||||||
|
#endif /* defined(CONFIG_440) */
|
||||||
|
out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
|
||||||
|
|
||||||
|
/* Set fifo limit entry in tx mode 0 */
|
||||||
|
out32 (EMAC_TXM0 + hw_addr, 0x00000003);
|
||||||
|
/* Frame gap set */
|
||||||
|
out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
|
||||||
|
sync ();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ether_post_halt (int devnum, int hw_addr)
|
||||||
|
{
|
||||||
|
int i = 0;
|
||||||
|
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||||
|
unsigned long mfr;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* 1st reset MAL channel */
|
||||||
|
/* Note: writing a 0 to a channel has no effect */
|
||||||
|
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||||
|
mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
|
||||||
|
#else
|
||||||
|
mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
|
||||||
|
#endif
|
||||||
|
mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
|
||||||
|
|
||||||
|
/* wait for reset */
|
||||||
|
while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
|
||||||
|
if (i++ >= 1000)
|
||||||
|
break;
|
||||||
|
udelay (1000);
|
||||||
|
}
|
||||||
|
/* emac reset */
|
||||||
|
out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
|
||||||
|
|
||||||
|
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||||
|
/* remove clocks for EMAC internal loopback */
|
||||||
|
mfsdr (sdr_mfr, mfr);
|
||||||
|
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
|
||||||
|
mtsdr (sdr_mfr, mfr);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
|
||||||
|
{
|
||||||
|
int i = 0;
|
||||||
|
|
||||||
|
while (tx.ctrl & MAL_TX_CTRL_READY) {
|
||||||
|
if (i++ > 100) {
|
||||||
|
printf ("TX timeout\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
udelay (1000);
|
||||||
|
}
|
||||||
|
tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
|
||||||
|
EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
|
||||||
|
tx.data_len = length;
|
||||||
|
memcpy (tx.data_ptr, packet, length);
|
||||||
|
sync ();
|
||||||
|
|
||||||
|
out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
|
||||||
|
sync ();
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
|
||||||
|
{
|
||||||
|
int length;
|
||||||
|
int i = 0;
|
||||||
|
|
||||||
|
while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
|
||||||
|
if (i++ > 100) {
|
||||||
|
printf ("RX timeout\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
udelay (1000);
|
||||||
|
}
|
||||||
|
length = rx.data_len - 4;
|
||||||
|
if (length <= max_length)
|
||||||
|
memcpy(packet, rx.data_ptr, length);
|
||||||
|
sync ();
|
||||||
|
|
||||||
|
rx.ctrl |= MAL_RX_CTRL_EMPTY;
|
||||||
|
sync ();
|
||||||
|
|
||||||
|
return length;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Test routines
|
||||||
|
*/
|
||||||
|
|
||||||
|
static void packet_fill (char *packet, int length)
|
||||||
|
{
|
||||||
|
char c = (char) length;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* set up ethernet header */
|
||||||
|
memset (packet, 0xff, 14);
|
||||||
|
|
||||||
|
for (i = 14; i < length; i++) {
|
||||||
|
packet[i] = c++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int packet_check (char *packet, int length)
|
||||||
|
{
|
||||||
|
char c = (char) length;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 14; i < length; i++) {
|
||||||
|
if (packet[i] != c++)
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int test_ctlr (int devnum, int hw_addr)
|
||||||
|
{
|
||||||
|
int res = -1;
|
||||||
|
char packet_send[MAX_PACKET_LENGTH];
|
||||||
|
char packet_recv[MAX_PACKET_LENGTH];
|
||||||
|
int length;
|
||||||
|
int i;
|
||||||
|
int l;
|
||||||
|
|
||||||
|
ether_post_init (devnum, hw_addr);
|
||||||
|
|
||||||
|
for (i = 0; i < TEST_NUM; i++) {
|
||||||
|
for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
|
||||||
|
packet_fill (packet_send, l);
|
||||||
|
|
||||||
|
ether_post_send (devnum, hw_addr, packet_send, l);
|
||||||
|
|
||||||
|
length = ether_post_recv (devnum, hw_addr, packet_recv,
|
||||||
|
sizeof (packet_recv));
|
||||||
|
|
||||||
|
if (length != l || packet_check (packet_recv, length) < 0) {
|
||||||
|
goto Done;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
res = 0;
|
||||||
|
|
||||||
|
Done:
|
||||||
|
|
||||||
|
ether_post_halt (devnum, hw_addr);
|
||||||
|
|
||||||
|
if (res != 0) {
|
||||||
|
post_log ("EMAC%d test failed\n", devnum);
|
||||||
|
}
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
int ether_post_test (int flags)
|
||||||
|
{
|
||||||
|
int res = 0;
|
||||||
|
|
||||||
|
/* Allocate tx & rx packet buffers */
|
||||||
|
tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
|
||||||
|
rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
|
||||||
|
|
||||||
|
if (!tx_buf || !rx_buf) {
|
||||||
|
printf ("Failed to allocate packet buffers\n");
|
||||||
|
res = -1;
|
||||||
|
goto out_free;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* EMAC0 */
|
||||||
|
if (test_ctlr (0, 0))
|
||||||
|
res = -1;
|
||||||
|
|
||||||
|
/* EMAC1 */
|
||||||
|
if (test_ctlr (1, 0x100))
|
||||||
|
res = -1;
|
||||||
|
|
||||||
|
out_free:
|
||||||
|
free (tx_buf);
|
||||||
|
free (rx_buf);
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_ETHER */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -1,5 +1,8 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (C) 2007 Wolfgang Denk <wd@denx.de>
|
* (C) Copyright 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* Author: Sergei Poselenov <sposelenov@emcraft.com>
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
|
@ -51,5 +54,6 @@ void fpu_enable(void)
|
||||||
mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
|
mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
|
||||||
mtmsr(mfmsr() | MSR_FP);
|
mtmsr(mfmsr() | MSR_FP);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif /* CONFIG_POST */
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
* (C) Copyright 2007
|
* (C) Copyright 2007
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
|
* Author: Igor Lisitsin <igor@emcraft.com>
|
||||||
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
*
|
*
|
||||||
|
@ -39,12 +41,13 @@
|
||||||
|
|
||||||
#if CONFIG_POST & CFG_POST_SPR
|
#if CONFIG_POST & CFG_POST_SPR
|
||||||
|
|
||||||
static struct
|
#include <asm/processor.h>
|
||||||
{
|
|
||||||
int number;
|
static struct {
|
||||||
char * name;
|
int number;
|
||||||
unsigned long mask;
|
char * name;
|
||||||
unsigned long value;
|
unsigned long mask;
|
||||||
|
unsigned long value;
|
||||||
} spr_test_list [] = {
|
} spr_test_list [] = {
|
||||||
/* Standard Special-Purpose Registers */
|
/* Standard Special-Purpose Registers */
|
||||||
|
|
||||||
|
@ -60,8 +63,10 @@ static struct
|
||||||
{0x113, "SPRG3", 0x00000000, 0x00000000},
|
{0x113, "SPRG3", 0x00000000, 0x00000000},
|
||||||
{0x11f, "PVR", 0x00000000, 0x00000000},
|
{0x11f, "PVR", 0x00000000, 0x00000000},
|
||||||
|
|
||||||
/* Additional Special-Purpose Registers */
|
/* Additional Special-Purpose Registers.
|
||||||
|
* The values must match the initialization
|
||||||
|
* values from cpu/ppc4xx/start.S
|
||||||
|
*/
|
||||||
{0x30, "PID", 0x00000000, 0x00000000},
|
{0x30, "PID", 0x00000000, 0x00000000},
|
||||||
{0x3a, "CSRR0", 0x00000000, 0x00000000},
|
{0x3a, "CSRR0", 0x00000000, 0x00000000},
|
||||||
{0x3b, "CSRR1", 0x00000000, 0x00000000},
|
{0x3b, "CSRR1", 0x00000000, 0x00000000},
|
||||||
|
@ -90,22 +95,22 @@ static struct
|
||||||
{0x13f, "DVC2", 0x00000000, 0x00000000},
|
{0x13f, "DVC2", 0x00000000, 0x00000000},
|
||||||
{0x150, "TSR", 0x00000000, 0x00000000},
|
{0x150, "TSR", 0x00000000, 0x00000000},
|
||||||
{0x154, "TCR", 0x00000000, 0x00000000},
|
{0x154, "TCR", 0x00000000, 0x00000000},
|
||||||
{0x190, "IVOR0", 0x00000000, 0x00000000},
|
{0x190, "IVOR0", 0x0000fff0, 0x00000100},
|
||||||
{0x191, "IVOR1", 0x00000000, 0x00000000},
|
{0x191, "IVOR1", 0x0000fff0, 0x00000200},
|
||||||
{0x192, "IVOR2", 0x00000000, 0x00000000},
|
{0x192, "IVOR2", 0x0000fff0, 0x00000300},
|
||||||
{0x193, "IVOR3", 0x00000000, 0x00000000},
|
{0x193, "IVOR3", 0x0000fff0, 0x00000400},
|
||||||
{0x194, "IVOR4", 0x00000000, 0x00000000},
|
{0x194, "IVOR4", 0x0000fff0, 0x00000500},
|
||||||
{0x195, "IVOR5", 0x00000000, 0x00000000},
|
{0x195, "IVOR5", 0x0000fff0, 0x00000600},
|
||||||
{0x196, "IVOR6", 0x00000000, 0x00000000},
|
{0x196, "IVOR6", 0x0000fff0, 0x00000700},
|
||||||
{0x197, "IVOR7", 0x00000000, 0x00000000},
|
{0x197, "IVOR7", 0x0000fff0, 0x00000800},
|
||||||
{0x198, "IVOR8", 0x00000000, 0x00000000},
|
{0x198, "IVOR8", 0x0000fff0, 0x00000c00},
|
||||||
{0x199, "IVOR9", 0x00000000, 0x00000000},
|
{0x199, "IVOR9", 0x00000000, 0x00000000},
|
||||||
{0x19a, "IVOR10", 0x00000000, 0x00000000},
|
{0x19a, "IVOR10", 0x0000fff0, 0x00000900},
|
||||||
{0x19b, "IVOR11", 0x00000000, 0x00000000},
|
{0x19b, "IVOR11", 0x00000000, 0x00000000},
|
||||||
{0x19c, "IVOR12", 0x00000000, 0x00000000},
|
{0x19c, "IVOR12", 0x00000000, 0x00000000},
|
||||||
{0x19d, "IVOR13", 0x00000000, 0x00000000},
|
{0x19d, "IVOR13", 0x0000fff0, 0x00001300},
|
||||||
{0x19e, "IVOR14", 0x00000000, 0x00000000},
|
{0x19e, "IVOR14", 0x0000fff0, 0x00001400},
|
||||||
{0x19f, "IVOR15", 0x00000000, 0x00000000},
|
{0x19f, "IVOR15", 0x0000fff0, 0x00002000},
|
||||||
{0x23a, "MCSRR0", 0x00000000, 0x00000000},
|
{0x23a, "MCSRR0", 0x00000000, 0x00000000},
|
||||||
{0x23b, "MCSRR1", 0x00000000, 0x00000000},
|
{0x23b, "MCSRR1", 0x00000000, 0x00000000},
|
||||||
{0x23c, "MCSR", 0x00000000, 0x00000000},
|
{0x23c, "MCSR", 0x00000000, 0x00000000},
|
||||||
|
@ -126,8 +131,8 @@ static struct
|
||||||
{0x395, "DTV1", 0x00000000, 0x00000000},
|
{0x395, "DTV1", 0x00000000, 0x00000000},
|
||||||
{0x396, "DTV2", 0x00000000, 0x00000000},
|
{0x396, "DTV2", 0x00000000, 0x00000000},
|
||||||
{0x397, "DTV3", 0x00000000, 0x00000000},
|
{0x397, "DTV3", 0x00000000, 0x00000000},
|
||||||
{0x398, "DVLIM", 0x00000000, 0x00000000},
|
{0x398, "DVLIM", 0x0fc1f83f, 0x0001f800},
|
||||||
{0x399, "IVLIM", 0x00000000, 0x00000000},
|
{0x399, "IVLIM", 0x0fc1f83f, 0x0001f800},
|
||||||
{0x39b, "RSTCFG", 0x00000000, 0x00000000},
|
{0x39b, "RSTCFG", 0x00000000, 0x00000000},
|
||||||
{0x39c, "DCDBTRL", 0x00000000, 0x00000000},
|
{0x39c, "DCDBTRL", 0x00000000, 0x00000000},
|
||||||
{0x39d, "DCDBTRH", 0x00000000, 0x00000000},
|
{0x39d, "DCDBTRH", 0x00000000, 0x00000000},
|
||||||
|
@ -172,5 +177,6 @@ int spr_post_test (int flags)
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_POST & CFG_POST_SPR */
|
#endif /* CONFIG_POST & CFG_POST_SPR */
|
||||||
#endif /* CONFIG_POST */
|
#endif /* CONFIG_POST */
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
* (C) Copyright 2007
|
* (C) Copyright 2007
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
|
* Author: Igor Lisitsin <igor@emcraft.com>
|
||||||
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
*
|
*
|
||||||
|
@ -210,5 +212,4 @@ int uart_post_test (int flags)
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_POST & CFG_POST_UART */
|
#endif /* CONFIG_POST & CFG_POST_UART */
|
||||||
|
|
||||||
#endif /* CONFIG_POST */
|
#endif /* CONFIG_POST */
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
* (C) Copyright 2007
|
* (C) Copyright 2007
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
|
* Author: Igor Lisitsin <igor@emcraft.com>
|
||||||
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
*
|
*
|
||||||
|
@ -36,17 +38,18 @@
|
||||||
#ifdef CONFIG_POST
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
#include <post.h>
|
#include <post.h>
|
||||||
#include <watchdog.h>
|
|
||||||
|
|
||||||
#if CONFIG_POST & CFG_POST_WATCHDOG
|
#if CONFIG_POST & CFG_POST_WATCHDOG
|
||||||
|
|
||||||
|
#include <watchdog.h>
|
||||||
|
|
||||||
int watchdog_post_test (int flags)
|
int watchdog_post_test (int flags)
|
||||||
{
|
{
|
||||||
if (flags & POST_REBOOT) {
|
if (flags & POST_REBOOT) {
|
||||||
/* Test passed */
|
/* Test passed */
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
} else {
|
}
|
||||||
|
else {
|
||||||
/* 10-second delay */
|
/* 10-second delay */
|
||||||
int ints = disable_interrupts ();
|
int ints = disable_interrupts ();
|
||||||
ulong base = post_time_ms (0);
|
ulong base = post_time_ms (0);
|
||||||
|
|
|
@ -26,6 +26,6 @@ SUBDIRS =
|
||||||
|
|
||||||
LIB = libpostdrivers.a
|
LIB = libpostdrivers.a
|
||||||
|
|
||||||
COBJS = cache.o i2c.o memory.o rtc.o
|
COBJS = i2c.o memory.o rtc.o
|
||||||
|
|
||||||
include $(TOPDIR)/post/rules.mk
|
include $(TOPDIR)/post/rules.mk
|
||||||
|
|
|
@ -21,6 +21,7 @@
|
||||||
# MA 02111-1307 USA
|
# MA 02111-1307 USA
|
||||||
#
|
#
|
||||||
|
|
||||||
|
SUBDIRS = fpu
|
||||||
|
|
||||||
LIB = libpostppc.a
|
LIB = libpostppc.a
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,62 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* This file is originally a part of the GCC testsuite.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_FPU
|
||||||
|
|
||||||
|
int fpu_post_test_math1 (void)
|
||||||
|
{
|
||||||
|
volatile double a, *p;
|
||||||
|
double c, d;
|
||||||
|
volatile double b;
|
||||||
|
|
||||||
|
d = 1.0;
|
||||||
|
p = &b;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
c = d;
|
||||||
|
d = c * 0.5;
|
||||||
|
b = 1 + d;
|
||||||
|
} while (b != 1.0);
|
||||||
|
|
||||||
|
a = 1.0 + c;
|
||||||
|
|
||||||
|
if (a == 1.0) {
|
||||||
|
post_log ("Error in FPU math1 test\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_FPU */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,66 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* This file is originally a part of the GCC testsuite.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_FPU
|
||||||
|
|
||||||
|
static float rintf (float x)
|
||||||
|
{
|
||||||
|
volatile float TWO23 = 8388608.0;
|
||||||
|
|
||||||
|
if (__builtin_fabs (x) < TWO23)
|
||||||
|
{
|
||||||
|
if (x > 0.0)
|
||||||
|
{
|
||||||
|
x += TWO23;
|
||||||
|
x -= TWO23;
|
||||||
|
}
|
||||||
|
else if (x < 0.0)
|
||||||
|
{
|
||||||
|
x = TWO23 - x;
|
||||||
|
x = -(x - TWO23);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return x;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fpu_post_test_math2 (void)
|
||||||
|
{
|
||||||
|
if (rintf (-1.5) != -2.0) {
|
||||||
|
post_log ("Error in FPU math2 test\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_FPU */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,54 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* This file is originally a part of the GCC testsuite.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_FPU
|
||||||
|
|
||||||
|
int fpu_post_test_math3 (void)
|
||||||
|
{
|
||||||
|
volatile long double dfrom = 1.1;
|
||||||
|
volatile long double m1;
|
||||||
|
volatile long double m2;
|
||||||
|
volatile unsigned long mant_long;
|
||||||
|
|
||||||
|
m1 = dfrom / 2.0;
|
||||||
|
m2 = m1 * 4294967296.0;
|
||||||
|
mant_long = ((unsigned long) m2) & 0xffffffff;
|
||||||
|
|
||||||
|
if (mant_long != 0x8ccccccc) {
|
||||||
|
post_log ("Error in FPU math3 test\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_FPU */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,60 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* This file is originally a part of the GCC testsuite.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_FPU
|
||||||
|
|
||||||
|
int fpu_post_test_math4 (void)
|
||||||
|
{
|
||||||
|
volatile float reale = 1.0f;
|
||||||
|
volatile float oneplus;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (sizeof (float) != 4)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
for (i = 0; ; i++)
|
||||||
|
{
|
||||||
|
oneplus = 1.0f + reale;
|
||||||
|
if (oneplus == 1.0f)
|
||||||
|
break;
|
||||||
|
reale = reale / 2.0f;
|
||||||
|
}
|
||||||
|
/* Assumes ieee754 accurate arithmetic above. */
|
||||||
|
if (i != 24) {
|
||||||
|
post_log ("Error in FPU math4 test\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_FPU */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,32 @@
|
||||||
|
#
|
||||||
|
# (C) Copyright 2007
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
|
||||||
|
LIB = libpostppcfpu.a
|
||||||
|
|
||||||
|
COBJS += fpu.o 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o
|
||||||
|
COBJS += acc1.o compare-fp-1.o mul-subnormal-single-1.o
|
||||||
|
|
||||||
|
include $(TOPDIR)/post/rules.mk
|
||||||
|
|
||||||
|
CFLAGS += -mhard-float -fkeep-inline-functions
|
|
@ -0,0 +1,57 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* This file is originally a part of the GCC testsuite.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_FPU
|
||||||
|
|
||||||
|
static double func (const double *array)
|
||||||
|
{
|
||||||
|
double d = *array;
|
||||||
|
|
||||||
|
if (d == 0.0)
|
||||||
|
return d;
|
||||||
|
else
|
||||||
|
return d + func (array + 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
int fpu_post_test_math5 (void)
|
||||||
|
{
|
||||||
|
double values[] = { 0.1e-100, 1.0, -1.0, 0.0 };
|
||||||
|
|
||||||
|
if (func (values) != 0.1e-100) {
|
||||||
|
post_log ("Error in FPU math5 test\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_FPU */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,225 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* Test for correctness of composite floating-point comparisons.
|
||||||
|
* Written by Paolo Bonzini, 26th May 2004.
|
||||||
|
* This file is originally a part of the GCC testsuite.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_FPU
|
||||||
|
|
||||||
|
static int failed;
|
||||||
|
|
||||||
|
#define TEST(c) if ((c) != ok) failed++
|
||||||
|
#define ORD(a, b) (!__builtin_isunordered ((a), (b)))
|
||||||
|
#define UNORD(a, b) (__builtin_isunordered ((a), (b)))
|
||||||
|
#define UNEQ(a, b) (__builtin_isunordered ((a), (b)) || ((a) == (b)))
|
||||||
|
#define UNLT(a, b) (__builtin_isunordered ((a), (b)) || ((a) < (b)))
|
||||||
|
#define UNLE(a, b) (__builtin_isunordered ((a), (b)) || ((a) <= (b)))
|
||||||
|
#define UNGT(a, b) (__builtin_isunordered ((a), (b)) || ((a) > (b)))
|
||||||
|
#define UNGE(a, b) (__builtin_isunordered ((a), (b)) || ((a) >= (b)))
|
||||||
|
#define LTGT(a, b) (__builtin_islessgreater ((a), (b)))
|
||||||
|
|
||||||
|
static float pinf;
|
||||||
|
static float ninf;
|
||||||
|
static float NaN;
|
||||||
|
|
||||||
|
static void iuneq (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (UNEQ (x, y));
|
||||||
|
TEST (!LTGT (x, y));
|
||||||
|
TEST (UNLE (x, y) && UNGE (x,y));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ieq (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (ORD (x, y) && UNEQ (x, y));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void iltgt (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (!UNEQ (x, y)); /* Not optimizable. */
|
||||||
|
TEST (LTGT (x, y)); /* Same, __builtin_islessgreater does not trap. */
|
||||||
|
TEST (ORD (x, y) && (UNLT (x, y) || UNGT (x,y)));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ine (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (UNLT (x, y) || UNGT (x, y));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void iunlt (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (UNLT (x, y));
|
||||||
|
TEST (UNORD (x, y) || (x < y));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ilt (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (ORD (x, y) && UNLT (x, y)); /* Not optimized */
|
||||||
|
TEST ((x <= y) && (x != y));
|
||||||
|
TEST ((x <= y) && (y != x));
|
||||||
|
TEST ((x != y) && (x <= y)); /* Not optimized */
|
||||||
|
TEST ((y != x) && (x <= y)); /* Not optimized */
|
||||||
|
}
|
||||||
|
|
||||||
|
static void iunle (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (UNLE (x, y));
|
||||||
|
TEST (UNORD (x, y) || (x <= y));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ile (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (ORD (x, y) && UNLE (x, y)); /* Not optimized */
|
||||||
|
TEST ((x < y) || (x == y));
|
||||||
|
TEST ((y > x) || (x == y));
|
||||||
|
TEST ((x == y) || (x < y)); /* Not optimized */
|
||||||
|
TEST ((y == x) || (x < y)); /* Not optimized */
|
||||||
|
}
|
||||||
|
|
||||||
|
static void iungt (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (UNGT (x, y));
|
||||||
|
TEST (UNORD (x, y) || (x > y));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void igt (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (ORD (x, y) && UNGT (x, y)); /* Not optimized */
|
||||||
|
TEST ((x >= y) && (x != y));
|
||||||
|
TEST ((x >= y) && (y != x));
|
||||||
|
TEST ((x != y) && (x >= y)); /* Not optimized */
|
||||||
|
TEST ((y != x) && (x >= y)); /* Not optimized */
|
||||||
|
}
|
||||||
|
|
||||||
|
static void iunge (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (UNGE (x, y));
|
||||||
|
TEST (UNORD (x, y) || (x >= y));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ige (float x, float y, int ok)
|
||||||
|
{
|
||||||
|
TEST (ORD (x, y) && UNGE (x, y)); /* Not optimized */
|
||||||
|
TEST ((x > y) || (x == y));
|
||||||
|
TEST ((y < x) || (x == y));
|
||||||
|
TEST ((x == y) || (x > y)); /* Not optimized */
|
||||||
|
TEST ((y == x) || (x > y)); /* Not optimized */
|
||||||
|
}
|
||||||
|
|
||||||
|
int fpu_post_test_math6 (void)
|
||||||
|
{
|
||||||
|
pinf = __builtin_inf ();
|
||||||
|
ninf = -__builtin_inf ();
|
||||||
|
NaN = __builtin_nan ("");
|
||||||
|
|
||||||
|
iuneq (ninf, pinf, 0);
|
||||||
|
iuneq (NaN, NaN, 1);
|
||||||
|
iuneq (pinf, ninf, 0);
|
||||||
|
iuneq (1, 4, 0);
|
||||||
|
iuneq (3, 3, 1);
|
||||||
|
iuneq (5, 2, 0);
|
||||||
|
|
||||||
|
ieq (1, 4, 0);
|
||||||
|
ieq (3, 3, 1);
|
||||||
|
ieq (5, 2, 0);
|
||||||
|
|
||||||
|
iltgt (ninf, pinf, 1);
|
||||||
|
iltgt (NaN, NaN, 0);
|
||||||
|
iltgt (pinf, ninf, 1);
|
||||||
|
iltgt (1, 4, 1);
|
||||||
|
iltgt (3, 3, 0);
|
||||||
|
iltgt (5, 2, 1);
|
||||||
|
|
||||||
|
ine (1, 4, 1);
|
||||||
|
ine (3, 3, 0);
|
||||||
|
ine (5, 2, 1);
|
||||||
|
|
||||||
|
iunlt (NaN, ninf, 1);
|
||||||
|
iunlt (pinf, NaN, 1);
|
||||||
|
iunlt (pinf, ninf, 0);
|
||||||
|
iunlt (pinf, pinf, 0);
|
||||||
|
iunlt (ninf, ninf, 0);
|
||||||
|
iunlt (1, 4, 1);
|
||||||
|
iunlt (3, 3, 0);
|
||||||
|
iunlt (5, 2, 0);
|
||||||
|
|
||||||
|
ilt (1, 4, 1);
|
||||||
|
ilt (3, 3, 0);
|
||||||
|
ilt (5, 2, 0);
|
||||||
|
|
||||||
|
iunle (NaN, ninf, 1);
|
||||||
|
iunle (pinf, NaN, 1);
|
||||||
|
iunle (pinf, ninf, 0);
|
||||||
|
iunle (pinf, pinf, 1);
|
||||||
|
iunle (ninf, ninf, 1);
|
||||||
|
iunle (1, 4, 1);
|
||||||
|
iunle (3, 3, 1);
|
||||||
|
iunle (5, 2, 0);
|
||||||
|
|
||||||
|
ile (1, 4, 1);
|
||||||
|
ile (3, 3, 1);
|
||||||
|
ile (5, 2, 0);
|
||||||
|
|
||||||
|
iungt (NaN, ninf, 1);
|
||||||
|
iungt (pinf, NaN, 1);
|
||||||
|
iungt (pinf, ninf, 1);
|
||||||
|
iungt (pinf, pinf, 0);
|
||||||
|
iungt (ninf, ninf, 0);
|
||||||
|
iungt (1, 4, 0);
|
||||||
|
iungt (3, 3, 0);
|
||||||
|
iungt (5, 2, 1);
|
||||||
|
|
||||||
|
igt (1, 4, 0);
|
||||||
|
igt (3, 3, 0);
|
||||||
|
igt (5, 2, 1);
|
||||||
|
|
||||||
|
iunge (NaN, ninf, 1);
|
||||||
|
iunge (pinf, NaN, 1);
|
||||||
|
iunge (ninf, pinf, 0);
|
||||||
|
iunge (pinf, pinf, 1);
|
||||||
|
iunge (ninf, ninf, 1);
|
||||||
|
iunge (1, 4, 0);
|
||||||
|
iunge (3, 3, 1);
|
||||||
|
iunge (5, 2, 1);
|
||||||
|
|
||||||
|
ige (1, 4, 0);
|
||||||
|
ige (3, 3, 1);
|
||||||
|
ige (5, 2, 1);
|
||||||
|
|
||||||
|
if (failed) {
|
||||||
|
post_log ("Error in FPU math6 test\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_FPU */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,92 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* Author: Sergei Poselenov <sposelenov@emcraft.com>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPU test
|
||||||
|
*
|
||||||
|
* This test checks the arithmetic logic unit (ALU) of CPU.
|
||||||
|
* It tests independently various groups of instructions using
|
||||||
|
* run-time modification of the code to reduce the memory footprint.
|
||||||
|
* For more details refer to post/cpu/ *.c files.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_FPU
|
||||||
|
|
||||||
|
#include <watchdog.h>
|
||||||
|
|
||||||
|
extern int fpu_status (void);
|
||||||
|
extern void fpu_enable (void);
|
||||||
|
extern void fpu_disable (void);
|
||||||
|
|
||||||
|
extern int fpu_post_test_math1 (void);
|
||||||
|
extern int fpu_post_test_math2 (void);
|
||||||
|
extern int fpu_post_test_math3 (void);
|
||||||
|
extern int fpu_post_test_math4 (void);
|
||||||
|
extern int fpu_post_test_math5 (void);
|
||||||
|
extern int fpu_post_test_math6 (void);
|
||||||
|
extern int fpu_post_test_math7 (void);
|
||||||
|
|
||||||
|
int fpu_post_test (int flags)
|
||||||
|
{
|
||||||
|
int fpu = fpu_status ();
|
||||||
|
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
WATCHDOG_RESET ();
|
||||||
|
|
||||||
|
if (!fpu)
|
||||||
|
fpu_enable ();
|
||||||
|
|
||||||
|
if (ret == 0)
|
||||||
|
ret = fpu_post_test_math1 ();
|
||||||
|
if (ret == 0)
|
||||||
|
ret = fpu_post_test_math2 ();
|
||||||
|
if (ret == 0)
|
||||||
|
ret = fpu_post_test_math3 ();
|
||||||
|
if (ret == 0)
|
||||||
|
ret = fpu_post_test_math4 ();
|
||||||
|
if (ret == 0)
|
||||||
|
ret = fpu_post_test_math5 ();
|
||||||
|
if (ret == 0)
|
||||||
|
ret = fpu_post_test_math6 ();
|
||||||
|
if (ret == 0)
|
||||||
|
ret = fpu_post_test_math7 ();
|
||||||
|
|
||||||
|
if (!fpu)
|
||||||
|
fpu_disable ();
|
||||||
|
|
||||||
|
WATCHDOG_RESET ();
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_FPU */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,103 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* This file is originally a part of the GCC testsuite.
|
||||||
|
* Check that certain subnormal numbers (formerly known as denormalized
|
||||||
|
* numbers) are rounded to within 0.5 ulp. PR other/14354.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#if CONFIG_POST & CFG_POST_FPU
|
||||||
|
|
||||||
|
union uf
|
||||||
|
{
|
||||||
|
unsigned int u;
|
||||||
|
float f;
|
||||||
|
};
|
||||||
|
|
||||||
|
static float
|
||||||
|
u2f (unsigned int v)
|
||||||
|
{
|
||||||
|
union uf u;
|
||||||
|
u.u = v;
|
||||||
|
return u.f;
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int
|
||||||
|
f2u (float v)
|
||||||
|
{
|
||||||
|
union uf u;
|
||||||
|
u.f = v;
|
||||||
|
return u.u;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ok = 1;
|
||||||
|
|
||||||
|
static void
|
||||||
|
tstmul (unsigned int ux, unsigned int uy, unsigned int ur)
|
||||||
|
{
|
||||||
|
float x = u2f (ux);
|
||||||
|
float y = u2f (uy);
|
||||||
|
|
||||||
|
if (f2u (x * y) != ur)
|
||||||
|
/* Set a variable rather than aborting here, to simplify tracing when
|
||||||
|
several computations are wrong. */
|
||||||
|
ok = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* We don't want to make this const and static, or else we risk inlining
|
||||||
|
causing the test to fold as constants at compile-time. */
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
unsigned int p1, p2, res;
|
||||||
|
} static volatile expected[] =
|
||||||
|
{
|
||||||
|
{0xfff, 0x3f800400, 0xfff},
|
||||||
|
{0xf, 0x3fc88888, 0x17},
|
||||||
|
{0xf, 0x3f844444, 0xf}
|
||||||
|
};
|
||||||
|
|
||||||
|
int fpu_post_test_math7 (void)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
for (i = 0; i < sizeof (expected) / sizeof (expected[0]); i++)
|
||||||
|
{
|
||||||
|
tstmul (expected[i].p1, expected[i].p2, expected[i].res);
|
||||||
|
tstmul (expected[i].p2, expected[i].p1, expected[i].res);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!ok) {
|
||||||
|
post_log ("Error in FPU math7 test\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST & CFG_POST_FPU */
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -21,10 +21,10 @@
|
||||||
# MA 02111-1307 USA
|
# MA 02111-1307 USA
|
||||||
#
|
#
|
||||||
|
|
||||||
BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX)
|
BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) ubsha1$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX)
|
||||||
|
|
||||||
OBJ_LINKS = environment.o crc32.o
|
OBJ_LINKS = environment.o crc32.o sha1.o
|
||||||
OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o
|
OBJ_FILES = img2srec.o mkimage.o envcrc.o ubsha1.o gen_eth_addr.o bmp_logo.o
|
||||||
|
|
||||||
ifeq ($(ARCH),mips)
|
ifeq ($(ARCH),mips)
|
||||||
BIN_FILES += inca-swap-bytes$(SFX)
|
BIN_FILES += inca-swap-bytes$(SFX)
|
||||||
|
@ -126,14 +126,17 @@ MAKEDEPEND = makedepend
|
||||||
|
|
||||||
all: $(obj).depend $(BINS) $(LOGO_H) subdirs
|
all: $(obj).depend $(BINS) $(LOGO_H) subdirs
|
||||||
|
|
||||||
$(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)environment.o
|
$(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)environment.o $(obj)sha1.o
|
||||||
|
$(CC) $(CFLAGS) -o $@ $^
|
||||||
|
|
||||||
|
$(obj)ubsha1$(SFX): $(obj)ubsha1.o $(obj)sha1.o
|
||||||
$(CC) $(CFLAGS) -o $@ $^
|
$(CC) $(CFLAGS) -o $@ $^
|
||||||
|
|
||||||
$(obj)img2srec$(SFX): $(obj)img2srec.o
|
$(obj)img2srec$(SFX): $(obj)img2srec.o
|
||||||
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
|
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
|
||||||
$(STRIP) $@
|
$(STRIP) $@
|
||||||
|
|
||||||
$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o
|
$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o $(obj)sha1.o
|
||||||
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
|
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
|
||||||
$(STRIP) $@
|
$(STRIP) $@
|
||||||
|
|
||||||
|
@ -160,9 +163,15 @@ $(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o
|
||||||
$(obj)envcrc.o: $(src)envcrc.c
|
$(obj)envcrc.o: $(src)envcrc.c
|
||||||
$(CC) -g $(CFLAGS) -c -o $@ $<
|
$(CC) -g $(CFLAGS) -c -o $@ $<
|
||||||
|
|
||||||
|
$(obj)ubsha1.o: $(src)ubsha1.c
|
||||||
|
$(CC) -g $(CFLAGS) -c -o $@ $<
|
||||||
|
|
||||||
$(obj)crc32.o: $(obj)crc32.c
|
$(obj)crc32.o: $(obj)crc32.c
|
||||||
$(CC) -g $(CFLAGS) -c -o $@ $<
|
$(CC) -g $(CFLAGS) -c -o $@ $<
|
||||||
|
|
||||||
|
$(obj)sha1.o: $(obj)sha1.c
|
||||||
|
$(CC) -g $(CFLAGS) -c -o $@ $<
|
||||||
|
|
||||||
$(obj)mkimage.o: $(src)mkimage.c
|
$(obj)mkimage.o: $(src)mkimage.c
|
||||||
$(CC) -g $(CFLAGS) -c -o $@ $<
|
$(CC) -g $(CFLAGS) -c -o $@ $<
|
||||||
|
|
||||||
|
@ -203,6 +212,10 @@ $(obj)crc32.c:
|
||||||
@rm -f $(obj)crc32.c
|
@rm -f $(obj)crc32.c
|
||||||
ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c
|
ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c
|
||||||
|
|
||||||
|
$(obj)sha1.c:
|
||||||
|
@rm -f $(obj)sha1.c
|
||||||
|
ln -s $(src)../lib_generic/sha1.c $(obj)sha1.c
|
||||||
|
|
||||||
$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP)
|
$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP)
|
||||||
$(obj)./bmp_logo $(LOGO_BMP) >$@
|
$(obj)./bmp_logo $(LOGO_BMP) >$@
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,118 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Heiko Schocher, DENX Software Engineering, <hs@denx.de>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <unistd.h>
|
||||||
|
#include <fcntl.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <sys/mman.h>
|
||||||
|
#include <sys/stat.h>
|
||||||
|
#include "sha1.h"
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
#define __ASSEMBLY__ /* Dirty trick to get only #defines */
|
||||||
|
#endif
|
||||||
|
#include <config.h>
|
||||||
|
#undef __ASSEMBLY__
|
||||||
|
|
||||||
|
#ifndef O_BINARY /* should be define'd on __WIN32__ */
|
||||||
|
#define O_BINARY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MAP_FAILED
|
||||||
|
#define MAP_FAILED (-1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern int errno;
|
||||||
|
|
||||||
|
extern void sha1_csum (unsigned char *input, int ilen, unsigned char output[20]);
|
||||||
|
|
||||||
|
int main (int argc, char **argv)
|
||||||
|
{
|
||||||
|
unsigned char output[20];
|
||||||
|
int i, len;
|
||||||
|
|
||||||
|
char *imagefile;
|
||||||
|
char *cmdname = *argv;
|
||||||
|
unsigned char *ptr;
|
||||||
|
unsigned char *data;
|
||||||
|
struct stat sbuf;
|
||||||
|
unsigned char *ptroff;
|
||||||
|
int ifd;
|
||||||
|
int off;
|
||||||
|
|
||||||
|
if (argc > 1) {
|
||||||
|
imagefile = argv[1];
|
||||||
|
ifd = open (imagefile, O_RDWR|O_BINARY);
|
||||||
|
if (ifd < 0) {
|
||||||
|
fprintf (stderr, "%s: Can't open %s: %s\n",
|
||||||
|
cmdname, imagefile, strerror(errno));
|
||||||
|
exit (EXIT_FAILURE);
|
||||||
|
}
|
||||||
|
if (fstat (ifd, &sbuf) < 0) {
|
||||||
|
fprintf (stderr, "%s: Can't stat %s: %s\n",
|
||||||
|
cmdname, imagefile, strerror(errno));
|
||||||
|
exit (EXIT_FAILURE);
|
||||||
|
}
|
||||||
|
len = sbuf.st_size;
|
||||||
|
ptr = (unsigned char *)mmap(0, len,
|
||||||
|
PROT_READ, MAP_SHARED, ifd, 0);
|
||||||
|
if (ptr == (unsigned char *)MAP_FAILED) {
|
||||||
|
fprintf (stderr, "%s: Can't read %s: %s\n",
|
||||||
|
cmdname, imagefile, strerror(errno));
|
||||||
|
exit (EXIT_FAILURE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* create a copy, so we can blank out the sha1 sum */
|
||||||
|
data = malloc (len);
|
||||||
|
memcpy (data, ptr, len);
|
||||||
|
off = SHA1_SUM_POS;
|
||||||
|
ptroff = &data[len + off];
|
||||||
|
for (i = 0; i < SHA1_SUM_LEN; i++) {
|
||||||
|
ptroff[i] = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
|
||||||
|
|
||||||
|
printf ("U-Boot sum:\n");
|
||||||
|
for (i = 0; i < 20 ; i++) {
|
||||||
|
printf ("%02X ", output[i]);
|
||||||
|
}
|
||||||
|
printf ("\n");
|
||||||
|
/* overwrite the sum in the bin file, with the actual */
|
||||||
|
lseek (ifd, SHA1_SUM_POS, SEEK_END);
|
||||||
|
if (write (ifd, output, SHA1_SUM_LEN) != SHA1_SUM_LEN) {
|
||||||
|
fprintf (stderr, "%s: Can't write %s: %s\n",
|
||||||
|
cmdname, imagefile, strerror(errno));
|
||||||
|
exit (EXIT_FAILURE);
|
||||||
|
}
|
||||||
|
|
||||||
|
free (data);
|
||||||
|
(void) munmap((void *)ptr, len);
|
||||||
|
(void) close (ifd);
|
||||||
|
}
|
||||||
|
|
||||||
|
return EXIT_SUCCESS;
|
||||||
|
}
|
Loading…
Reference in New Issue