diff --git a/CHANGELOG b/CHANGELOG index 7bd8615a5..4e07e734b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,145 @@ +commit f33e9653c9c09868995d788511d573771c209fe5 +Author: Anatolij Gustschin +Date: Fri Feb 15 00:13:20 2008 +0100 + + Fix compile warning on lib_ppc/board.c + + Signed-off-by: Anatolij Gustschin + +commit e5c6f9f8bec4dff9603419161e3a15cc8ad5d5f4 +Author: Anatolij Gustschin +Date: Thu Feb 14 18:22:04 2008 +0100 + + Add Radeon Mobility 9200 pci device id to the radeon driver + + This patch extends PCI device id table of the + radeon driver so that the driver will also support + Radeon Mobility 9200 (M9+) based boards. + + Signed-off-by: Anatolij Gustschin + +commit 1b8607e1f7143548c6062c28371449ec69588c00 +Author: Anatolij Gustschin +Date: Thu Feb 14 18:19:50 2008 +0100 + + Extend ATI Radeon driver to support more video modes + + Adds ATI Radeon 9200 support for 1280x1024, 1024x768, + 800x600, 640x480 at 24, 16 and 8 bpp. + + Signed-off-by: Anatolij Gustschin + +commit 4124382de029d361162a4b8cecc773eb8f26e2a8 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Feb 10 17:05:20 2008 +0100 + + xsengine: fix typo and few coding style + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 6f4abee789b6d9be3ec4b97ad48f509355559e9e +Author: Guennadi Liakhovetski +Date: Fri Feb 8 21:25:58 2008 +0100 + + Fix wrong memory limit calculation in memory-test + + If the length of the memory address range passed to the "mtest" command is + not of the form 2^x - 1, not all address lines are tested. This bug is + inherited from the original software at + http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C. Fix + this. + + Signed-off-by: Guennadi Liakhovetski + +commit 7e30f5eac7f07082a7ca77b7d91b944a8d0af6db +Author: Wolfgang Denk +Date: Fri Feb 15 00:11:39 2008 +0100 + + Coding STyle cleanup. + + Signed-off-by: Wolfgang Denk + +commit f6921e3dc331293c873ec4d109fd5517a42a90b3 +Author: Nobuhiro Iwamatsu +Date: Tue Feb 5 13:30:43 2008 +0900 + + sh: Fix register address of SH7722 + + The address of SH7722 is wrong by old document. + This patch fixes this problem. + + Signed-off-by: Nobuhiro Iwamatsu + +commit 0ec7a061fb1c277f6afd73d61dd71bd21e7ef7b2 +Author: Mike Frysinger +Date: Mon Feb 4 17:44:23 2008 -0500 + + only update version header as needed + + Constantly rebuilding the version header will force useless relinking, so we + simply need to compare the new header with the existing one before updating + it. + + Signed-off-by: Mike Frysinger + +commit 208447f8e953f347425eb92c8e28d59e6d911363 +Author: Mike Frysinger +Date: Mon Jan 28 05:56:19 2008 -0500 + + Do not specify a CROSS_COMPILE default when executing size + + Signed-off-by: Mike Frysinger + +commit 1f780aa6f17a5d79791d69ec1d2f66d76ac45d8e +Author: Guennadi Liakhovetski +Date: Wed Feb 13 11:19:19 2008 +0100 + + Fix return value of mtest when CFG_ALT_MEMTEST set + + Fix a missing return statement from a non-void function. + + Signed-off-by: Guennadi Liakhovetski + +commit 943afa229cf5bf70ef917c7eb6bd0db59a1ba602 +Author: Timur Tabi +Date: Wed Jan 9 14:35:26 2008 -0600 + + 85xx, 86xx: Determine I2C clock frequencies and store in global_data + + Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx. + + Update the get_clocks() function in 85xx and 86xx to determine the I2C + clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk. + + Signed-off-by: Timur Tabi + +commit b931b3a9c3bdfaaeaa71e57a6026eec726005b08 +Author: Wolfgang Denk +Date: Thu Feb 14 23:18:01 2008 +0100 + + TQM834x: clean up configuration + + Get board name consistent with Linux and elsewhere; + get rid of local network definitions etc. + + Signed-off-by: Wolfgang Denk + +commit 38cc09c55b1d7f233789052c6fc462e5377669a9 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu Feb 14 08:02:12 2008 +0100 + + TFTP: fix search of ':' in BootFile + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 0bc9efada170096c6b273f19165e32936d330d80 +Author: Wolfgang Denk +Date: Thu Feb 14 22:46:55 2008 +0100 + + Coding style cleanup; update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit e7670f6c1e52ae6d2a43ff75a8bcfa7a5c86e47b Author: Wolfgang Denk Date: Thu Feb 14 22:43:22 2008 +0100 @@ -94,6 +236,32 @@ Date: Tue Jan 15 12:52:31 2008 +0100 Signed-off-by: Rafal Jaworowski +commit 3f2ac8f928c76cbd2374437b2d079f8b4324aaba +Author: Jon Loeliger +Date: Wed Jan 23 15:55:02 2008 -0600 + + 86xx: Fix compilation warning in sys_eprom.c + + sys_eeprom.c:82:9: warning: unknown escape sequence '\/' + + Signed-off-by: Jon Loeliger + +commit b7f6193e76651e1fd606e46eb11915b53cb6618b +Author: Niklaus Giger +Date: Tue Feb 5 10:26:42 2008 +0100 + + ppc4xx: HCU4/5. Fix make O=../xx + + Signed-off-by: Niklaus Giger + +commit 29e3500cbc43c89eff6e720ca83e375deeecd9b3 +Author: Larry Johnson +Date: Tue Jan 22 08:51:59 2008 -0500 + + ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code + + Signed-off-by: Larry Johnson + commit fe891ecf4d187e9d11dde869ed4623af52b54451 Author: Hiroshi Ito Date: Thu Jan 31 18:35:04 2008 +0900 @@ -173,6 +341,16 @@ Date: Wed Feb 13 15:09:58 2008 -0600 Signed-off-by: Kumar Gala +commit ccd6e1464e5396bc1a9aebf7077ddf4342eafe03 +Author: Jon Loeliger +Date: Tue Feb 12 14:53:28 2008 -0600 + + Add CFG_MPC86xx_DDR_ADDR and CFG_MPC86xx_DDR2_ADDR symbols + + These replace direct structure references for IMMR sections. + + Signed-off-by: Jon Loeliger + commit c62776be8dca4097ca03d4f9415f08d4887b45d0 Author: Wolfgang Denk Date: Tue Feb 12 00:45:06 2008 +0100 @@ -262,6 +440,264 @@ Date: Sat Jan 12 23:35:33 2008 -0500 Signed-off-by: Larry Johnson +commit ed2cf548cac80cd3cf8154dcfe7b2685bef45938 +Author: Kumar Gala +Date: Thu Jan 17 08:25:45 2008 -0600 + + QE: Move FDT support into a common file + + Move the flat device tree setup for QE related devices into + a common file shared between 83xx & 85xx platforms that have QE's. + + Signed-off-by: Kumar Gala + +commit d38da537943cd36356b9d3d9d9b60533554b81d8 +Author: Haavard Skinnemoen +Date: Wed Jan 23 17:20:14 2008 +0100 + + AVR32: Make SDRAM refresh rate configurable + + The existing code assumes the SDRAM row refresh period should always + be 15.6 us. This is not always true, and indeed on the ATNGW100, the + refresh rate should really be 7.81 us. + + Add a refresh_period member to struct sdram_info and initialize it + properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will + panic() until the refresh_period member is updated properly. + + Big thanks to Gerhard Berghofer for pointing out this issue. + + Signed-off-by: Haavard Skinnemoen + +commit 61151cccb660cdb06a07fb283de6089913d7bde0 +Author: Haavard Skinnemoen +Date: Thu Apr 19 10:10:11 2007 +0200 + + ATSTK1000: Fix potential flash programming bug + + The (now obsolete) atngw100 flash programming code was having problems + programming the onboard at49bv642 chip. The atstk1000 flash + programming code may have the same bug, so import fix for this problem + from the AVR32 Linux BSP. + + Signed-off-by: Haavard Skinnemoen + +commit b2e1d5b64469f10dfcce27f7b0afd935684a8e11 +Author: Haavard Skinnemoen +Date: Thu Nov 22 17:04:13 2007 +0100 + + ATSTK1004: Fix comment about default load address + + The default load address is SDRAM + 2MB, not SDRAM + 4MB. The latter + wouldn't have worked anyway since the board can only access 4MB of + SDRAM. + + Signed-off-by: Haavard Skinnemoen + +commit 8269ab53608d8db2aa06969c337ab0b0518211e5 +Author: Haavard Skinnemoen +Date: Thu Nov 22 17:01:24 2007 +0100 + + ATSTK1002: Use SDRAM + 4MB as default load address + + Many people run into problems when they compile a big kernel and load + the uImage at the default SDRAM + 2MB address as the kernel will + overwrite the uImage as it is being unpacked. Increase the default + load address so that we can load a 4MB kernel image without any + problems. + + Signed-off-by: Haavard Skinnemoen + +commit 2bcacc2d841b77f3d2d3910db722003742727e9f +Author: Haavard Skinnemoen +Date: Thu Nov 22 16:51:39 2007 +0100 + + ATNGW100: Fix default mtest range + + Let mtest cover the whole SDRAM except the last megabyte, which is + where u-boot lives. + + Signed-off-by: Haavard Skinnemoen + +commit 9856a6b3104e0bc210b0868dfe691c52bf03c227 +Author: Nobuhiro Iwamatsu +Date: Tue Jan 22 15:31:56 2008 +0900 + + sh: Fix register address of SH7722. + + The address of SH7722 is wrong by old document. + This patch fixes this problem. + + Signed-off-by: Nobuhiro Iwamatsu + +commit 30942b18b66f35f2ceedab39af10e9eccaa943cc +Author: Mike Frysinger +Date: Mon Feb 4 19:26:57 2008 -0500 + + new command for displaying strings at specified memory locations + + Signed-off-by: Mike Frysinger + +commit b58d8b48e25b0c866d167cc577f118f528cd9e0a +Author: Mike Frysinger +Date: Mon Feb 4 19:26:57 2008 -0500 + + rewrite/cleanup Blackfin RTC driver + + Signed-off-by: Mike Frysinger + +commit 94a91e248b71c3ff951fc27cff6909e82ca37d15 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:57 2008 -0500 + + generate u-boot.ldr for Blackfin targets + + Signed-off-by: Mike Frysinger + +commit b779f7a59530436040f157f7841db7ab796542df +Author: Mike Frysinger +Date: Mon Feb 4 19:26:57 2008 -0500 + + scrub unused symbols + + Signed-off-by: Mike Frysinger + +commit cc2977acc3bbbb7850f16645dd1081f95335868d +Author: Mike Frysinger +Date: Mon Feb 4 19:26:57 2008 -0500 + + move Blackfin cpu object list to respective cpu directories + + Signed-off-by: Mike Frysinger + +commit d0b01a246d0a351bc7dce1d0c9cf6aebdf6d7505 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:57 2008 -0500 + + interface to Blackfin on-chip One-Time-Programmable memory + + Signed-off-by: Mike Frysinger + +commit 4c727c77e43872d3a1d1f76a949fcb3f26a38788 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:56 2008 -0500 + + add support for memory commands with Blackfin L1 instruction memory + + Signed-off-by: Mike Frysinger + +commit 6b9097e5e7490aa7b828c6f1a1c7a0e875df8464 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:56 2008 -0500 + + use C code rather than inline assembly + + Signed-off-by: Mike Frysinger + +commit 97c26e006d2fa6d4e1560933ee6f385d8b8908b9 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:56 2008 -0500 + + add Blackfin-specific reginfo command + + Signed-off-by: Mike Frysinger + +commit 0858b835e7ea501ea084d34cef75932f098342bb +Author: Mike Frysinger +Date: Mon Feb 4 19:26:55 2008 -0500 + + add support for Blackfin symbol prefixes to examples + + Signed-off-by: Mike Frysinger + +commit 8dc48d71a4be753ea9f84956cd33600de35fad04 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:55 2008 -0500 + + add Blackfin-specific bdinfo command + + Signed-off-by: Mike Frysinger + +commit 0003613e3c7df3b84b2cb92e797d77f46f15a43a +Author: Mike Frysinger +Date: Mon Feb 4 19:26:55 2008 -0500 + + move -ffixed-P5 to blackfin_config.mk and drop unused -D__BLACKFIN__ + + Signed-off-by: Mike Frysinger + +commit 60fa72d65610c7ef33e1d6db858979d05ff0df58 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:55 2008 -0500 + + unify the Blackfin board targets + + Signed-off-by: Mike Frysinger + +commit d4d7730853e5d675f76ec666807da3028c91d592 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:55 2008 -0500 + + punt Blackfin VDSP headers and import sanitized/auto-generated ones + + Signed-off-by: Mike Frysinger + +commit 6cfcce67671a3425229d66203386fa3cbd0cc3bd +Author: Mike Frysinger +Date: Mon Feb 4 19:26:54 2008 -0500 + + always pull in asm/blackfin.h for Blackfin ports + + Signed-off-by: Mike Frysinger + +commit bf53974c2ddae678d7660f2b5ccfeb0732b6f5dc +Author: Mike Frysinger +Date: Mon Feb 4 19:26:54 2008 -0500 + + add missing __raw versions of Blackfin read/write io functions + + Signed-off-by: Mike Frysinger + +commit 24e02d0fd3acc50e73e1a3cdd567f0a77946f15d +Author: Mike Frysinger +Date: Mon Feb 4 19:26:54 2008 -0500 + + add the default Blackfin logo used by Blackfin boards with splash screens + + Signed-off-by: Mike Frysinger + +commit 4c58eb5552220e425c8af6ac8d2839244a2f57b1 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:54 2008 -0500 + + add some more Blackfin docs + + Signed-off-by: Mike Frysinger + +commit 32a9f5f2160a034ea87ea651b233ef7c635e55cf +Author: Mike Frysinger +Date: Mon Feb 4 19:26:54 2008 -0500 + + make smc91111_eeprom managment simpler by depending on the board configuration file rather than a hardcoded list of boards + + Signed-off-by: Mike Frysinger + +commit 4087bc88cebec75c432a7fe9f6afb545b0919831 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:54 2008 -0500 + + fix building on Blackfin as the assembler supports the .set syntax, not the = syntax, for assigning symbols + + Signed-off-by: Mike Frysinger + +commit b45264ee85cbd92020640a32e02fb434fd557108 +Author: Mike Frysinger +Date: Mon Feb 4 19:26:53 2008 -0500 + + add gitignores for Blackfin pieces + + Signed-off-by: Mike Frysinger + commit a93907c43f847f076dd0e34ee3b69b5e8e6d0d29 Author: Jean-Christophe PLAGNIOL-VILLARD Date: Fri Jan 18 01:14:03 2008 +0100 @@ -274,6 +710,19 @@ Date: Fri Jan 18 01:14:03 2008 +0100 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +commit e56b4b494cd92def577969f9678395aa22d34c9f +Author: Timur Tabi +Date: Wed Jan 9 14:35:26 2008 -0600 + + 85xx,86xx: Determine I2C clock frequencies and store in global_data + + Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx. + + Update the get_clocks() function in 85xx and 86xx to determine the I2C + clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk. + + Signed-off-by: Timur Tabi + commit 7ec8bb15ee368ea54d48d64867767a704d9ab4c2 Author: Wolfgang Denk Date: Thu Dec 27 10:56:54 2007 +0100 @@ -359,6 +808,41 @@ Date: Tue Dec 18 16:00:54 2007 -0800 Signed-off-by: K R Gururaja Hebbar +commit ff02f139804f3cb61414f7bbcbfdaa0279e3efae +Author: Stefan Roese +Date: Fri Feb 1 09:38:29 2008 +0100 + + ppc4xx: Fix ndfc HW ECC byte order + + The current ndfc HW ECC implementation swaps the first two ECC bytes. + But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering, + so this swapping in the HW ECC driver is bogus. This patch fixes this + problem and now really uses the SMC ECC byte order. + + Thanks to Sean MacLennan for pointing this out. + + Signed-off-by: Stefan Roese + +commit e1d1429b49b0ee58c80f8c7b29c1ebaf8be7f5f1 +Author: Stefan Roese +Date: Wed Jan 30 15:35:50 2008 +0100 + + ppc4xx: Fix GPIO configuration for pcs440ep + + The SRD0_PFC0 register was not configured correctly to enable the GPIO's + 49-63 for GPIO. They have been configured as trace signals. This patch + fixes this by clearing the corresponding bit. + + Signed-off-by: Stefan Roese + +commit 28d77d968bfe0316deb5bf15c17f57d5ff2c8821 +Author: Stefan Roese +Date: Wed Jan 30 14:48:28 2008 +0100 + + ppc4xx: Fix problem with init-ram bigger than 4k on 440 platforms + + Signed-off-by: Stefan Roese + commit 4fedfddf97461b88668b9aec774dfb7a0c6dc368 Author: Ladislav Michl Date: Fri Dec 7 00:42:32 2007 +0100 @@ -486,6 +970,79 @@ Date: Fri Jan 25 09:56:17 2008 +0100 Signed-off-by: Wolfgang Denk +commit 4f93f8b1a4d35b6d302842132edba920ef8f62aa +Author: Becky Bruce +Date: Wed Jan 23 16:31:06 2008 -0600 + + 86xx: Add reginfo command + + Signed-off-by: Becky Bruce + +commit ddcebcb638715a6278da93b553d5016f99823816 +Author: Becky Bruce +Date: Wed Jan 23 16:31:05 2008 -0600 + + 86xx: Add print_laws function to fsl_law.c + + This can be used for debug, and will be used by board code + to help implement reginfo. + + Signed-off-by: Becky Bruce + +commit 9cd32426f26a0567bb61f339edd83c6a2ce9bfc3 +Author: Becky Bruce +Date: Wed Jan 23 16:31:04 2008 -0600 + + 86xx: Remove old-style law setup code + + This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d. + + Signed-off-by: Becky Bruce + +commit 713d8186649dae874613d495b0cecaa039a98b30 +Author: Becky Bruce +Date: Wed Jan 23 16:31:03 2008 -0600 + + 86xx: Convert sbc8641d to use new law setup code. + + Signed-off-by: Becky Bruce + +commit 031976f6364b93833e989f57e9f1e023e0be8c4c +Author: Becky Bruce +Date: Wed Jan 23 16:31:02 2008 -0600 + + 86xx: Convert mpc8610hpcd to new law setup method. + + Signed-off-by: Becky Bruce + +commit 4933b91f8a49e436681f163df3173beb91cac44a +Author: Becky Bruce +Date: Wed Jan 23 16:31:01 2008 -0600 + + 86xx: Support new law setup method and convert mpc8641 + + Adds the support code in cpu/mpc86xx for the new law setup code + recently created fsl_law.c, and changes the MPC8641HPCN config + to use this code. + + Signed-off-by: Becky Bruce + +commit 1a41f7ce9c086e208c0eabf52565a237af2a2bd1 +Author: Becky Bruce +Date: Wed Jan 23 16:31:00 2008 -0600 + + 86xx: Rearrange the sequence in start.S + + * split the BAT initialization so that only 2 BATs (for the boot page + and stack) are programmed very early on. The rest are initialized later. + * Move other BAT setup, ccsrbar setup, and law setup later in the code + after translation has been enabled. + + These changes will facilitate the moving of law and BAT initialization + to C code, and will aid with 36-bit physical addressing support. + + Signed-off-by: Becky Bruce + commit 33dac03b1b5d61e4fed7bad445ba40b4c97feba0 Author: Wolfgang Denk Date: Wed Jan 23 14:41:37 2008 +0100 diff --git a/Makefile b/Makefile index 38ade5010..9512b71ee 100644 --- a/Makefile +++ b/Makefile @@ -23,8 +23,8 @@ VERSION = 1 PATCHLEVEL = 3 -SUBLEVEL = 1 -EXTRAVERSION = +SUBLEVEL = 2 +EXTRAVERSION = -rc1 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) VERSION_FILE = $(obj)include/version_autogenerated.h diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 000107f72..ed91f2704 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -700,7 +700,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int rcode = 0; #if defined(CFG_ALT_MEMTEST) - vu_long addr_mask; + vu_long len; vu_long offset; vu_long test_offset; vu_long pattern; @@ -836,26 +836,19 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * all possible. * * Returns: 0 if the test succeeds, 1 if the test fails. - * - * ## NOTE ## Be sure to specify start and end - * addresses such that addr_mask has - * lots of bits set. For example an - * address range of 01000000 02000000 is - * bad while a range of 01000000 - * 01ffffff is perfect. */ - addr_mask = ((ulong)end - (ulong)start)/sizeof(vu_long); + len = ((ulong)end - (ulong)start)/sizeof(vu_long); pattern = (vu_long) 0xaaaaaaaa; anti_pattern = (vu_long) 0x55555555; - PRINTF("%s:%d: addr mask = 0x%.8lx\n", + PRINTF("%s:%d: length = 0x%.8lx\n", __FUNCTION__, __LINE__, - addr_mask); + len); /* * Write the default pattern at each of the * power-of-two offsets. */ - for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { + for (offset = 1; offset < len; offset <<= 1) { start[offset] = pattern; } @@ -865,7 +858,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) test_offset = 0; start[test_offset] = anti_pattern; - for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { + for (offset = 1; offset < len; offset <<= 1) { temp = start[offset]; if (temp != pattern) { printf ("\nFAILURE: Address bit stuck high @ 0x%.8lx:" @@ -879,10 +872,10 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Check for addr bits stuck low or shorted. */ - for (test_offset = 1; (test_offset & addr_mask) != 0; test_offset <<= 1) { + for (test_offset = 1; test_offset < len; test_offset <<= 1) { start[test_offset] = anti_pattern; - for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { + for (offset = 1; offset < len; offset <<= 1) { temp = start[offset]; if ((temp != pattern) && (offset != test_offset)) { printf ("\nFAILURE: Address bit stuck low or shorted @" diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c index 0bdaa1c04..a1e7baec1 100644 --- a/drivers/video/ati_radeon_fb.c +++ b/drivers/video/ati_radeon_fb.c @@ -44,6 +44,7 @@ #include #include #include +#include "videomodes.h" #include #include "ati_ids.h" @@ -65,11 +66,27 @@ #define MAX_MAPPED_VRAM (2048*2048*4) #define MIN_MAPPED_VRAM (1024*768*1) +#define RADEON_BUFFER_ALIGN 0x00000fff +#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ + & ~RADEON_BUFFER_ALIGN) - 1) +#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ + ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) + +#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ + (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) +#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ + (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) +#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ + ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) +#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ + ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) + /*#define PCI_VENDOR_ID_ATI*/ #define PCI_CHIP_RV280_5960 0x5960 #define PCI_CHIP_RV280_5961 0x5961 #define PCI_CHIP_RV280_5962 0x5962 #define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5C63 0x5C63 #define PCI_CHIP_RV370_5B60 0x5B60 #define PCI_CHIP_RV380_5657 0x5657 #define PCI_CHIP_R420_554d 0x554d @@ -79,6 +96,7 @@ static struct pci_device_id ati_radeon_pci_ids[] = { {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63}, {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, @@ -90,6 +108,7 @@ static u16 ati_radeon_id_family_table[][2] = { {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280}, {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, @@ -350,6 +369,204 @@ void radeon_setmode(void) radeon_write_pll_regs(rinfo, mode); } +static void set_pal(void) +{ + int idx, val = 0; + + for (idx = 0; idx < 256; idx++) { + OUTREG8(PALETTE_INDEX, idx); + OUTREG(PALETTE_DATA, val); + val += 0x00010101; + } +} + +void radeon_setmode_9200(int vesa_idx, int bpp) +{ + struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); + + mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; + mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; + mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; + mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; + + switch (bpp) { + case 24: + mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ +#if defined(__BIG_ENDIAN) + mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; + mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; +#endif + break; + case 16: + mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ +#if defined(__BIG_ENDIAN) + mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; + mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; +#endif + break; + default: + mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ + mode->surface_cntl = 0x00000000; + break; + } + + switch (vesa_idx) { + case RES_MODE_1280x1024: + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); + mode->ppll_div_3 = 0x00010078; +#else /* default @ 60 Hz */ + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); + mode->ppll_div_3 = 0x00010060; +#endif + /* + * for this mode pitch expands to the same value for 32, 16 and 8 bpp, + * so we set it here once only. + */ + mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); + break; + default: /* 8 bpp */ + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); + break; + } + break; + case RES_MODE_1024x768: +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); + mode->ppll_div_3 = 0x0002008c; +#else /* @ 60 Hz */ + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00020074; +#endif + /* also same pitch value for 32, 16 and 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); + break; + default: /* 8 bpp */ + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); + break; + } + break; + case RES_MODE_800x600: + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); + mode->ppll_div_3 = 0x000300b0; +#else /* @ 60 Hz */ + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); + mode->ppll_div_3 = 0x0003008e; +#endif + switch (bpp) { + case 24: + mode->crtc_pitch = RADEON_CRT_PITCH(832,32); + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); + break; + case 16: + mode->crtc_pitch = RADEON_CRT_PITCH(896,16); + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); + break; + default: /* 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); + break; + } + break; + default: /* RES_MODE_640x480 */ +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00030070; +#else /* @ 60 Hz */ + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00030059; +#endif + /* also same pitch value for 32, 16 and 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(640,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); + break; + default: /* 8 bpp */ + mode->crtc_offset_cntl = 0x00000000; + break; + } + break; + } + + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); + OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); + OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); + OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); + OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); + OUTREG(CRTC_OFFSET, 0); + OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); + OUTREG(CRTC_PITCH, mode->crtc_pitch); + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); + + mode->clk_cntl_index = 0x300; + mode->ppll_ref_div = 0xc; + + radeon_write_pll_regs(rinfo, mode); + + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREG(SURFACE0_INFO, mode->surf_info[0]); + OUTREG(SURFACE0_LOWER_BOUND, 0); + OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); + OUTREG(SURFACE_CNTL, mode->surface_cntl); + + if (bpp > 8) + set_pal(); + + free(mode); +} + #include "../bios_emulator/include/biosemu.h" extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp); @@ -421,29 +638,101 @@ GraphicDevice ctfb; void *video_hw_init(void) { GraphicDevice *pGD = (GraphicDevice *) & ctfb; - int i; u32 *vm; + char *penv; + unsigned long t1, hsynch, vsynch; + int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; rinfo = malloc(sizeof(struct radeonfb_info)); + printf("Video: "); if(radeon_probe(rinfo)) { printf("No radeon video card found!\n"); return NULL; } + tmp = 0; + + videomode = CFG_DEFAULT_VIDEO_MODE; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE); + i = 0; + } + res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + vesa_idx = vesa_modes[i].resindex; + } else { + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + /* fill in Graphic device struct */ - sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640, - 480, 16, (1000 / 1000), - (2000 / 1000)); + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; - pGD->winSizeX = 640; - pGD->winSizeY = 480; - pGD->plnSizeX = 640; - pGD->plnSizeY = 480; - - pGD->gdfBytesPP = 1; - pGD->gdfIndex = GDF__8BIT_INDEX; + switch (bits_per_pixel) { + case 24: + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + if (res_mode->xres == 800) { + pGD->winSizeX = 832; + pGD->plnSizeX = 832; + } + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + if (res_mode->xres == 800) { + pGD->winSizeX = 896; + pGD->plnSizeX = 896; + } + break; + default: + if (res_mode->xres == 800) { + pGD->winSizeX = 1024; + pGD->plnSizeX = 1024; + } + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + } pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; pGD->pciBase = rinfo->fb_base_phys; @@ -464,14 +753,17 @@ void *video_hw_init(void) pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ /* set up Hardware */ - /* Clear video memory */ - i = pGD->memSize / 4; + /* Clear video memory (only visible screen area) */ + i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; vm = (unsigned int *) pGD->pciBase; while (i--) *vm++ = 0; /*SetDrawingEngine (bits_per_pixel);*/ - radeon_setmode(); + if (rinfo->family == CHIP_FAMILY_RV280) + radeon_setmode_9200(vesa_idx, bits_per_pixel); + else + radeon_setmode(); return ((void *) pGD); } diff --git a/include/common.h b/include/common.h index 93e3f7a06..cd8aad090 100644 --- a/include/common.h +++ b/include/common.h @@ -391,7 +391,7 @@ void icache_disable(void); int dcache_status (void); void dcache_enable (void); void dcache_disable(void); -void relocate_code (ulong, gd_t *, ulong); +void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index d167e0174..4d1bdd7b1 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -33,7 +33,7 @@ #define CONFIG_XSENGINE 1 #define CONFIG_MMC 1 #define CONFIG_DOS_PARTITION 1 -#define OARD_LATE_INIT 1 +#define BOARD_LATE_INIT 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ @@ -86,8 +86,8 @@ #define CFG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */ /* Size of malloc() pool */ #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) @@ -96,7 +96,7 @@ /* Hardware drivers */ #define CONFIG_DRIVER_SMC91111 #define CONFIG_SMC91111_BASE 0x04000300 -#define CONFIG_SMC_USE_32_BIT 1 +#define CONFIG_SMC_USE_32_BIT 1 /* select serial console configuration */ #define CONFIG_FFUART 1 @@ -138,15 +138,15 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0xA0400000 /* memtest works on */ #define CFG_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ #define CFG_MMC_BASE 0xF0000000 -#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */ +#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */ /* Stack sizes - The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ @@ -168,7 +168,7 @@ /* GP direction register */ #define CFG_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ #define CFG_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */ -#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */ +#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */ /* GP rising edge detect register */ #define CFG_GRER0_VAL 0x00000000 @@ -185,7 +185,7 @@ #define CFG_GAFR0_U_VAL 0x00000010 /* RDY */ #define CFG_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */ #define CFG_GAFR1_U_VAL 0x00000008 /* nPWE */ -#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */ +#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */ #define CFG_GAFR2_U_VAL 0x00000000 #define CFG_PSSR_VAL 0x00000020 /* Power manager sleep status */ diff --git a/include/radeon.h b/include/radeon.h index 3d11b0572..35875f177 100644 --- a/include/radeon.h +++ b/include/radeon.h @@ -154,8 +154,10 @@ #define PALETTE_30_DATA 0x00B8 #define CRTC_H_TOTAL_DISP 0x0200 #define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_H_SYNC_POL (1 << 23) #define CRTC_V_TOTAL_DISP 0x0208 #define CRTC_V_SYNC_STRT_WID 0x020C +#define CRTC_V_SYNC_POL (1 << 23) #define CRTC_VLINE_CRNT_VLINE 0x0210 #define CRTC_CRNT_FRAME 0x0214 #define CRTC_GUI_TRIG_VLINE 0x0218 @@ -749,6 +751,8 @@ #define NONSURF_AP1_SWP_16BPP (1 << 22) #define NONSURF_AP1_SWP_32BPP (1 << 23) +#define R200_SURF_TILE_COLOR_MACRO (1 << 16) + /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)