Blackfin: bf561-acvilon: new board port
Signed-off-by: Valentin Yakovenkov <yakovenkov@niistt.ru> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Valentin Yakovenkov
Mike Frysinger
parent
16ada4f66f
commit
446707c90f
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@ -978,6 +978,11 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
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IBF-DSP561 BF561
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Valentin Yakovenkov <yakovenkov@niistt.ru>
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Anton Shurpin <shurpin.aa@niistt.ru>
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BF561-ACVILON BF561
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#########################################################################
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# End of MAINTAINERS list #
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#########################################################################
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1
MAKEALL
1
MAKEALL
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@ -879,6 +879,7 @@ LIST_blackfin=" \
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bf537-stamp \
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bf538f-ezkit \
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bf548-ezkit \
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bf561-acvilon \
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bf561-ezkit \
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blackstamp \
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cm-bf527 \
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2
Makefile
2
Makefile
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@ -3531,7 +3531,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
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BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 tcm-bf537
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# Misc third party boards
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BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp
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BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp
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# I-SYST Micromodule
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BFIN_BOARDS += ibf-dsp561
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@ -0,0 +1,56 @@
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2007 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,58 @@
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/*
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* File: board/bf561-acvilon/bf561-acvilon.c
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* Based on: board/bf561-ezkit/bf561-ezkit.c
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* Author:
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*
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* Created: 2009-06-23
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* Description: Acvilon System On Module board file
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*
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* Modified:
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* Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Bugs:
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <common.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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printf("Board: CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n");
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printf(" Support: http://www.niistt.ru/\n");
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
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return gd->bd->bi_memsize;
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}
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#ifdef CONFIG_SMC911X
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int board_eth_init(bd_t *bis)
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{
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return smc911x_initialize(0, CONFIG_SMC911X_BASE);
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}
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#endif
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@ -0,0 +1,34 @@
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# This is not actually used for Blackfin boards so do not change it
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#TEXT_BASE = do-not-use-me
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CFLAGS_lib_generic += -O2
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CFLAGS_lzma += -O2
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# Set some default LDR flags based on boot mode.
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LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
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LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
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@ -0,0 +1,178 @@
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/*
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* U-boot - Configuration file for BF561 Acvilon System On Module
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* For more information please go to http://www.niistt.ru/
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*/
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#ifndef __CONFIG_BF561_ACVILON_H__
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#define __CONFIG_BF561_ACVILON_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf561-0.5
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 12000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 50
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 10
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#define CONFIG_MEM_SIZE 128
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#define CONFIG_EBIU_SDRRC_VAL 0x300
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#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189
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#define CONFIG_EBIU_AMGCTL_VAL 0x4e
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#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
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#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
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/*
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* RTC Settings
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*/
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_I2C_DTT_ADDR 0x49
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/*#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3*/
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/*
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* Network Settings
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*/
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_NET_MULTI
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DTT
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_SMC911X 1
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#define CONFIG_SMC911X_32_BIT
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/* #define CONFIG_SMC911X_16_BIT */
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#define CONFIG_SMC911X_BASE 0x28000000
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#endif /* (CONFIG_CMD_NET) */
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#define CONFIG_HOSTNAME bf561-acvilon
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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/*
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* Flash Settings
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*/
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#define CONFIG_SYS_NO_FLASH
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/*
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* I2C Settings
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*/
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#define CONFIG_HARD_I2C
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/* Use 300kHz speed by default */
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#define CONFIG_SYS_I2C_SPEED 0x00
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#define CONFIG_PCA9564_I2C
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#define CONFIG_PCA9564_BASE 0x2c000000
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_ATMEL
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/*
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* Env Storage Settings
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*/
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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/* #define CONFIG_CMD_SAVEENV */
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#define CONFIG_ENV_SECT_SIZE (1056 * 8)
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#define CONFIG_ENV_OFFSET ((16 + 256) * 1056)
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#define CONFIG_ENV_SIZE (8 * 1056)
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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/*
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* NAND Settings
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* We're using NAND_PLAT driver to make things simplier
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*/
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#define CONFIG_NAND_PLAT
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BASE 0x24000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
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#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
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#define BFIN_NAND_READY PF10
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#define BFIN_NAND_WRITE(addr, cmd) \
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do { \
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bfin_write8(addr, cmd); \
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SSYNC(); \
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} while (0)
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#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
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#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
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#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY)
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#define NAND_PLAT_INIT() \
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do { \
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bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \
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bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \
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} while (0)
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/*
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* Misc Settings
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*/
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_BAUDRATE 57600
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#define CONFIG_SYS_PROMPT "Acvilon> "
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif /* __CONFIG_BF561_ACVILON_H__ */
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