[PATCH] Clean up 40EZ/Acadia support

This patch cleans up all the open issue of the preliminary
Acadia support.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-03-24 15:45:34 +01:00
parent 16c0cc1c82
commit 3cb86f3e40
11 changed files with 450 additions and 1917 deletions

View File

@ -26,9 +26,6 @@
extern void board_pll_init_f(void);
/* Some specific Acadia Defines */
#define CPLD_BASE 0x80000000
void liveoak_gpio_init(void)
{
/*
@ -54,62 +51,12 @@ void liveoak_gpio_init(void)
out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
}
#if 0 /* test-only: not called at all??? */
void ext_bus_cntlr_init(void)
{
#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
mtebc(pb4ap, EBC_PB4AP);
mtebc(pb4cr, EBC_PB4CR);
#endif
}
#endif
int board_early_init_f(void)
{
unsigned int reg;
#if 0 /* test-only */
/*
* If CRAM memory and SPI/NAND boot, and if the CRAM memory is
* already initialized by the pre-loader then we can't reinitialize
* CPR registers, GPIO registers and EBC registers as this will
* have the effect of un-initializing CRAM.
*/
spr_reg = (volatile unsigned long) mfspr(SPRG7);
if (spr_reg != LOAK_CRAM) { /* != CRAM */
board_pll_init_f();
liveoak_gpio_init();
ext_bus_cntlr_init();
mtebc(pb1ap, CFG_EBC_PB1AP);
mtebc(pb1cr, CFG_EBC_PB1CR);
mtebc(pb2ap, CFG_EBC_PB2AP);
mtebc(pb2cr, CFG_EBC_PB2CR);
}
#else
board_pll_init_f();
liveoak_gpio_init();
/* ext_bus_cntlr_init(); */
#endif
#if 0 /* test-only (orig) */
/*
* If we boot from NAND Flash, we are running in
* RAM, so disable the EBC_CS0 so that it goes back
* to the NOR Flash. It will be enabled later
* for the NAND Flash on EBC_CS1
*/
mfsdr(sdrultra0, reg);
mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
#endif
#if 0 /* test-only */
/* configure for NAND */
mfsdr(sdrultra0, reg);
reg &= ~SDR_ULTRA0_CSN_MASK;
reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS;
mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
#endif
/* USB Host core needs this bit set */
mfsdr(sdrultra1, reg);
@ -128,7 +75,7 @@ int board_early_init_f(void)
int misc_init_f(void)
{
/* Set EPLD to take PHY out of reset */
out8(CPLD_BASE + 0x05, 0x00);
out8(CFG_CPLD_BASE + 0x05, 0x00);
udelay(100000);
return 0;

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@ -1,5 +1,5 @@
#
# (C) Copyright 2000
# (C) Copyright 2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -27,15 +27,6 @@ ifndef TEXT_BASE
TEXT_BASE = 0xFFFC0000
endif
ifeq ($(CONFIG_NAND_U_BOOT),y)
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
ifeq ($(CONFIG_SPI_U_BOOT),y)
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds
PAD_TO = 0x00840000
endif
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

View File

@ -76,19 +76,19 @@ void board_pll_init_f(void)
* | UART0 | 28.57 | 7 (0x07)|
* | UART1 | 28.57 | 7 (0x07)|
* | DAC | 28.57 | 7 (0xA7)|
* | ADC | 4 | 50 (0x32)|
* | ADC | 4 | 50 (0x32)|
* | PWM | 28.57 | 7 (0x07)|
* | EMAC | 4 | 50 (0x32)|
* -----------------------------------
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x20000238);
mtcpr(cprplld, 0x03010400);
mtcpr(cprpllc, 0x20000238);
mtcpr(cprplld, 0x03010400);
mtcpr(cprprimad, 0x03050a0a);
mtcpr(cprperc0, 0x00000000);
mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0x07323200);
mtcpr(cprperc0, 0x00000000);
mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0x07323200);
mtcpr(cprclkupd, 0x40000000);
}
@ -117,11 +117,11 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033C);
mtcpr(cprplld, 0x0a010000);
mtcpr(cprpllc, 0x0000033C);
mtcpr(cprplld, 0x0a010000);
mtcpr(cprprimad, 0x02040808);
mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xA6A60300);
mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xA6A60300);
mtcpr(cprclkupd, 0x40000000);
}
@ -143,20 +143,20 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x000003BC);
mtcpr(cprplld, 0x06060600);
mtcpr(cprpllc, 0x000003BC);
mtcpr(cprplld, 0x06060600);
mtcpr(cprprimad, 0x02020004);
mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xC8C81600);
mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xC8C81600);
mtcpr(cprclkupd, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
#endif /* CPU_<speed>_405EZ */
#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk (void)
unsigned long get_tbclk(void)
{
unsigned long cpr_plld;
unsigned long cpr_primad;
@ -184,12 +184,12 @@ unsigned long get_tbclk (void)
/*
* Determine FBK_DIV.
*/
pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
if (pllFbkDiv == 0)
pllFbkDiv = 256;
pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
if (pllFbkDiv == 0)
pllFbkDiv = 256;
freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
return (freqProcessor);
}
#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */

File diff suppressed because it is too large Load Diff

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@ -21,541 +21,80 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#define CRAM_BANK0_BASE 0x0
#define CRAM_DIDR 0x00100000
#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43
#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343
#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */
#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */
#define CRAM_DEVID_NOT_SUPPORTED 0x00000000
#define PSRAM_PASS 0x50415353 /* "PASS" */
#define PSRAM_FAIL 0x4641494C /* "FAIL" */
static u32 is_cram_inited(void);
static u32 is_cram(void);
static long int cram_init(u32);
static void cram_bcr_write(u32);
void udelay (unsigned long);
void sdram_init(void)
{
volatile unsigned long spr_reg;
/*
* If CRAM not initialized or CRAM looks initialized because this
* is after a warm reboot then set SPRG7 to indicate CRAM needs
* initialization. Note that CRAM is initialized by the SPI and
* NAND preloader.
*/
spr_reg = (volatile unsigned long) mfspr(SPRG6);
if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
mtspr(SPRG7, LOAK_NONE); /* "NONE" */
}
#if 1
/*
* When running the NAND SPL, the normal EBC configuration is not
* done, so We need to enable EPLD access on EBC_CS_2 and the memory
* on EBC_CS_3
*/
/* Enable CPLD - Needed for PSRAM Access */
/* Init SDRAM by setting EBC Bank 3 for PSRAM */
mtebc(pb1ap, CFG_EBC_PB1AP);
mtebc(pb1cr, CFG_EBC_PB1CR);
mtebc(pb2ap, CFG_EBC_PB2AP);
mtebc(pb2cr, CFG_EBC_PB2CR);
/* pre-boot loader code: we are in OCM */
mtspr(SPRG6, LOAK_SPL); /* "SPL " */
mtspr(SPRG7, LOAK_OCM); /* "OCM " */
/* define DEBUG for debugging output (obviously ;-)) */
#if 0
#define DEBUG
#endif
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
static void cram_bcr_write(u32 wr_val)
{
u32 tmp_reg;
u32 val;
volatile u32 gpio_reg;
wr_val <<= 2;
/* # Program CRAM write */
/* set CRAM_CRE to 1 */
gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
/*
* set CRAM_CRE = 0x1
* set wr_val = wr_val << 2
*/
gpio_reg = in32(GPIO1_OR);
out32(GPIO1_OR, gpio_reg | 0x00000400);
wr_val = wr_val << 2;
/* wr_val = 0x1c048; */
/* Write BCR to CRAM on CS1 */
out32(wr_val + 0x00200000, 0);
debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
/* Write BCR to CRAM on CS2 */
out32(wr_val + 0x02200000, 0);
debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
/*
* # stop PLL clock before programming CRAM
* set EPLD0_MUX_CTL.OESPR3 = 1
* delay 2
*/
sync();
eieio();
/* set CRAM_CRE back to 0 (normal operation) */
gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
/*
* # CS1
* read 0x00200000
* #shift 2 bit left before write
* set val = wr_val + 0x00200000
* write dmem val 0
* read 0x00200000 val
* print val/8x
*/
tmp_reg = in32(0x00200000);
val = wr_val + 0x00200000;
/* val = 0x0021c048; */
out32(val, 0x0000);
udelay(100000);
val = in32(0x00200000);
debug("CRAM VAL: %x for CS1 ", val);
/*
* # CS2
* read 0x02200000
* #shift 2 bit left before write
* set val = wr_val + 0x02200000
* write dmem val 0
* read 0x02200000 val
* print val/8x
*/
tmp_reg = in32(0x02200000);
val = wr_val + 0x02200000;
/* val = 0x0221c048; */
out32(val, 0x0000);
udelay(100000);
val = in32(0x02200000);
debug("CRAM VAL: %x for CS2 ", val);
/*
* # Start PLL clock before programming CRAM
* set EPLD0_MUX_CTL.OESPR3 = 0
*/
/*
* set CRAMCR = 0x1
*/
gpio_reg = in32(GPIO1_OR);
out32(GPIO1_OR, gpio_reg | 0x00000400);
/*
* # read CRAM config BCR ( bit19:18 = 10b )
* #read 0x00200000
* # 1001_1001_0001_1111 ( 991f ) =>
* #10_0110_0100_0111_1100 => 2647c => 0022647c
* #0011_0010_0011_1110 (323e)
* #
*/
/*
* set EPLD0_MUX_CTL.CRAMCR = 0x0
*/
gpio_reg = in32(GPIO1_OR);
out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF);
return;
}
static u32 is_cram_inited()
{
volatile unsigned long spr_reg;
/*
* If CRAM is initialized already, then don't reinitialize it again.
* In the case of NAND boot and SPI boot, CRAM will already be
* initialized by the pre-loader
*/
spr_reg = (volatile unsigned long) mfspr(SPRG7);
if (spr_reg == LOAK_CRAM) {
return 1;
} else {
return 0;
}
}
/******
* return 0 if not CRAM
* return 1 if CRAM and it's already inited by preloader
* else return cram_id (CRAM Device Identification Register)
******/
static u32 is_cram(void)
{
u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
volatile u32 gpio_reg;
volatile u32 cram_id = 0;
if (is_cram_inited() == 1) {
/* this is CRAM and it is already inited (by preloader) */
cram_id = 1;
} else {
/*
* # CRAM CLOCK
* set GPIO0_TCR.G8 = 1
* set GPIO0_OSRL.G8 = 0
* set GPIO0_OR.G8 = 0
*/
gpio_reg = in32(GPIO0_TCR);
gpio_TCR = gpio_reg;
out32(GPIO0_TCR, gpio_reg | 0x00800000);
gpio_reg = in32(GPIO0_OSRL);
gpio_OSRL = gpio_reg;
out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
gpio_reg = in32(GPIO0_OR);
gpio_OR = gpio_reg;
out32(GPIO0_OR, gpio_reg & 0xff7fffff);
/*
* # CRAM Addreaa Valid
* set GPIO0_TCR.G10 = 1
* set GPIO0_OSRL.G10 = 0
* set GPIO0_OR.G10 = 0
*/
gpio_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, gpio_reg | 0x00200000);
gpio_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
gpio_reg = in32(GPIO0_OR);
out32(GPIO0_OR, gpio_reg & 0xffdfffff);
/*
* # config input (EBC_WAIT)
* set GPIO0_ISR1L.G9 = 1
* set GPIO0_TCR.G9 = 0
*/
gpio_reg = in32(GPIO0_ISR1L);
gpio_ISR1L = gpio_reg;
out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
gpio_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
/*
* Enable CRE to read Registers
* set GPIO0_TCR.21 = 1
* set GPIO1_OR.21 = 1
*/
gpio_reg = in32(GPIO1_TCR);
out32(GPIO1_TCR, gpio_reg | 0x00000400);
gpio_reg = in32(GPIO1_OR);
out32(GPIO1_OR, gpio_reg | 0x00000400);
/* Read Version ID */
cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
udelay(100000);
asm volatile(" sync");
asm volatile(" eieio");
debug("Cram ID: %X ", cram_id);
switch (cram_id) {
case MICRON_MT45W8MW16BGX_CRAM_ID:
case MICRON_MT45W8MW16BGX_CRAM_ID2:
/* supported CRAM vendor/part */
break;
case CRAM_DEVID_NOT_SUPPORTED:
default:
/* check for DIDR Vendor ID of Micron */
if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
MICRON_DIDR_VENDOR_ID)
{
/* supported CRAM vendor */
break;
}
/* this is not CRAM or not supported CRAM vendor/part */
cram_id = 0;
/*
* reset the GPIO registers to the values that were
* there before this routine
*/
out32(GPIO0_TCR, gpio_TCR);
out32(GPIO0_OSRL, gpio_OSRL);
out32(GPIO0_OR, gpio_OR);
out32(GPIO0_ISR1L, gpio_ISR1L);
break;
}
}
return cram_id;
}
static long int cram_init(u32 already_inited)
{
volatile u32 tmp_reg;
u32 cram_wr_val;
if (already_inited == 0) return 0;
/*
* If CRAM is initialized already, then don't reinitialize it again.
* In the case of NAND boot and SPI boot, CRAM will already be
* initialized by the pre-loader
*/
if (already_inited != 1)
{
/*
* #o CRAM Card
* # - CRAMCRE @reg16 = 1; for CRAM to use
* # - CRAMCRE @reg16 = 0; for CRAM to program
*
* # enable CRAM SEL, move from setEPLD.cmd
* set EPLD0_MUX_CTL.OECRAM = 0
* set EPLD0_MUX_CTL.CRAMCR = 1
* set EPLD0_ETHRSTBOOT.SLCRAM = 0
* #end
*/
/*
* #1. EBC need to program READY, CLK, ADV for ASync mode
* # config output
*/
/*
* # CRAM CLOCK
* set GPIO0_TCR.G8 = 1
* set GPIO0_OSRL.G8 = 0
* set GPIO0_OR.G8 = 0
*/
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x00800000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
tmp_reg = in32(GPIO0_OR);
out32(GPIO0_OR, tmp_reg & 0xff7fffff);
/*
* # CRAM Addreaa Valid
* set GPIO0_TCR.G10 = 1
* set GPIO0_OSRL.G10 = 0
* set GPIO0_OR.G10 = 0
*/
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x00200000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
tmp_reg = in32(GPIO0_OR);
out32(GPIO0_OR, tmp_reg & 0xffdfffff);
/*
* # config input (EBC_WAIT)
* set GPIO0_ISR1L.G9 = 1
* set GPIO0_TCR.G9 = 0
*/
tmp_reg = in32(GPIO0_ISR1L);
out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
/*
* # config CS4 from GPIO
* set GPIO0_TCR.G0 = 1
* set GPIO0_OSRL.G0 = 1
*/
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x80000000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg | 0x40000000);
/*
* #2. EBC in Async mode
* # set EBC0_PB1AP = 0x078f0ec0
* set EBC0_PB1AP = 0x078f1ec0
* set EBC0_PB2AP = 0x078f1ec0
*/
mtebc(pb1ap, 0x078F1EC0);
mtebc(pb2ap, 0x078F1EC0);
/*
* #set EBC0_PB1CR = 0x000bc000
* #enable CS2 for CRAM
* set EBC0_PB2CR = 0x020bc000
*/
mtebc(pb1cr, 0x000BC000);
mtebc(pb2cr, 0x020BC000);
/*
* #3. set CRAM in Sync mode
* #exec cm_bcr_write.cmd { 0x701f }
* #3. set CRAM in Sync mode (full drv strength)
* exec cm_bcr_write.cmd { 0x701F }
*/
cram_wr_val = 0x7012; /* CRAM burst setting */
cram_bcr_write(cram_wr_val);
/*
* #4. EBC in Sync mode
* #set EBC0_PB1AP = 0x9f800fc0
* #set EBC0_PB1AP = 0x900001c0
* set EBC0_PB2AP = 0x9C0201c0
* set EBC0_PB2AP = 0x9C0201c0
*/
mtebc(pb1ap, 0x9C0201C0);
mtebc(pb2ap, 0x9C0201C0);
/*
* #5. EBC need to program READY, CLK, ADV for Sync mode
* # config output
* set GPIO0_TCR.G8 = 1
* set GPIO0_OSRL.G8 = 1
* set GPIO0_TCR.G10 = 1
* set GPIO0_OSRL.G10 = 1
*/
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x00800000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg | 0x00004000);
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x00200000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg | 0x00000400);
/*
* # config input
* set GPIO0_ISR1L.G9 = 1
* set GPIO0_TCR.G9 = 0
*/
tmp_reg = in32(GPIO0_ISR1L);
out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
/*
* # config EBC to use RDY
* set SDR0_ULTRA0.EBCREN = 1
*/
mfsdr(sdrultra0, tmp_reg);
mtsdr(sdrultra0, tmp_reg | 0x04000000);
/*
* set EPLD0_MUX_CTL.OESPR3 = 0
*/
mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */
} /* if (already_inited != 1) */
return (64 * 1024 * 1024);
}
/******
* return 0 if not PSRAM
* return 1 if is PSRAM
******/
static int is_psram(u32 addr)
{
u32 test_pattern = 0xdeadbeef;
volatile u32 readback;
if (addr == CFG_SDRAM_BASE) {
/* This is to temp enable OE for PSRAM */
out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
udelay(10000);
}
out32(addr, test_pattern);
asm volatile(" sync");
asm volatile(" eieio");
readback = (volatile u32) in32(addr);
asm volatile(" sync");
asm volatile(" eieio");
if (readback == test_pattern) {
return 1;
} else {
return 0;
}
}
static long int psram_init(void)
{
u32 readback;
long psramsize = 0;
int i;
/* This is to temp enable OE for PSRAM */
out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
udelay(10000);
/*
* PSRAM bank 1: read then write to address 0x00000000
*/
for (i = 0; i < 100; i++) {
if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) {
readback = PSRAM_PASS;
} else {
readback = PSRAM_FAIL;
break;
}
}
if (readback == PSRAM_PASS) {
debug("psram_init(bank0): pass\n");
psramsize = (16 * 1024 * 1024);
} else {
debug("psram_init(bank0): fail\n");
return 0;
}
#if 0
/*
* PSRAM bank 1: read then write to address 0x01000000
*/
for (i = 0; i < 100; i++) {
if (is_psram((1 << 24) + (i*256)) == 1) {
readback = PSRAM_PASS;
} else {
readback = PSRAM_FAIL;
break;
}
}
if (readback == PSRAM_PASS) {
debug("psram_init(bank1): pass\n");
psramsize = psramsize + (16 * 1024 * 1024);
}
#endif
mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */
return psramsize;
}
long int initdram(int board_type)
{
long int sram_size;
u32 cram_inited;
u32 val;
/* Determine Attached Memory Expansion Card*/
cram_inited = is_cram();
if (cram_inited != 0) { /* CRAM */
debug("CRAM Expansion Card attached\n");
sram_size = cram_init(cram_inited);
} else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */
debug("PSRAM Expansion Card attached\n");
sram_size = psram_init();
} else { /* no SRAM */
debug("No Memory Card Attached!!\n");
sram_size = 0;
}
/* 1. EBC need to program READY, CLK, ADV for ASync mode */
gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
return sram_size;
/* 2. EBC in Async mode */
mtebc(pb1ap, 0x078F1EC0);
mtebc(pb2ap, 0x078F1EC0);
mtebc(pb1cr, 0x000BC000);
mtebc(pb2cr, 0x020BC000);
/* 3. Set CRAM in Sync mode */
cram_bcr_write(0x7012); /* CRAM burst setting */
/* 4. EBC in Sync mode */
mtebc(pb1ap, 0x9C0201C0);
mtebc(pb2ap, 0x9C0201C0);
/* Set GPIO pins back to alternate function */
gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
/* Config EBC to use RDY */
mfsdr(sdrultra0, val);
mtsdr(sdrultra0, val | 0x04000000);
return (CFG_MBYTES_RAM << 20);
}
int testdram(void)

View File

@ -62,19 +62,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)

View File

@ -41,7 +41,7 @@ struct serial_device *default_serial_console (void)
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
@ -91,7 +91,7 @@ void serial_initialize (void)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
serial_register(&serial0_device);
serial_register(&serial1_device);
#endif

214
cpu/ppc4xx/gpio.c Normal file
View File

@ -0,0 +1,214 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
#if defined(CFG_440_GPIO_TABLE)
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
#endif
#if defined(GPIO0_OSRL)
/* Only some 4xx variants support alternate funtions on the GPIO's */
void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
{
u32 mask;
u32 mask2;
u32 val;
u32 offs = 0;
u32 offs2 = 0;
int pin2 = pin << 1;
if (pin >= GPIO_MAX) {
offs = 0x100;
pin -= GPIO_MAX;
}
if (pin >= GPIO_MAX/2) {
offs2 = 0x100;
pin2 = (pin - GPIO_MAX/2) << 1;
}
mask = 0x80000000 >> pin;
mask2 = 0xc0000000 >> (pin2 << 1);
/* first set TCR to 0 */
out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);
if (in_out == GPIO_OUT) {
val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
switch (gpio_alt) {
case GPIO_ALT1:
val |= GPIO_ALT1_SEL >> pin2;
break;
case GPIO_ALT2:
val |= GPIO_ALT2_SEL >> pin2;
break;
case GPIO_ALT3:
val |= GPIO_ALT3_SEL >> pin2;
break;
}
out32(GPIO0_OSRL + offs + offs2, val);
/* setup requested output value */
if (out_val == GPIO_OUT_0)
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
else if (out_val == GPIO_OUT_1)
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask);
/* now configure TCR to drive output if selected */
out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask);
} else {
val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
val |= GPIO_IN_SEL >> pin2;
out32(GPIO0_ISR1L + offs + offs2, val);
}
}
#endif /* GPIO_OSRL */
void gpio_write_bit(int pin, int val)
{
u32 offs = 0;
if (pin >= GPIO_MAX) {
offs = 0x100;
pin -= GPIO_MAX;
}
if (val)
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin));
else
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
}
#if defined(CFG_440_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
unsigned char i=0, j=0, offs=0, gpio_core;
unsigned long reg, core_add;
for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
j = 0;
offs = 0;
/* GPIO config of the GPIOs 0 to 31 */
for (i=0; i<GPIO_MAX; i++, j++) {
if (i == GPIO_MAX/2) {
offs = 4;
j = i-16;
}
core_add = gpio_tab[gpio_core][i].add;
if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
switch (gpio_tab[gpio_core][i].alt_nb) {
case GPIO_SEL:
break;
case GPIO_ALT1:
reg = in32(GPIO_IS1(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS1(core_add+offs), reg);
break;
case GPIO_ALT2:
reg = in32(GPIO_IS2(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS2(core_add+offs), reg);
break;
case GPIO_ALT3:
reg = in32(GPIO_IS3(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS3(core_add+offs), reg);
break;
}
}
if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
switch (gpio_tab[gpio_core][i].alt_nb) {
case GPIO_SEL:
if (gpio_core == GPIO0) {
reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
out32(GPIO0_TCR, reg);
}
if (gpio_core == GPIO1) {
reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
out32(GPIO1_TCR, reg);
}
reg = in32(GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
out32(GPIO_OS(core_add+offs), reg);
reg = in32(GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
out32(GPIO_TS(core_add+offs), reg);
break;
case GPIO_ALT1:
reg = in32(GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT1_SEL >> (j*2));
out32(GPIO_OS(core_add+offs), reg);
reg = in32(GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT1_SEL >> (j*2));
out32(GPIO_TS(core_add+offs), reg);
break;
case GPIO_ALT2:
reg = in32(GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT2_SEL >> (j*2));
out32(GPIO_OS(core_add+offs), reg);
reg = in32(GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT2_SEL >> (j*2));
out32(GPIO_TS(core_add+offs), reg);
break;
case GPIO_ALT3:
reg = in32(GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT3_SEL >> (j*2));
out32(GPIO_OS(core_add+offs), reg);
reg = in32(GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT3_SEL >> (j*2));
out32(GPIO_TS(core_add+offs), reg);
break;
}
}
}
}
}
#endif /* CFG_440_GPIO_TABLE */

View File

@ -2,6 +2,7 @@
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
@ -757,7 +758,6 @@ _start:
#endif /* CONFIG_405EP */
#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
/* test-only... (clean up later when NAND booting is supported) */
#if defined(CONFIG_405EZ)
/********************************************************************
* Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
@ -786,41 +786,7 @@ _start:
mtdcr ocmdsisdpc,r4
isync
#if defined(CONFIG_NAND_SPL)
/*
* 405EZ can boot from NAND Flash.
* If we are booting the SPL (Pre-loader), copy code from
* the mapped 4K NAND Flash to the OCM
*/
li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
mtctr r4
lis r2,CFG_NAND_BOOT_SPL_SRC@h
ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
lis r3,CFG_NAND_BOOT_SPL_DST@h
ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
spl_loop:
lwzu r4,4(r2)
stwu r4,4(r3)
bdnz spl_loop
/*
* Jump to code in OCM Ram
*/
bl 00f
00: mflr r10
lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
sub r10,r10,r3
addi r10,r10,28
mtlr r10
blr
start_ram:
sync
isync
#endif
#else
/* ...test-only */
#else /* CONFIG_405EZ */
/********************************************************************
* Setup OCM - On Chip Memory
*******************************************************************/
@ -828,14 +794,15 @@ start_ram:
lis r0, 0x7FFF
ori r0, r0, 0xFFFF
mfdcr r3, ocmiscntl /* get instr-side IRAM config */
mfdcr r4, ocmdscntl /* get data-side IRAM config */
and r3, r3, r0 /* disable data-side IRAM */
and r4, r4, r0 /* disable data-side IRAM */
mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
mtdcr ocmdscntl, r4 /* set data-side IRAM config */
mfdcr r4, ocmdscntl /* get data-side IRAM config */
and r3, r3, r0 /* disable data-side IRAM */
and r4, r4, r0 /* disable data-side IRAM */
mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
mtdcr ocmdscntl, r4 /* set data-side IRAM config */
isync
addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
ori r3,r3,CFG_OCM_DATA_ADDR@l
mtdcr ocmdsarc, r3
addis r4, 0, 0xC000 /* OCM data area enabled */
mtdcr ocmdscntl, r4

View File

@ -31,20 +31,18 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_ACADIA 1 /* Board is Acadia */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
#undef CFG_DRAM_TEST /* Disable-takes long time */
#define CONFIG_ACADIA 1 /* Board is Acadia */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
#define CONFIG_NO_SERIAL_EEPROM
/*#undef CONFIG_NO_SERIAL_EEPROM*/
#ifdef CONFIG_NO_SERIAL_EEPROM
/*----------------------------------------------------------------------------
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
* assuming a 66MHz input clock to the 405EZ.
@ -59,24 +57,125 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFE000000
#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */
#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xfe000000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_CPLD_BASE 0x80000000
#define CFG_NAND_ADDR 0xd0000000
#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
/*
* Define here the location of the environment variables (FLASH).
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
* supported for backward compatibility.
*/
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CFG_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* RAM (CRAM)
*----------------------------------------------------------------------*/
#define CFG_MBYTES_RAM 64 /* 64MB */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
#if 0 /* test-only... */
/*-----------------------------------------------------------------------
* SPI stuff - Define to include SPI control
*-----------------------------------------------------------------------
*/
#define CONFIG_SPI
#endif
/*-----------------------------------------------------------------------
* Ethernet
*----------------------------------------------------------------------*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
@ -122,13 +221,6 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
@ -166,7 +258,6 @@
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_USB)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@ -174,76 +265,34 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*/
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CFG_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
#if 0 /* test-only... */
/*-----------------------------------------------------------------------
* SPI stuff - Define to include SPI control
*-----------------------------------------------------------------------
*/
#define CONFIG_SPI
#endif
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
@ -251,39 +300,13 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#ifdef TEST_ONLY_NAND
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS)
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#endif
@ -296,50 +319,42 @@
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define CFG_NAND 0xd0000000
*----------------------------------------------------------------------*/
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 0 (Flash) initialization */
/* Memory Bank 0 (Flash) initialization */
#define CFG_EBC_PB0AP 0x03337200
#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */
#define CFG_EBC_PB0CR 0xfe0bc000
/* Memory Bank 1 (CRAM) initialization */
/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
/* Memory Bank 1 (CRAM) initialization */
#define CFG_EBC_PB1AP 0x030400c0
#define CFG_EBC_PB1CR 0x000bc000
/* Memory Bank 2 (CRAM) initialization */
/* Memory Bank 2 (CRAM) initialization */
#define CFG_EBC_PB2AP 0x030400c0
#define CFG_EBC_PB2CR 0x020bc000
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CFG_EBC_PB3AP 0x018003c0
#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000)
#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
/* Memory Bank 4 (CPLD) initialization */
/* Memory Bank 4 (CPLD) initialization */
#define CFG_EBC_PB4AP 0x04006000
#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */
#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000)
#define CFG_EBC_CFG 0xf8400000
/*-----------------------------------------------------------------------
* GPIO Setup
*----------------------------------------------------------------------*/
#define CFG_GPIO_CRAM_CLK 8
#define CFG_GPIO_CRAM_WAIT 9
#define CFG_GPIO_CRAM_ADV 10
#define CFG_GPIO_CRAM_CRE (32 + 21)
/*-----------------------------------------------------------------------
* Definitions for GPIO_0 setup (PPC405EZ specific)
*
@ -389,25 +404,6 @@
#define CFG_GPIO1_TSRL 0x00000000
#define CFG_GPIO1_TCR 0xFFFF8014
/*-----------------------------------------------------------------------
* EPLD Regs.
*/
#define EPLD_BASE 0x80000000
#define EPLD_ETHRSTBOOT 0x10
#define EPLD_CTRL 0x14
#define EPLD_MUXOE 0x16
/*
* State definations
*/
#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */
#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */
#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */
#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */
#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */
#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */
#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */
/*
* Internal Definitions
*

View File

@ -23,7 +23,7 @@ extern struct serial_device serial_scc_device;
extern struct serial_device * default_serial_console (void);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CFG_NS16550_SERIAL)