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Merge git://www.denx.de/git/u-boot

This commit is contained in:
Kim Phillips 2007-04-23 15:58:17 -05:00
parent 6fbf261f8d 14da5f7675
commit 396955fed2
365 changed files with 40453 additions and 5536 deletions
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1723
CHANGELOG
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File diff suppressed because it is too large Load Diff

5
CREDITS
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@ -474,3 +474,8 @@ N: Timur Tabi
E: timur@freescale.com
D: Support for MPC8349E-mITX
W: www.freescale.com
N: Michal Simek
E: monstr@monstr.eu
D: Support for Microblaze, ML401, XUPV2P board
W: www.monstr.eu

27
MAINTAINERS
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@ -257,15 +257,6 @@ Frank Panno <fpanno@delphintech.com>
ep8260 MPC8260
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied &
supported core modules
- see http://www.arm.com
/products/DevTools
/Hardware_Platforms.html
versatile ARM926EJ-S
versatile ARM926EJ-S
Denis Peter <d.peter@mpl.ch>
MIP405 PPC4xx
@ -284,6 +275,7 @@ Stefan Roese <sr@denx.de>
TQM85xx MPC8540/8541/8555/8560
acadia PPC405EZ
alpr PPC440GX
bamboo PPC440EP
bunbinga PPC405EP
@ -443,6 +435,9 @@ Gary Jennejohn <gj@denx.de>
smdk2400 ARM920T
trab ARM920T
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
@ -460,6 +455,15 @@ Rolf Offermanns <rof@sysgo.de>
shannon SA1100
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied &
supported core modules
-see http://www.arm.com
/products/DevTools
/Hardware_Platforms.html
versatile ARM926EJ-S
versatile ARM926EJ-S
Dave Peverley <dpeverley@mpc-data.co.uk>
omap730p2 ARM926EJS
@ -563,6 +567,11 @@ Yasushi Shoji <yashi@atmark-techno.com>
SUZAKU MicroBlaze
Michal Simek <monstr@monstr.eu>
ML401 MicroBlaze
XUPV2P MicroBlaze
#########################################################################
# Coldfire Systems: #
# #

54
MAKEALL
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@ -75,22 +75,22 @@ LIST_8xx=" \
#########################################################################
LIST_4xx=" \
ADCIOP alpr AP1000 AR405 \
ASH405 bamboo bubinga CANBT \
CMS700 CPCI2DP CPCI405 CPCI4052 \
CPCI405AB CPCI405DT CPCI440 CPCIISER4 \
CRAYL1 csb272 csb472 DASA_SIM \
DP405 DU405 ebony ERIC \
EXBITGEN G2000 HH405 HUB405 \
JSE KAREF katmai luan \
METROBOX MIP405 MIP405T ML2 \
ml300 ocotea OCRTC ORSG \
p3p440 PCI405 pcs440ep PIP405 \
PLU405 PMC405 PPChameleonEVB sbc405 \
sc3 sequoia sequoia_nand taishan \
VOH405 VOM405 W7OLMC W7OLMG \
walnut WUH405 XPEDITE1K yellowstone \
yosemite yucca \
acadia ADCIOP alpr AP1000 \
AR405 ASH405 bamboo bubinga \
CANBT CMS700 CPCI2DP CPCI405 \
CPCI4052 CPCI405AB CPCI405DT CPCI440 \
CPCIISER4 CRAYL1 csb272 csb472 \
DASA_SIM DP405 DU405 ebony \
ERIC EXBITGEN G2000 HH405 \
HUB405 JSE KAREF katmai \
luan METROBOX MIP405 MIP405T \
ML2 ml300 ocotea OCRTC \
ORSG p3p440 PCI405 pcs440ep \
PIP405 PLU405 PMC405 PPChameleonEVB \
sbc405 sc3 sequoia sequoia_nand \
taishan VOH405 VOM405 W7OLMC \
W7OLMG walnut WUH405 XPEDITE1K \
yellowstone yosemite yucca \
"
#########################################################################
@ -155,6 +155,7 @@ LIST_85xx=" \
LIST_74xx=" \
DB64360 DB64460 EVB64260 P3G4 \
p3m7448 PCIPPC2 PCIPPC6 ZUMA \
mpc7448hpc2
"
LIST_7xx=" \
@ -293,7 +294,7 @@ LIST_nios2=" \
#########################################################################
LIST_microblaze=" \
suzaku
suzaku ml401 xupv2p
"
#########################################################################
@ -312,6 +313,14 @@ LIST_coldfire=" \
LIST_avr32="atstk1002"
#########################################################################
## Blackfin Systems
#########################################################################
LIST_blackfin=" \
bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit \
"
#-----------------------------------------------------------------------
#----- for now, just run PPC by default -----
@ -338,14 +347,15 @@ build_target() {
for arg in $@
do
case "$arg" in
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \
arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa| \
avr32| \
blackfin| \
coldfire| \
microblaze| \
mips|mips_el| \
nios|nios2| \
x86|I486| \
coldfire| \
avr32)
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}

103
Makefile
View File

@ -146,10 +146,10 @@ ifeq ($(ARCH),microblaze)
CROSS_COMPILE = mb-
endif
ifeq ($(ARCH),blackfin)
CROSS_COMPILE = bfin-elf-
CROSS_COMPILE = bfin-uclinux-
endif
ifeq ($(ARCH),avr32)
CROSS_COMPILE = avr32-
CROSS_COMPILE = avr32-linux-
endif
endif
endif
@ -178,7 +178,15 @@ OBJS += cpu/$(CPU)/resetvec.o
endif
ifeq ($(CPU),bf533)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
ifeq ($(CPU),bf537)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
ifeq ($(CPU),bf561)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
OBJS := $(addprefix $(obj),$(OBJS))
@ -211,6 +219,7 @@ LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
LIBS += common/libcommon.a
LIBS += libfdt/libfdt.a
LIBS += $(BOARDLIBS)
LIBS := $(addprefix $(obj),$(LIBS))
@ -422,6 +431,7 @@ inka4x0_config: unconfig
@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
lite5200b_config \
lite5200b_PM_config \
lite5200b_LOWBOOT_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/icecube
@ -430,6 +440,10 @@ lite5200b_LOWBOOT_config: unconfig
@ echo "... DDR memory revision"
@ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h
@ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h
@[ -z "$(findstring _PM_,$@)" ] || \
{ echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \
echo "... with power management (low-power mode) support" ; \
}
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
echo "... with LOWBOOT configuration" ; \
@ -998,6 +1012,9 @@ wtk_config: unconfig
#########################################################################
xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))
acadia_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc
ADCIOP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd
@ -1179,44 +1196,31 @@ PPChameleonEVB_HI_33_config: unconfig
}
@$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
rainier_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_RAINIER" > $(obj)include/config.h
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
rainier_nand_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)nand_spl
@mkdir -p $(obj)board/amcc/sequoia
@echo "#define CONFIG_RAINIER" > $(obj)include/config.h
@echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h
@echo "Compile NAND boot image for sequoia"
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sbc405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
sequoia_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sequoia amcc
sequoia_config \
rainier_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
sequoia_nand_config: unconfig
sequoia_nand_config \
rainier_nand_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)nand_spl
@mkdir -p $(obj)board/amcc/sequoia
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
@echo "Compile NAND boot image for sequoia"
@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sc3_config:unconfig
@./mkconfig $(@:_config=) ppc ppc4xx sc3
sycamore_config: unconfig
@$(MKCONFIG) -n $@ -a walnut ppc ppc4xx walnut amcc
taishan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
@ -1233,8 +1237,10 @@ W7OLMC_config \
W7OLMG_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx w7o
walnut_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx walnut amcc
# Walnut & Sycamore images are identical (recognized via PVR)
walnut_config \
sycamore_config: unconfig
@$(MKCONFIG) -n $@ -a walnut ppc ppc4xx walnut amcc
WUH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
@ -1242,12 +1248,11 @@ WUH405_config: unconfig
XPEDITE1K_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k
yosemite_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yosemite amcc
yellowstone_config: unconfig
yosemite_config \
yellowstone_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_YELLOWSTONE" > $(obj)include/config.h
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a yosemite ppc ppc4xx yosemite amcc
yucca_config: unconfig
@ -1815,6 +1820,9 @@ EVB64260_config \
EVB64260_750CX_config: unconfig
@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
mpc7448hpc2_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
P3G4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
@ -2347,17 +2355,30 @@ suzaku_config: unconfig
@echo "#define CONFIG_SUZAKU 1" >> $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
ml401_config: unconfig
@ >include/config.h
@echo "#define CONFIG_ML401 1" >> include/config.h
@./mkconfig -a $(@:_config=) microblaze microblaze ml401 xilinx
xupv2p_config: unconfig
@ >include/config.h
@echo "#define CONFIG_XUPV2P 1" >> include/config.h
@./mkconfig -a $(@:_config=) microblaze microblaze xupv2p xilinx
#########################################################################
## Blackfin
#########################################################################
ezkit533_config : unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 ezkit533
bf533-ezkit_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-ezkit
stamp_config : unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 stamp
bf533-stamp_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-stamp
dspstamp_config : unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 dsp_stamp
bf537-stamp_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf537 bf537-stamp
bf561-ezkit_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf561 bf561-ezkit
#========================================================================
# AVR32
@ -2394,6 +2415,8 @@ clean:
rm -f $(obj)board/netstar/*.srec $(obj)board/netstar/*.bin
rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
rm -f $(obj)board/bf533-ezkit/u-boot.lds $(obj)board/bf533-stamp/u-boot.lds
rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
rm -f $(obj)include/bmp_logo.h
rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map

55
README
View File

@ -164,6 +164,7 @@ Directory Hierarchy:
- lib_mips Files generic to MIPS architecture
- lib_nios Files generic to NIOS architecture
- lib_ppc Files generic to PowerPC architecture
- libfdt Library files to support flattened device trees
- net Networking code
- post Power On Self Test
- rtc Real Time Clock drivers
@ -430,12 +431,23 @@ The following options need to be configured:
expect it to be in bytes, others in MB.
Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
CONFIG_OF_FLAT_TREE
CONFIG_OF_LIBFDT / CONFIG_OF_FLAT_TREE
New kernel versions are expecting firmware settings to be
passed using flat open firmware trees.
The environment variable "disable_of", when set, disables this
functionality.
passed using flattened device trees (based on open firmware
concepts).
CONFIG_OF_LIBFDT
* New libfdt-based support
* Adds the "fdt" command
* The bootm command does _not_ modify the fdt
CONFIG_OF_FLAT_TREE
* Deprecated, see CONFIG_OF_LIBFDT
* Original ft_build.c-based support
* Automatically modifies the dft as part of the bootm command
* The environment variable "disable_of", when set,
disables this functionality.
CONFIG_OF_FLAT_TREE_MAX_SIZE
@ -448,13 +460,16 @@ The following options need to be configured:
CONFIG_OF_HAS_BD_T
The resulting flat device tree will have a copy of the bd_t.
Space should be pre-allocated in the dts for the bd_t.
* CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
* CONFIG_OF_FLAT_TREE - The resulting flat device tree
will have a copy of the bd_t. Space should be
pre-allocated in the dts for the bd_t.
CONFIG_OF_HAS_UBOOT_ENV
The resulting flat device tree will have a copy of u-boot's
environment variables
* CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
* CONFIG_OF_FLAT_TREE - The resulting flat device tree
will have a copy of u-boot's environment variables
CONFIG_OF_BOARD_SETUP
@ -721,6 +736,8 @@ The following options need to be configured:
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET)
Other Commands:
fdt (flattened device tree) command: CONFIG_OF_LIBFDT
Note: Don't enable the "icache" and "dcache" commands
(configuration option CFG_CMD_CACHE) unless you know
@ -2381,17 +2398,17 @@ configurations; the following names are supported:
csb272_config lwmon_config sbc8260_config
CU824_config MBX860T_config sbc8560_33_config
DUET_ADS_config MBX_config sbc8560_66_config
EBONY_config MPC8260ADS_config SM850_config
ELPT860_config MPC8540ADS_config SPD823TS_config
ESTEEM192E_config MPC8540EVAL_config stxgp3_config
ETX094_config MPC8560ADS_config SXNI855T_config
FADS823_config NETVIA_config TQM823L_config
FADS850SAR_config omap1510inn_config TQM850L_config
FADS860T_config omap1610h2_config TQM855L_config
FPS850L_config omap1610inn_config TQM860L_config
omap5912osk_config walnut_config
omap2420h4_config Yukon8220_config
ZPC1900_config
EBONY_config mpc7448hpc2_config SM850_config
ELPT860_config MPC8260ADS_config SPD823TS_config
ESTEEM192E_config MPC8540ADS_config stxgp3_config
ETX094_config MPC8540EVAL_config SXNI855T_config
FADS823_config NMPC8560ADS_config TQM823L_config
FADS850SAR_config NETVIA_config TQM850L_config
FADS860T_config omap1510inn_config TQM855L_config
FPS850L_config omap1610h2_config TQM860L_config
omap1610inn_config walnut_config
omap5912osk_config Yukon8220_config
omap2420h4_config ZPC1900_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for

2
avr32_config.mk
View File

@ -21,5 +21,5 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic -mrelax
PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax
PLATFORM_LDFLAGS += --relax

2
blackfin_config.mk
View File

@ -21,4 +21,4 @@
# MA 02111-1307 USA
#
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN

2
board/AtmarkTechno/suzaku/suzaku.c
View File

@ -24,7 +24,7 @@
/* This is a board specific file. It's OK to include board specific
* header files */
#include <asm/suzaku.h>
#include <config.h>
void do_reset(void)
{

3
board/AtmarkTechno/suzaku/u-boot.lds
View File

@ -61,6 +61,7 @@ SECTIONS
{
__bss_start = .;
*(.bss)
__bss_start = .;
__bss_end = .;
}
__end = . ;
}

17
board/ezkit533/Makefile → board/amcc/acadia/Makefile
View File

@ -1,9 +1,5 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005 blackfin.uclinux.org
#
# (C) Copyright 2000-2006
# (C) Copyright 2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -29,15 +25,22 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ezkit533.o
COBJS = $(BOARD).o cpr.o memory.o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
#########################################################################
# defines $(obj).depend target

103
board/amcc/acadia/acadia.c Normal file
View File

@ -0,0 +1,103 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
extern void board_pll_init_f(void);
static void acadia_gpio_init(void)
{
/*
* GPIO0 setup (select GPIO or alternate function)
*/
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
/*
* Ultra (405EZ) was nice enough to add another GPIO controller
*/
out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
}
int board_early_init_f(void)
{
unsigned int reg;
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
acadia_gpio_init();
/* USB Host core needs this bit set */
mfsdr(sdrultra1, reg);
mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000010);
mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
int misc_init_f(void)
{
/* Set EPLD to take PHY out of reset */
out8(CFG_CPLD_BASE + 0x05, 0x00);
udelay(100000);
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return (0);
}

11
board/ezkit533/config.mk → board/amcc/acadia/config.mk
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2001
# (C) Copyright 2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -21,5 +21,10 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0x01FC0000
PLATFORM_CPPFLAGS += -I$(TOPDIR)
ifndef TEXT_BASE
TEXT_BASE = 0xFFFC0000
endif
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

195
board/amcc/acadia/cpr.c Normal file
View File

@ -0,0 +1,195 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <ppc405.h>
/* test-only: move into cpu directory!!! */
#if defined(PLLMR0_200_133_66)
void board_pll_init_f(void)
{
/*
* set PLL clocks based on input sysclk is 33M
*
* ----------------------------------
* | CLK | FREQ (MHz) | DIV RATIO |
* ----------------------------------
* | CPU | 200.0 | 4 (0x02)|
* | PLB | 133.3 | 6 (0x06)|
* | OPB | 66.6 | 12 (0x0C)|
* | EBC | 66.6 | 12 (0x0C)|
* | SPI | 66.6 | 12 (0x0C)|
* | UART0 | 10.0 | 40 (0x28)|
* | UART1 | 10.0 | 40 (0x28)|
* | DAC | 2.0 | 200 (0xC8)|
* | ADC | 2.0 | 200 (0xC8)|
* | PWM | 100.0 | 4 (0x04)|
* | EMAC | 25.0 | 16 (0x10)|
* -----------------------------------
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033c);
mtcpr(cprplld, 0x0c010200);
mtcpr(cprprimad, 0x04060c0c);
mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprclkupd, 0x40000000);
}
#elif defined(PLLMR0_266_160_80)
void board_pll_init_f(void)
{
/*
* set PLL clocks based on input sysclk is 33M
*
* ----------------------------------
* | CLK | FREQ (MHz) | DIV RATIO |
* ----------------------------------
* | CPU | 266.64 | 3 |
* | PLB | 159.98 | 5 (0x05)|
* | OPB | 79.99 | 10 (0x0A)|
* | EBC | 79.99 | 10 (0x0A)|
* | SPI | 79.99 | 10 (0x0A)|
* | UART0 | 28.57 | 7 (0x07)|
* | UART1 | 28.57 | 7 (0x07)|
* | DAC | 28.57 | 7 (0xA7)|
* | ADC | 4 | 50 (0x32)|
* | PWM | 28.57 | 7 (0x07)|
* | EMAC | 4 | 50 (0x32)|
* -----------------------------------
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x20000238);
mtcpr(cprplld, 0x03010400);
mtcpr(cprprimad, 0x03050a0a);
mtcpr(cprperc0, 0x00000000);
mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0x07323200);
mtcpr(cprclkupd, 0x40000000);
}
#elif defined(PLLMR0_333_166_83)
void board_pll_init_f(void)
{
/*
* set PLL clocks based on input sysclk is 33M
*
* ----------------------------------
* | CLK | FREQ (MHz) | DIV RATIO |
* ----------------------------------
* | CPU | 333.33 | 2 |
* | PLB | 166.66 | 4 (0x04)|
* | OPB | 83.33 | 8 (0x08)|
* | EBC | 83.33 | 8 (0x08)|
* | SPI | 83.33 | 8 (0x08)|
* | UART0 | 16.66 | 5 (0x05)|
* | UART1 | 16.66 | 5 (0x05)|
* | DAC | ???? | 166 (0xA6)|
* | ADC | ???? | 166 (0xA6)|
* | PWM | 41.66 | 3 (0x03)|
* | EMAC | ???? | 3 (0x03)|
* -----------------------------------
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033C);
mtcpr(cprplld, 0x0a010000);
mtcpr(cprprimad, 0x02040808);
mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xA6A60300);
mtcpr(cprclkupd, 0x40000000);
}
#elif defined(PLLMR0_100_100_12)
void board_pll_init_f(void)
{
/*
* set PLL clocks based on input sysclk is 33M
*
* ----------------------
* | CLK | FREQ (MHz) |
* ----------------------
* | CPU | 100.00 |
* | PLB | 100.00 |
* | OPB | 12.00 |
* | EBC | 49.00 |
* ----------------------
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x000003BC);
mtcpr(cprplld, 0x06060600);
mtcpr(cprprimad, 0x02020004);
mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xC8C81600);
mtcpr(cprclkupd, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk(void)
{
unsigned long cpr_plld;
unsigned long cpr_primad;
unsigned long primad_cpudv;
unsigned long pllFbkDiv;
unsigned long freqProcessor;
/*
* Read PLL Mode registers
*/
mfcpr(cprplld, cpr_plld);
/*
* Read CPR_PRIMAD register
*/
mfcpr(cprprimad, cpr_primad);
/*
* Determine CPU clock frequency
*/
primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
if (primad_cpudv == 0)
primad_cpudv = 16;
/*
* Determine FBK_DIV.
*/
pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
if (pllFbkDiv == 0)
pllFbkDiv = 256;
freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
return (freqProcessor);
}
#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */

103
board/amcc/acadia/memory.c Normal file
View File

@ -0,0 +1,103 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* define DEBUG for debugging output (obviously ;-)) */
#if 0
#define DEBUG
#endif
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
/* set CRAM_CRE to 1 */
gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
/* Write BCR to CRAM on CS1 */
out32(wr_val + 0x00200000, 0);
debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
/* Write BCR to CRAM on CS2 */
out32(wr_val + 0x02200000, 0);
debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
sync();
eieio();
/* set CRAM_CRE back to 0 (normal operation) */
gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
return;
}
long int initdram(int board_type)
{
u32 val;
/* 1. EBC need to program READY, CLK, ADV for ASync mode */
gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
/* 2. EBC in Async mode */
mtebc(pb1ap, 0x078F1EC0);
mtebc(pb2ap, 0x078F1EC0);
mtebc(pb1cr, 0x000BC000);
mtebc(pb2cr, 0x020BC000);
/* 3. Set CRAM in Sync mode */
cram_bcr_write(0x7012); /* CRAM burst setting */
/* 4. EBC in Sync mode */
mtebc(pb1ap, 0x9C0201C0);
mtebc(pb2ap, 0x9C0201C0);
/* Set GPIO pins back to alternate function */
gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
/* Config EBC to use RDY */
mfsdr(sdrultra0, val);
mtsdr(sdrultra0, val | 0x04000000);
return (CFG_MBYTES_RAM << 20);
}
int testdram(void)
{
return (0);
}

137
board/amcc/acadia/u-boot.lds Normal file
View File

@ -0,0 +1,137 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

1
board/amcc/bamboo/bamboo.c
View File

@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <spd_sdram.h>
#include <ppc440.h>
#include "bamboo.h"

10
board/amcc/bamboo/bamboo.h
View File

@ -264,19 +264,9 @@
#define TRUE 1
#define FALSE 0
#define GPIO_GROUP_MAX 2
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
/* For the other GPIO number, you must shift */
#define GPIO0 0
#define GPIO1 1
/*#define MAX_SELECTION_NB CORE_NB */
#define MAX_CORE_SELECT_NB 22

105
board/amcc/katmai/cmd_katmai.c
View File

@ -27,6 +27,9 @@
#include <i2c.h>
#include <asm/byteorder.h>
#define CONFIG_STRESS /* enable 667 MHz CPU freq selection */
#define DEBUG
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar chip;
@ -49,55 +52,28 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
else
chip = IIC0_ALT_BOOTPROM_ADDR;
do {
printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0))
nbytes=0;
strcpy(sysClock, console_buffer);
} while (nbytes == 0);
/* on Katmai SysClk is always 33MHz */
strcpy(sysClock, "33");
do {
if (strcmp(sysClock, "66") == 0) {
printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
} else {
#ifdef CONFIG_STRESS
printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
#else
printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
#endif
}
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "533") != 0)
if ((strcmp(console_buffer, "400") != 0) &&
(strcmp(console_buffer, "500") != 0) &&
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
&& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
} else {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "500") != 0) &
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
) {
nbytes = 0;
}
strcpy(cpuClock, console_buffer);
@ -124,13 +100,13 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
if (strcmp(cpuClock, "400") == 0) {
if ((strcmp(console_buffer, "100") != 0) &
if ((strcmp(console_buffer, "100") != 0) &&
(strcmp(console_buffer, "133") != 0))
nbytes = 0;
}
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0) {
if ((strcmp(console_buffer, "133") != 0) &
if ((strcmp(console_buffer, "133") != 0) &&
(strcmp(console_buffer, "166") != 0))
nbytes = 0;
}
@ -147,9 +123,9 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0) &
(strcmp(console_buffer, "100") != 0) &
if ((strcmp(console_buffer, "33") != 0) &&
(strcmp(console_buffer, "66") != 0) &&
(strcmp(console_buffer, "100") != 0) &&
(strcmp(console_buffer, "133") != 0)) {
nbytes = 0;
}
@ -176,11 +152,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
} while (nbytes == 0);
if (strcmp(sysClock, "33") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
if ((strcmp(cpuClock, "400") == 0) &&
(strcmp(plbClock, "100") == 0))
data = 0x8678c206;
if ((strcmp(cpuClock, "400") == 0) &
if ((strcmp(cpuClock, "400") == 0) &&
(strcmp(plbClock, "133") == 0))
data = 0x8678c2c6;
@ -189,42 +165,16 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if ((strcmp(cpuClock, "533") == 0))
data = 0x87790252;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
if ((strcmp(cpuClock, "667") == 0) &&
(strcmp(plbClock, "133") == 0))
data = 0x87794256;
if ((strcmp(cpuClock, "667") == 0) &
if ((strcmp(cpuClock, "667") == 0) &&
(strcmp(plbClock, "166") == 0))
data = 0x87794206;
#endif
}
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "100") == 0))
data = 0x84706206;
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x847062c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x85708206;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x8570a256;
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "166") == 0))
data = 0x8570a206;
#endif
}
#ifdef DEBUG
printf(" pin strap0 to write in i2c = %x\n", data);
#endif /* DEBUG */
@ -233,19 +183,20 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("Error writing strap0 in %s\n", argv[2]);
if (strcmp(pcixClock, "33") == 0)
data = 0x00000701;
data = 0x000007E1;
if (strcmp(pcixClock, "66") == 0)
data = 0x00000601;
data = 0x000006E1;
if (strcmp(pcixClock, "100") == 0)
data = 0x00000501;
data = 0x000005E1;
if (strcmp(pcixClock, "133") == 0)
data = 0x00000401;
data = 0x000004E1;
if (strcmp(plbClock, "166") == 0)
data |= 0x05950000;
/* data |= 0x05950000; */ /* this set's DDR2 clock == PLB clock */
data |= 0x05A50000; /* this set's DDR2 clock == 2 * PLB clock */
else
data |= 0x05A50000;

2
board/amcc/katmai/init.S
View File

@ -103,7 +103,7 @@ tlbtabB:
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)

1
board/amcc/katmai/katmai.c
View File

@ -27,6 +27,7 @@
#include <asm/processor.h>
#include <i2c.h>
#include <asm-ppc/io.h>
#include <asm-ppc/gpio.h>
#include "../cpu/ppc4xx/440spe_pcie.h"

4
board/amcc/sequoia/sequoia.c
View File

@ -363,8 +363,8 @@ int checkboard(void)
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
rev = *(u8 *)(CFG_BCSR_BASE + 0);
val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {

2
board/atmel/atstk1000/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(BOARD).a
COBJS := $(BOARD).o flash.o
COBJS := $(BOARD).o flash.o eth.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

24
board/atmel/atstk1000/atstk1000.c
View File

@ -23,6 +23,8 @@
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
DECLARE_GLOBAL_DATA_PTR;
@ -40,9 +42,27 @@ static const struct sdram_info sdram = {
.txsr = 5,
};
void board_init_memories(void)
int board_early_init_f(void)
{
gd->sdram_size = sdram_init(&sdram);
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
hmatrix2_writel(SFR4, 1 << 1);
gpio_enable_ebi();
gpio_enable_usart1();
#if defined(CONFIG_MACB)
gpio_enable_macb0();
gpio_enable_macb1();
#endif
#if defined(CONFIG_MMC)
gpio_enable_mmci();
#endif
return 0;
}
long int initdram(int board_type)
{
return sdram_init(&sdram);
}
void board_init_info(void)

22
cpu/at32ap/at32ap7000/hebi.c → board/atmel/atstk1000/eth.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2006 Atmel Corporation
* Copyright (C) 2005-2006 Atmel Corporation
*
* Ethernet initialization for the ATSTK1000 starterkit
*
* See file CREDITS for list of people who contributed to this
* project.
@ -21,18 +23,16 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hmatrix2.h>
#include <asm/arch/memory-map.h>
#include <asm/arch/platform.h>
void cpu_enable_sdram(void)
extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & CFG_CMD_NET)
void atstk1000_eth_initialize(bd_t *bi)
{
const struct device *hmatrix;
int id = 0;
hmatrix = get_device(DEVICE_HMATRIX);
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
hmatrix2_writel(hmatrix, SFR4, 1 << 1);
macb_eth_initialize(id++, (void *)MACB0_BASE, bi->bi_phy_id[0]);
macb_eth_initialize(id++, (void *)MACB1_BASE, bi->bi_phy_id[1]);
}
#endif

2
board/atmel/atstk1000/flash.c
View File

@ -57,7 +57,7 @@ unsigned long flash_init(void)
gd->bd->bi_flashstart = CFG_FLASH_BASE;
gd->bd->bi_flashsize = CFG_FLASH_SIZE;
gd->bd->bi_flashoffset = __edata_lma - _text;
gd->bd->bi_flashoffset = _edata - _text;
flash_info[0].size = CFG_FLASH_SIZE;
flash_info[0].sector_count = 135;

21
board/atmel/atstk1000/u-boot.lds
View File

@ -40,35 +40,38 @@ SECTIONS
}
. = ALIGN(32);
__flashprog_end = .;
_etext = .;
. = ALIGN(8);
.rodata : {
*(.rodata)
*(.rodata.*)
}
_etext = .;
__data_lma = ALIGN(8);
. = 0x24000000;
. = ALIGN(8);
_data = .;
.data : AT(__data_lma) {
.data : {
*(.data)
*(.data.*)
}
. = ALIGN(4);
__u_boot_cmd_start = .;
__u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data);
.u_boot_cmd : AT(__u_boot_cmd_lma) {
.u_boot_cmd : {
KEEP(*(.u_boot_cmd))
}
__u_boot_cmd_end = .;
. = ALIGN(4);
_got = .;
.got : {
*(.got)
}
_egot = .;
. = ALIGN(8);
_edata = .;
__edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start);
.bss : AT(__edata_lma) {
.bss : {
*(.bss)
*(.bss.*)
}

41
board/stamp/Makefile → board/bf533-ezkit/Makefile
View File

@ -1,7 +1,7 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005 blackfin.uclinux.org
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -25,41 +25,28 @@
# MA 02111-1307 USA
#
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o stamp.o
COBJS := $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################

30
board/ezkit533/ezkit533.c → board/bf533-ezkit/bf533-ezkit.c
View File

@ -1,7 +1,7 @@
/*
* U-boot - ezkit533.c
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
@ -30,24 +30,28 @@
#include "psd4256.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
#if (BFIN_CPU == ADSP_BF531)
printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
#elif (BFIN_CPU == ADSP_BF532)
printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
#else
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
#endif
printf("Board: ADI BF533 EZ-Kit Lite board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
printf(" Richard Klingler <richard@uclinux.net>\n");
return 0;
}
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
brate = simple_strtoul(tmp, NULL, 16);
printf("Serial Port initialized with Baud rate = %x\n",brate);
printf("Serial Port initialized with Baud rate = %x\n", brate);
printf("SDRAM attributes:\n");
printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
@ -64,9 +68,13 @@ long int initdram(int board_type)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
/* Set direction bits for Video en/decoder reset as output */
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
/* Deactivate Video en/decoder reset lines */
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
/* Set direction bits for Video en/decoder reset as output */
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) =
PSDA_VDEC_RST | PSDA_VENC_RST;
/* Deactivate Video en/decoder reset lines */
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) =
PSDA_VDEC_RST | PSDA_VENC_RST;
return 0;
}
#endif

25
board/bf533-ezkit/config.mk Normal file
View File

@ -0,0 +1,25 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
TEXT_BASE = 0x01FC0000

14
board/ezkit533/flash-defines.h → board/bf533-ezkit/flash-defines.h
View File

@ -1,7 +1,7 @@
/*
* U-boot - flash-defines.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __FLASHDEFINES_H__
@ -52,19 +52,15 @@
#define CFG_FLASH0_BASE 0x20000000
#define RESET_VAL 0xF0
asm("#define FLASH_START_L 0x0000");
asm("#define FLASH_START_H 0x2000");
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
int get_codes(void);
int poll_toggle_bit(long lOffset);
void reset_flash(void);
int erase_flash(void);
int erase_block_flash(int,unsigned long);
int erase_block_flash(int, unsigned long);
void unlock_flash(long lOffset);
int write_data(long lStart, long lCount, long lStride, int *pnData);
int write_data(long lStart, long lCount, uchar *pnData);
int FillData(long lStart, long lCount, long lStride, int *pnData);
int read_data(long lStart, long lCount, long lStride, int *pnData);
int read_flash(long nOffset, int *pnValue);

201
board/ezkit533/flash.c → board/bf533-ezkit/flash.c
View File

@ -1,7 +1,7 @@
/*
* U-boot - flash.c Flash driver for PSD4256GV
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
*
* (C) Copyright 2000-2004
@ -22,10 +22,11 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <asm/io.h>
#include "flash-defines.h"
void flash_reset(void)
@ -33,14 +34,13 @@ void flash_reset(void)
reset_flash();
}
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
int bank_flag)
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
{
int id = 0, i = 0;
static int FlagDev = 1;
id = get_codes();
if(FlagDev) {
if (FlagDev) {
#ifdef DEBUG
printf("Device ID of the Flash is %x\n", id);
#endif
@ -100,10 +100,11 @@ unsigned long flash_init(void)
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 >> 20);
size_b0, size_b0 >> 20);
}
(void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH0_BASE,
(flash_info[0].start[2] - 1), &flash_info[0]);
return (size_b0 + size_b1 + size_b2);
}
@ -122,15 +123,14 @@ void flash_print_info(flash_info_t * info)
printf("ST Microelectronics ");
break;
default:
printf("Unknown Vendor ");
printf("Unknown Vendor: (0x%08X) ", info->flash_id);
break;
}
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
return;
@ -138,8 +138,8 @@ void flash_print_info(flash_info_t * info)
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int cnt = 0,i;
int prot,sect;
int cnt = 0, i;
int prot, sect;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
@ -148,15 +148,16 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
}
if (prot)
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
else
printf ("\n");
printf("\n");
cnt = s_last - s_first + 1;
if (cnt == FLASH_TOT_SECT) {
printf("Erasing flash, Please Wait \n");
if(erase_flash() < 0) {
if (erase_flash() < 0) {
printf("Erasing flash failed \n");
return FLASH_FAIL;
}
@ -164,7 +165,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
printf("Erasing Flash locations, Please Wait\n");
for (i = s_first; i <= s_last; i++) {
if (info->protect[i] == 0) { /* not protected */
if(erase_block_flash(i, info->start[i]) < 0) {
if (erase_block_flash(i, info->start[i]) < 0) {
printf("Error Sector erasing \n");
return FLASH_FAIL;
}
@ -177,60 +178,66 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int ret;
ret = write_data(addr, cnt, 1, (int *) src);
if(ret == FLASH_FAIL)
int d;
if (addr % 2) {
read_flash(addr - 1 - CFG_FLASH_BASE, &d);
d = (int)((d & 0x00FF) | (*src++ << 8));
ret = write_data(addr - 1, 2, (uchar *) & d);
if (ret == FLASH_FAIL)
return ERR_NOT_ERASED;
ret = write_data(addr + 1, cnt - 1, src);
} else
ret = write_data(addr, cnt, src);
if (ret == FLASH_FAIL)
return ERR_NOT_ERASED;
return FLASH_SUCCESS;
}
int write_data(long lStart, long lCount, long lStride, int *pnData)
int write_data(long lStart, long lCount, uchar * pnData)
{
long i = 0;
int j = 0;
unsigned long ulOffset = lStart - CFG_FLASH_BASE;
int d;
int iShift = 0;
int iNumWords = 2;
int nLeftover = lCount % 4;
int nSector = 0;
int flag = 0;
for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
for (iShift = 0, j = 0; (j < iNumWords);
j++, ulOffset += (lStride * 2)) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND)) {
printf("Invalid locations, Try writing to another location \n");
return FLASH_FAIL;
}
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset,&d);
if(d != 0xffff) {
printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
iShift += 16;
}
if (lCount % 2) {
flag = 1;
lCount = lCount - 1;
}
if (nLeftover > 0) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset,&d);
if(d != 0xffff) {
printf("Flash already programmed. Please erase to reprogram \n");
printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
if(write_flash(ulOffset, pnData[i]) < 0) {
d = (int)(pnData[i] | pnData[i + 1] << 8);
write_flash(ulOffset, d);
if (poll_toggle_bit(ulOffset) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
if ((i > 0) && (!(i % AFP_SectorSize2)))
printf(".");
}
if (flag) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
d = (int)(pnData[i] | (d & 0xFF00));
write_flash(ulOffset, d);
if (poll_toggle_bit(ulOffset) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
@ -252,8 +259,8 @@ int read_data(long ulStart, long lCount, long lStride, int *pnData)
for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
for (iShift = 0, j = 0; j < iNumWords; j += 2) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &nLow);
@ -265,8 +272,8 @@ int read_data(long ulStart, long lCount, long lStride, int *pnData)
}
if (nLeftover > 0) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &pnData[i]);
@ -279,10 +286,10 @@ int write_flash(long nOffset, int nValue)
long addr;
addr = (CFG_FLASH_BASE + nOffset);
asm("ssync;");
*(unsigned volatile short *) addr = nValue;
asm("ssync;");
if(poll_toggle_bit(nOffset) < 0)
sync();
*(unsigned volatile short *)addr = nValue;
sync();
if (poll_toggle_bit(nOffset) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
}
@ -294,29 +301,30 @@ int read_flash(long nOffset, int *pnValue)
if (nOffset != 0x2)
reset_flash();
asm("ssync;");
nValue = *(volatile unsigned short *) addr;
asm("ssync;");
sync();
nValue = *(volatile unsigned short *)addr;
sync();
*pnValue = nValue;
return TRUE;
}
int poll_toggle_bit(long lOffset)
{
unsigned int u1,u2;
unsigned int u1, u2;
unsigned long timeout = 0xFFFFFFFF;
volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
while(1) {
if(timeout < 0)
volatile unsigned long *FB =
(volatile unsigned long *)(0x20000000 + lOffset);
while (1) {
if (timeout < 0)
break;
u1 = *(volatile unsigned short *)FB;
u2 = *(volatile unsigned short *)FB;
if((u1 & 0x0040) == (u2 & 0x0040))
if ((u1 & 0x0040) == (u2 & 0x0040))
return FLASH_SUCCESS;
if((u2 & 0x0020) == 0x0000)
if ((u2 & 0x0020) == 0x0000)
continue;
u1 = *(volatile unsigned short *)FB;
if((u2 & 0x0040) == (u1 & 0x0040))
if ((u2 & 0x0040) == (u1 & 0x0040))
return FLASH_SUCCESS;
else {
reset_flash();
@ -325,7 +333,8 @@ int poll_toggle_bit(long lOffset)
timeout--;
}
printf("Time out occured \n");
if(timeout <0) return FLASH_FAIL;
if (timeout < 0)
return FLASH_FAIL;
}
void reset_flash(void)
@ -344,7 +353,7 @@ int erase_flash(void)
write_flash(WRITESEQ5, WRITEDATA5);
write_flash(WRITESEQ6, WRITEDATA6);
if(poll_toggle_bit(0x0000) < 0)
if (poll_toggle_bit(0x0000) < 0)
return FLASH_FAIL;
write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
@ -354,7 +363,7 @@ int erase_flash(void)
write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
if(poll_toggle_bit(SecFlashASec1Off) < 0)
if (poll_toggle_bit(SecFlashASec1Off) < 0)
return FLASH_FAIL;
write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
@ -364,7 +373,7 @@ int erase_flash(void)
write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
if(poll_toggle_bit(PriFlashBOff) <0)
if (poll_toggle_bit(PriFlashBOff) < 0)
return FLASH_FAIL;
write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
@ -374,7 +383,7 @@ int erase_flash(void)
write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
if(poll_toggle_bit(SecFlashBOff) < 0)
if (poll_toggle_bit(SecFlashBOff) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
@ -397,7 +406,7 @@ int erase_block_flash(int nBlock, unsigned long address)
write_flash(ulSectorOff, BlockEraseVal);
if(poll_toggle_bit(ulSectorOff) < 0)
if (poll_toggle_bit(ulSectorOff) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
@ -435,34 +444,34 @@ void get_sector_number(long ulOffset, int *pnSector)
if (ulOffset >= SecFlashAOff) {
if ((ulOffset < SecFlashASec1Off)
&& (ulOffset < SecFlashASec2Off)) {
nSector = SECT32;
&& (ulOffset < SecFlashASec2Off)) {
nSector = SECT32;
} else if ((ulOffset >= SecFlashASec2Off)
&& (ulOffset < SecFlashASec3Off)) {
nSector = SECT33;
&& (ulOffset < SecFlashASec3Off)) {
nSector = SECT33;
} else if ((ulOffset >= SecFlashASec3Off)
&& (ulOffset < SecFlashASec4Off)) {
nSector = SECT34;
&& (ulOffset < SecFlashASec4Off)) {
nSector = SECT34;
} else if ((ulOffset >= SecFlashASec4Off)
&& (ulOffset < SecFlashAEndOff)) {
nSector = SECT35;
&& (ulOffset < SecFlashAEndOff)) {
nSector = SECT35;
}
} else if (ulOffset >= SecFlashBOff) {
if ((ulOffset < SecFlashBSec1Off)
&& (ulOffset < SecFlashBSec2Off)) {
nSector = SECT36;
&& (ulOffset < SecFlashBSec2Off)) {
nSector = SECT36;
}
if ((ulOffset < SecFlashBSec2Off)
&& (ulOffset < SecFlashBSec3Off)) {
nSector = SECT37;
&& (ulOffset < SecFlashBSec3Off)) {
nSector = SECT37;
}
if ((ulOffset < SecFlashBSec3Off)
&& (ulOffset < SecFlashBSec4Off)) {
nSector = SECT38;
&& (ulOffset < SecFlashBSec4Off)) {
nSector = SECT38;
}
if ((ulOffset < SecFlashBSec4Off)
&& (ulOffset < SecFlashBEndOff)) {
nSector = SECT39;
&& (ulOffset < SecFlashBEndOff)) {
nSector = SECT39;
}
} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
nSector = ulOffset & 0xffff0000;

28
board/ezkit533/psd4256.h → board/bf533-ezkit/psd4256.h
View File

@ -1,7 +1,7 @@
/*
* U-boot - psd4256.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/*
@ -49,19 +49,19 @@
* Flash A Port A Bit definitions
*/
#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */
#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */
#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */
#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */
#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */
#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */
#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */
#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */
#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */
#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */
/*
* Flash A Port B Bit definitions
*/
#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */
#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */
#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */
#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */
#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */
#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */
#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */
#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */

16
board/ezkit533/u-boot.lds → board/bf533-ezkit/u-boot.lds.S
View File

@ -1,7 +1,7 @@
/*
* U-boot - u-boot.lds
* U-boot - u-boot.lds.S
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -25,6 +25,8 @@
* MA 02111-1307 USA
*/
#include <config.h>
OUTPUT_ARCH(bfin)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
@ -55,6 +57,7 @@ SECTIONS
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
. = CFG_MONITOR_BASE;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
@ -68,10 +71,11 @@ SECTIONS
cpu/bf533/interrupt.o (.text)
cpu/bf533/serial.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
/* lib_blackfin/bf533_string.o (.text) */
/* lib_generic/vsprintf.o (.text) */
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
board/ezkit533/ezkit533.o (.text)
board/bf533-ezkit/bf533-ezkit.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
@ -119,9 +123,9 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
___u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
___u_boot_cmd_end = .;
__start___ex_table = .;

58
board/bf533-stamp/Makefile Normal file
View File

@ -0,0 +1,58 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o spi.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

142
board/stamp/stamp.c → board/bf533-stamp/bf533-stamp.c
View File

@ -1,7 +1,7 @@
/*
* U-boot - stamp.c STAMP board specific routines
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,15 +21,14 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <asm/mem_init.h>
#include "stamp.h"
DECLARE_GLOBAL_DATA_PTR;
#include <asm/io.h>
#include "bf533-stamp.h"
#define STATUS_LED_OFF 0
#define STATUS_LED_ON 1
@ -40,42 +39,45 @@ DECLARE_GLOBAL_DATA_PTR;
# define SHOW_BOOT_PROGRESS(arg)
#endif
int checkboard (void)
int checkboard(void)
{
printf ("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
printf ("Board: ADI BF533 Stamp board\n");
printf (" Support: http://blackfin.uclinux.org/\n");
printf (" Richard Klingler <richard@uclinux.net>\n");
#if (BFIN_CPU == ADSP_BF531)
printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
#elif (BFIN_CPU == ADSP_BF532)
printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
#else
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
#endif
printf("Board: ADI BF533 Stamp board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
return 0;
}
long int initdram (int board_type)
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
printf ("SDRAM attributes:\n");
printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
"CAS Latency:%d cycles\n",
(SDRAM_tRCD >> 15),
(SDRAM_tRP >> 11),
(SDRAM_tRAS >> 6),
(SDRAM_tWR >> 19),
(SDRAM_CL >> 2));
printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf ("Bank size = %d MB\n", 128);
printf("SDRAM attributes:\n");
printf
(" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
"CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
(SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf("Bank size = %d MB\n", 128);
#endif
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
return (gd->bd->bi_memsize);
}
void swap_to (int device_id)
void swap_to(int device_id)
{
if (device_id == ETHERNET) {
*pFIO_DIR = PF0;
asm ("ssync;");
sync();
*pFIO_FLAG_S = PF0;
asm ("ssync;");
sync();
} else if (device_id == FLASH) {
*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
*pFIO_FLAG_S = (PF4 | PF3 | PF2);
@ -85,9 +87,9 @@ void swap_to (int device_id)
*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
*pFIO_FLAG_D = (PF4 | PF3 | PF2);
asm ("ssync;");
sync();
} else {
printf ("Unknown bank to switch\n");
printf("Unknown bank to switch\n");
}
return;
@ -95,7 +97,7 @@ void swap_to (int device_id)
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
int misc_init_r (void)
int misc_init_r(void)
{
int i;
int cf_stat = 0;
@ -104,7 +106,7 @@ int misc_init_r (void)
*pFIO_EDGE = FIO_EDGE_CF_BITS;
*pFIO_POLAR = FIO_POLAR_CF_BITS;
for (i = 0; i < 0x300; i++)
asm ("nop;");
asm("nop;");
if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
cf_stat = 0;
@ -115,37 +117,36 @@ int misc_init_r (void)
*pFIO_EDGE = FIO_EDGE_BITS;
*pFIO_POLAR = FIO_POLAR_BITS;
if (cf_stat) {
printf ("Booting from COMPACT flash\n");
printf("Booting from COMPACT flash\n");
/* Set cycle time for CF */
*(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
*(volatile unsigned long *)ambctl1 = CF_AMBCTL1VAL;
for (i = 0; i < 0x1000; i++)
asm ("nop;");
asm("nop;");
for (i = 0; i < 0x1000; i++)
asm ("nop;");
asm("nop;");
for (i = 0; i < 0x1000; i++)
asm ("nop;");
asm("nop;");
serial_setbrg ();
ide_init ();
serial_setbrg();
ide_init();
setenv ("bootargs", "");
setenv ("bootcmd",
"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
setenv("bootargs", "");
setenv("bootcmd",
"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
} else {
printf ("Booting from FLASH\n");
printf("Booting from FLASH\n");
}
return 1;
return 0;
}
#endif
#ifdef CONFIG_STAMP_CF
void cf_outb (unsigned char val, volatile unsigned char *addr)
void cf_outb(unsigned char val, volatile unsigned char *addr)
{
/*
* Set PF1 PF0 respectively to 0 1 to divert address
@ -153,70 +154,70 @@ void cf_outb (unsigned char val, volatile unsigned char *addr)
*/
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
asm ("ssync;");
sync();
*(addr) = val;
asm ("ssync;");
sync();
/* Setback PF1 PF0 to 0 0 to address external
* memory banks */
*(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
asm ("ssync;");
*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
sync();
}
unsigned char cf_inb (volatile unsigned char *addr)
unsigned char cf_inb(volatile unsigned char *addr)
{
volatile unsigned char c;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
asm ("ssync;");
sync();
c = *(addr);
asm ("ssync;");
sync();
*pFIO_FLAG_C = CF_PF1_PF0;
asm ("ssync;");
sync();
return c;
}
void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
{
int i;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
asm ("ssync;");
sync();
for (i = 0; i < words; i++) {
*(sect_buf + i) = *(addr);
asm ("ssync;");
sync();
}
*pFIO_FLAG_C = CF_PF1_PF0;
asm ("ssync;");
sync();
}
void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
{
int i;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
asm ("ssync;");
sync();
for (i = 0; i < words; i++) {
*(addr) = *(sect_buf + i);
asm ("ssync;");
sync();
}
*pFIO_FLAG_C = CF_PF1_PF0;
asm ("ssync;");
sync();
}
#endif
void stamp_led_set (int LED1, int LED2, int LED3)
void stamp_led_set(int LED1, int LED2, int LED3)
{
*pFIO_INEN &= ~(PF2 | PF3 | PF4);
*pFIO_DIR |= (PF2 | PF3 | PF4);
@ -233,31 +234,31 @@ void stamp_led_set (int LED1, int LED2, int LED3)
*pFIO_FLAG_S = PF4;
else
*pFIO_FLAG_C = PF4;
asm ("ssync;");
sync();
}
void show_boot_progress (int status)
void show_boot_progress(int status)
{
switch (status) {
case 1:
stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
break;
case 2:
stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
break;
case 3:
stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
break;
case 4:
stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
break;
case 5:
case 6:
stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
break;
case 7:
case 8:
stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
break;
case 9:
case 10:
@ -266,11 +267,10 @@ void show_boot_progress (int status)
case 13:
case 14:
case 15:
stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
STATUS_LED_OFF);
stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
break;
default:
stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
break;
}
}

7
board/stamp/stamp.h → board/bf533-stamp/bf533-stamp.h
View File

@ -1,7 +1,7 @@
/*
* U-boot - stamp.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __STAMP_H__
@ -36,7 +36,6 @@ extern volatile unsigned long *amgctl;
extern unsigned long pll_div_fact;
extern void serial_setbrg(void);
extern void pll_set(int vco, int crystal_frq, int pll_div);
/* Definitions used in Compact Flash Boot support */
#define FIO_EDGE_CF_BITS 0x0000

4
board/stamp/config.mk → board/bf533-stamp/config.mk
View File

@ -20,6 +20,6 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
TEXT_BASE = 0x07FC0000
PLATFORM_CPPFLAGS += -I$(TOPDIR)

473
board/bf533-stamp/spi.c Normal file
View File

@ -0,0 +1,473 @@
/****************************************************************************
* SPI flash driver for M25P64
****************************************************************************/
#include <common.h>
#include <linux/ctype.h>
#include <asm/io.h>
#if defined(CONFIG_SPI)
/*Application definitions */
#define NUM_SECTORS 128 /* number of sectors */
#define SECTOR_SIZE 0x10000
#define NOP_NUM 1000
#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /*Settings to the SPI_CTL */
#define TIMOD01 (0x01) /*stes the SPI to work with core instructions */
/*Flash commands */
#define SPI_WREN (0x06) /*Set Write Enable Latch */
#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
#define SPI_RDSR (0x05) /*Read Status Register */
#define SPI_WRSR (0x01) /*Write Status Register */
#define SPI_READ (0x03) /*Read data from memory */
#define SPI_PP (0x02) /*Program Data into memory */
#define SPI_SE (0xD8) /*Erase one sector in memory */
#define SPI_BE (0xC7) /*Erase all memory */
#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
#define WEL (0x2) /*Check the write enable bit of the SPI status register */
#define TIMEOUT 350000000
typedef enum {
NO_ERR,
POLL_TIMEOUT,
INVALID_SECTOR,
INVALID_BLOCK,
} ERROR_CODE;
void spi_init_f(void);
void spi_init_r(void);
ssize_t spi_read(uchar *, int, uchar *, int);
ssize_t spi_write(uchar *, int, uchar *, int);
char ReadStatusRegister(void);
void Wait_For_SPIF(void);
void SetupSPI(const int spi_setting);
void SPI_OFF(void);
void SendSingleCommand(const int iCommand);
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
ERROR_CODE EraseBlock(int nBlock);
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
ERROR_CODE Wait_For_Status(char Statusbit);
ERROR_CODE Wait_For_WEL(void);
/* -------------------
* Variables
* ------------------- */
/* **************************************************************************
*
* Function: spi_init_f
*
* Description: Init SPI-Controller (ROM part)
*
* return: ---
*
* *********************************************************************** */
void spi_init_f(void)
{
}
/* **************************************************************************
*
* Function: spi_init_r
*
* Description: Init SPI-Controller (RAM part) -
* The malloc engine is ready and we can move our buffers to
* normal RAM
*
* return: ---
*
* *********************************************************************** */
void spi_init_r(void)
{
return;
}
/****************************************************************************
* Function: spi_write
**************************************************************************** */
ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
{
unsigned long offset;
int start_block, end_block;
int start_byte, end_byte;
ERROR_CODE result = NO_ERR;
uchar temp[SECTOR_SIZE];
int i, num;
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
/* Get the start block number */
result = GetSectorNumber(offset, &start_block);
if (result == INVALID_SECTOR) {
printf("Invalid sector! ");
return 0;
}
/* Get the end block number */
result = GetSectorNumber(offset + len - 1, &end_block);
if (result == INVALID_SECTOR) {
printf("Invalid sector! ");
return 0;
}
for (num = start_block; num <= end_block; num++) {
ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
start_byte = num * SECTOR_SIZE;
end_byte = (num + 1) * SECTOR_SIZE - 1;
if (start_byte < offset)
start_byte = offset;
if (end_byte > (offset + len))
end_byte = (offset + len - 1);
for (i = start_byte; i <= end_byte; i++)
temp[i - num * SECTOR_SIZE] = buffer[i - offset];
EraseBlock(num);
result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
if (result != NO_ERR)
return 0;
printf(".");
}
return len;
}
/****************************************************************************
* Function: spi_read
**************************************************************************** */
ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
{
unsigned long offset;
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
ReadData(offset, len, (int *)buffer);
return len;
}
void SendSingleCommand(const int iCommand)
{
unsigned short dummy;
/*turns on the SPI in single write mode */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
/*sends the actual command to the SPI TX register */
*pSPI_TDBR = iCommand;
sync();
/*The SPI status register will be polled to check the SPIF bit */
Wait_For_SPIF();
dummy = *pSPI_RDBR;
/*The SPI will be turned off */
SPI_OFF();
}
void SetupSPI(const int spi_setting)
{
if (icache_status() || dcache_status())
udelay(CONFIG_CCLK_HZ / 50000000);
/*sets up the PF2 to be the slave select of the SPI */
*pSPI_FLG = 0xFB04;
*pSPI_BAUD = CONFIG_SPI_BAUD;
*pSPI_CTL = spi_setting;
sync();
}
void SPI_OFF(void)
{
*pSPI_CTL = 0x0400; /* disable SPI */
*pSPI_FLG = 0;
*pSPI_BAUD = 0;
sync();
udelay(CONFIG_CCLK_HZ / 50000000);
}
void Wait_For_SPIF(void)
{
unsigned short dummyread;
while ((*pSPI_STAT & TXS)) ;
while (!(*pSPI_STAT & SPIF)) ;
while (!(*pSPI_STAT & RXS)) ;
dummyread = *pSPI_RDBR; /* Read dummy to empty the receive register */
}
ERROR_CODE Wait_For_WEL(void)
{
int i;
char status_register = 0;
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
for (i = 0; i < TIMEOUT; i++) {
status_register = ReadStatusRegister();
if ((status_register & WEL)) {
ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
break;
}
ErrorCode = POLL_TIMEOUT; /* Time out error */
};
return ErrorCode;
}
ERROR_CODE Wait_For_Status(char Statusbit)
{
int i;
char status_register = 0xFF;
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
for (i = 0; i < TIMEOUT; i++) {
status_register = ReadStatusRegister();
if (!(status_register & Statusbit)) {
ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
break;
}
ErrorCode = POLL_TIMEOUT; /* Time out error */
};
return ErrorCode;
}
char ReadStatusRegister(void)
{
char status_register = 0;
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
*pSPI_TDBR = 0; /*send dummy to receive the status register */
sync();
Wait_For_SPIF(); /*wait until the data has been sent */
status_register = *pSPI_RDBR; /*read the status register */
SPI_OFF(); /* Turn off the SPI */
return status_register;
}
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
{
int nSector = 0;
ERROR_CODE ErrorCode = NO_ERR;
if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
ErrorCode = INVALID_SECTOR;
return ErrorCode;
}
nSector = (int)ulOffset / 0x10000;
*pnSector = nSector;
/* ok */
return ErrorCode;
}
ERROR_CODE EraseBlock(int nBlock)
{
unsigned long ulSectorOff = 0x0, ShiftValue;
ERROR_CODE ErrorCode = NO_ERR;
/* if the block is invalid just return */
if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */
return ErrorCode;
}
/* figure out the offset of the block in flash */
if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
ulSectorOff = (nBlock * SECTOR_SIZE);
} else {
ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */
return ErrorCode;
}
/* A write enable instruction must previously have been executed */
SendSingleCommand(SPI_WREN);
/*The status register will be polled to check the write enable latch "WREN" */
ErrorCode = Wait_For_WEL();
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Erase block error\n");
return ErrorCode;
} else
/*Turn on the SPI to send single commands */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
/* Send the erase block command to the flash followed by the 24 address */
/* to point to the start of a sector. */
*pSPI_TDBR = SPI_SE;
sync();
Wait_For_SPIF();
ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */
*pSPI_TDBR = ShiftValue;
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */
*pSPI_TDBR = ShiftValue;
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
*pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
/*Turns off the SPI */
SPI_OFF();
/* Poll the status register to check the Write in Progress bit */
/* Sector erase takes time */
ErrorCode = Wait_For_Status(WIP);
/* block erase should be complete */
return ErrorCode;
}
/*****************************************************************************
* ERROR_CODE ReadData()
*
* Read a value from flash for verify purpose
*
* Inputs: unsigned long ulStart - holds the SPI start address
* int pnData - pointer to store value read from flash
* long lCount - number of elements to read
***************************************************************************** */
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
{
unsigned long ShiftValue;
char *cnData;
int i;
cnData = (char *)pnData; /* Pointer cast to be able to increment byte wise */
/* Start SPI interface */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
*pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
*pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
/* After the SPI device address has been placed on the MOSI pin the data can be */
/* received on the MISO pin. */
for (i = 0; i < lCount; i++) {
*pSPI_TDBR = 0; /*send dummy */
sync();
while (!(*pSPI_STAT & RXS)) ;
*cnData++ = *pSPI_RDBR; /*read */
if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
printf(".");
}
SPI_OFF(); /* Turn off the SPI */
return NO_ERR;
}
ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
int *iDataSource, long *lWriteCount)
{
unsigned long ulWAddr;
long lWTransferCount = 0;
int i;
char iData;
char *temp = (char *)iDataSource;
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
/* First, a Write Enable Command must be sent to the SPI. */
SendSingleCommand(SPI_WREN);
/* Second, the SPI Status Register will be tested whether the */
/* Write Enable Bit has been set. */
ErrorCode = Wait_For_WEL();
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Write Time Out\n");
return ErrorCode;
} else
/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */
*pSPI_TDBR = SPI_PP;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = (ulStartAddr >> 16);
*pSPI_TDBR = ulWAddr;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = (ulStartAddr >> 8);
*pSPI_TDBR = ulWAddr;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = ulStartAddr;
*pSPI_TDBR = ulWAddr;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
/* and sent to the SPI device. */
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
iData = *temp;
*pSPI_TDBR = iData;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
temp++;
}
SPI_OFF(); /* Turns the SPI off */
/* Sixth, the SPI Write in Progress Bit must be toggled to ensure the */
/* programming is done before start of next transfer. */
ErrorCode = Wait_For_Status(WIP);
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Program Time out!\n");
return ErrorCode;
} else
*lWriteCount = lWTransferCount;
return ErrorCode;
}
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
{
unsigned long ulWStart = ulStart;
long lWCount = lCount, lWriteCount;
long *pnWriteCount = &lWriteCount;
ERROR_CODE ErrorCode = NO_ERR;
while (lWCount != 0) {
ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
/* After each function call of WriteFlash the counter must be adjusted */
lWCount -= *pnWriteCount;
/* Also, both address pointers must be recalculated. */
ulWStart += *pnWriteCount;
pnData += *pnWriteCount / 4;
}
/* return the appropriate error code */
return ErrorCode;
}
#endif /* CONFIG_SPI */

17
board/stamp/u-boot.lds → board/bf533-stamp/u-boot.lds.S
View File

@ -1,7 +1,7 @@
/*
* U-boot - u-boot.lds
* U-boot - u-boot.lds.S
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -25,6 +25,8 @@
* MA 02111-1307 USA
*/
#include <config.h>
OUTPUT_ARCH(bfin)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
@ -55,6 +57,7 @@ SECTIONS
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
. = CFG_MONITOR_BASE;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
@ -68,9 +71,11 @@ SECTIONS
cpu/bf533/interrupt.o (.text)
cpu/bf533/serial.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
/* lib_blackfin/bf533_string.o (.text) */
/* lib_generic/vsprintf.o (.text) */
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
/* lib_generic/zlib.o (.text) */
/* board/stamp/stamp.o (.text) */
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
@ -118,9 +123,9 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
___u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
___u_boot_cmd_end = .;
__start___ex_table = .;

58
board/bf537-stamp/Makefile Normal file
View File

@ -0,0 +1,58 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o flash.o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

437
board/bf537-stamp/bf537-stamp.c Normal file
View File

@ -0,0 +1,437 @@
/*
* U-boot - BF537.c
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
#include <asm/io.h>
#include "ether_bf537.h"
#define POST_WORD_ADDR 0xFF903FFC
/*
* the bootldr command loads an address, checks to see if there
* is a Boot stream that the on-chip BOOTROM can understand,
* and loads it via the BOOTROM Callback. It is possible
* to also add booting from SPI, or TWI, but this function does
* not currently support that.
*/
int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong addr, entry;
ulong *data;
/* Get the address */
if (argc < 2) {
addr = load_addr;
} else {
addr = simple_strtoul(argv[1], NULL, 16);
}
/* Check if it is a LDR file */
data = (ulong *) addr;
if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) {
/* We want to boot from FLASH or SDRAM */
entry = _BOOTROM_BOOT_DXE_FLASH;
printf("## Booting ldr image at 0x%08lx ...\n", addr);
if (icache_status())
icache_disable();
if (dcache_status())
dcache_disable();
__asm__("R7=%[a];\n" "P0=%[b];\n" "JUMP (P0);\n":
:[a] "d"(addr),[b] "a"(entry)
:"R7", "P0");
} else {
printf("## No ldr image at address 0x%08lx\n", addr);
}
return 0;
}
U_BOOT_CMD(bootldr, 2, 0, do_bootldr,
"bootldr - boot ldr image from memory\n",
"[addr]\n - boot ldr image stored in memory\n");
int checkboard(void)
{
#if (BFIN_CPU == ADSP_BF534)
printf("CPU: ADSP BF534 Rev.: 0.%d\n", *pCHIPID >> 28);
#elif (BFIN_CPU == ADSP_BF536)
printf("CPU: ADSP BF536 Rev.: 0.%d\n", *pCHIPID >> 28);
#else
printf("CPU: ADSP BF537 Rev.: 0.%d\n", *pCHIPID >> 28);
#endif
printf("Board: ADI BF537 stamp board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
return 0;
}
#if defined(CONFIG_BFIN_IDE)
void cf_outb(unsigned char val, volatile unsigned char *addr)
{
*(addr) = val;
sync();
}
unsigned char cf_inb(volatile unsigned char *addr)
{
volatile unsigned char c;
c = *(addr);
sync();
return c;
}
void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
{
int i;
for (i = 0; i < words; i++)
*(sect_buf + i) = *(addr);
sync();
}
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
{
int i;
for (i = 0; i < words; i++)
*(addr) = *(sect_buf + i);
sync();
}
#endif /* CONFIG_BFIN_IDE */
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
brate = simple_strtoul(tmp, NULL, 16);
printf("Serial Port initialized with Baud rate = %x\n", brate);
printf("SDRAM attributes:\n");
printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
3, 3, 6, 2, 3);
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
#endif
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
return CFG_MAX_RAM_SIZE;
}
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
char nid[32];
unsigned char *pMACaddr = (unsigned char *)0x203F0000;
u8 SrcAddr[6] = { 0x02, 0x80, 0xAD, 0x20, 0x31, 0xB8 };
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/* The 0xFF check here is to make sure we don't use the address
* in flash if it's simply been erased (aka all 0xFF values) */
if (getenv("ethaddr") == NULL && is_valid_ether_addr(pMACaddr)) {
sprintf(nid, "%02x:%02x:%02x:%02x:%02x:%02x",
pMACaddr[0], pMACaddr[1],
pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]);
setenv("ethaddr", nid);
}
if (getenv("ethaddr")) {
SetupMacAddr(SrcAddr);
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */
#if defined(CONFIG_BFIN_IDE)
#if defined(CONFIG_BFIN_TRUE_IDE)
/* Enable ATASEL when in True IDE mode */
printf("Using CF True IDE Mode\n");
cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
udelay(1000);
#elif defined(CONFIG_BFIN_CF_IDE)
/* Disable ATASEL when we're in Common Memory Mode */
printf("Using CF Common Memory Mode\n");
cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
udelay(1000);
#elif defined(CONFIG_BFIN_HDD_IDE)
printf("Using HDD IDE Mode\n");
#endif
ide_init();
#endif /* CONFIG_BFIN_IDE */
return 0;
}
#endif /* CONFIG_MISC_INIT_R */
#ifdef CONFIG_POST
#if (BFIN_BOOT_MODE != BF537_BYPASS_BOOT)
/* Using sw10-PF5 as the hotkey */
int post_hotkeys_pressed(void)
{
return 0;
}
#else
/* Using sw10-PF5 as the hotkey */
int post_hotkeys_pressed(void)
{
int delay = 3;
int i;
unsigned short value;
*pPORTF_FER &= ~PF5;
*pPORTFIO_DIR &= ~PF5;
*pPORTFIO_INEN |= PF5;
printf("########Press SW10 to enter Memory POST########: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF5;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
printf("\b\b\b 0");
printf("\n");
if (value == 0)
return 0;
else {
printf("Hotkey has been pressed, Enter POST . . . . . .\n");
return 1;
}
}
#endif
#endif
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
void post_word_store(ulong a)
{
volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
*save_addr = a;
}
ulong post_word_load(void)
{
volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
return *save_addr;
}
#endif
#ifdef CONFIG_POST
int uart_post_test(int flags)
{
return 0;
}
#define BLOCK_SIZE 0x10000
#define VERIFY_ADDR 0x2000000
extern int erase_block_flash(int);
extern int write_data(long lStart, long lCount, uchar * pnData);
int flash_post_test(int flags)
{
unsigned short *pbuf, *temp;
int offset, n, i;
int value = 0;
int result = 0;
printf("\n");
pbuf = (unsigned short *)VERIFY_ADDR;
temp = pbuf;
for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
offset = (n - 7) * BLOCK_SIZE;
printf("--------Erase block:%2d..", n);
erase_block_flash(n);
printf("OK\r");
printf("--------Program block:%2d...", n);
write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
printf("OK\r");
printf("--------Verify block:%2d...", n);
for (i = 0; i < BLOCK_SIZE; i += 2) {
if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
*temp++) {
value = 1;
result = 1;
}
}
if (value)
printf("failed\n");
else
printf("OK %3d%%\r",
(int)(
(n + 1 -
FLASH_START_POST_BLOCK) *
100 / (FLASH_END_POST_BLOCK -
FLASH_START_POST_BLOCK)));
temp = pbuf;
value = 0;
}
printf("\n");
if (result)
return -1;
else
return 0;
}
/****************************************************
* LED1 ---- PF6 LED2 ---- PF7 *
* LED3 ---- PF8 LED4 ---- PF9 *
* LED5 ---- PF10 LED6 ---- PF11 *
****************************************************/
int led_post_test(int flags)
{
*pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
*pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
*pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
*pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
udelay(1000000);
printf("LED1 on");
*pPORTFIO |= PF6;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("LED2 on");
*pPORTFIO |= PF7;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("LED3 on");
*pPORTFIO |= PF8;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("LED4 on");
*pPORTFIO |= PF9;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("LED5 on");
*pPORTFIO |= PF10;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("lED6 on");
*pPORTFIO |= PF11;
printf("\b\b\b\b\b\b\b ");
return 0;
}
/************************************************
* SW10 ---- PF5 SW11 ---- PF4 *
* SW12 ---- PF3 SW13 ---- PF2 *
************************************************/
int button_post_test(int flags)
{
int i, delay = 5;
unsigned short value = 0;
int result = 0;
*pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
*pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
*pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
printf("\n--------Press SW10: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF5;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
if (value != 0)
printf("\b\bOK");
else {
result = -1;
printf("\b\bfailed");
}
delay = 5;
printf("\n--------Press SW11: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF4;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
if (value != 0)
printf("\b\bOK");
else {
result = -1;
printf("\b\bfailed");
}
delay = 5;
printf("\n--------Press SW12: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF3;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
if (value != 0)
printf("\b\bOK");
else {
result = -1;
printf("\b\bfailed");
}
delay = 5;
printf("\n--------Press SW13: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF2;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
if (value != 0)
printf("\b\bOK");
else {
result = -1;
printf("\b\bfailed");
}
printf("\n");
return result;
}
#endif

201
board/bf537-stamp/cmd_bf537led.c Normal file
View File

@ -0,0 +1,201 @@
/*
* U-boot - cmd_bf537led.c
*
* Copyright (C) 2006 Aaron Gage, Ocean Optics Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
#include <asm-blackfin/string.h>
#ifdef CONFIG_BF537_STAMP_LEDCMD
/* Define the command usage in a reusable way */
#define USAGE_LONG \
"led <number> <action>\n" \
" <number> - Index (0-5) of LED to change, or \"all\"\n" \
" <action> - Must be one of:\n" \
" on off toggle\n"
/* Number of LEDs supported by the board */
#define NUMBER_LEDS 6
/* The BF537 stamp has 6 LEDs. This mask indicates that all should be lit. */
#define LED_ALL_MASK 0x003F
void show_cmd_usage(void);
void set_led_state(int index, int state);
void configure_GPIO_to_output(int index);
/* Map of LEDs according to their GPIO ports. This can be rearranged or
* otherwise changed to account for different GPIO configurations.
*/
int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 };
#define ACTION_TOGGLE -1
#define ACTION_OFF 0
#define ACTION_ON 1
#define LED_STATE_OFF 0
#define LED_STATE_ON 1
/* This is a trivial atoi implementation since we don't have one available */
int atoi(char *string)
{
int length;
int retval = 0;
int i;
int sign = 1;
length = strlen(string);
for (i = 0; i < length; i++) {
if (0 == i && string[0] == '-') {
sign = -1;
continue;
}
if (string[i] > '9' || string[i] < '0') {
break;
}
retval *= 10;
retval += string[i] - '0';
}
retval *= sign;
return retval;
}
int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int led_mask = 0;
int led_current_state = 0;
int action = ACTION_OFF;
int temp;
if (3 != argc) {
/* Not enough arguments, so just show usage information */
show_cmd_usage();
return 1;
}
if (strcmp(argv[1], "all") == 0) {
led_mask = LED_ALL_MASK;
} else {
temp = atoi(argv[1]);
if (temp < 0 || temp >= NUMBER_LEDS) {
printf("Invalid LED number [%s]\n", argv[1]);
show_cmd_usage();
return 2;
}
led_mask |= (1 << temp);
}
if (strcmp(argv[2], "off") == 0) {
action = ACTION_OFF;
} else if (strcmp(argv[2], "on") == 0) {
action = ACTION_ON;
} else if (strcmp(argv[2], "toggle") == 0) {
action = ACTION_TOGGLE;
} else {
printf("Invalid action [%s]\n", argv[2]);
show_cmd_usage();
return 3;
}
for (temp = 0; temp < NUMBER_LEDS; temp++) {
if ((led_mask & (1 << temp)) > 0) {
/*
* It is possible that the user has wired one of PF6-PF11 to
* something other than an LED, so this will only change a pin
* to output if the user has indicated a state change. This may
* happen a lot, but this way is safer than just setting all pins
* to output.
*/
configure_GPIO_to_output(temp);
led_current_state =
((*pPORTFIO & led_ports[temp]) >
0) ? LED_STATE_ON : LED_STATE_OFF;
/*
printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp],
led_current_state);
printf("*pPORTFIO is %x\n", *pPORTFIO);
*/
if (ACTION_ON == action
|| (ACTION_TOGGLE == action
&& 0 == led_current_state)) {
printf("Turning LED %d on\n", temp);
set_led_state(temp, LED_STATE_ON);
} else {
printf("Turning LED %d off\n", temp);
set_led_state(temp, LED_STATE_OFF);
}
}
}
return 0;
}
/*
* The GPIO pins that go to the LEDs on the BF537 stamp must be configured
* as output. This function simply configures them that way. This could
* be done to all of the GPIO lines at once, but if a user is using a
* custom board, this will try to be nice and only change the GPIO lines
* that the user specifically names.
*/
void configure_GPIO_to_output(int index)
{
int port;
port = led_ports[index];
/* Clear the Port F Function Enable Register */
*pPORTF_FER &= ~port;
/* Set the Port F I/O direction register */
*pPORTFIO_DIR |= port;
/* Clear the Port F I/O Input Enable Register */
*pPORTFIO_INEN &= ~port;
}
/* Enforce the given state on the GPIO line for the indicated LED */
void set_led_state(int index, int state)
{
int port;
port = led_ports[index];
if (LED_STATE_OFF == state) {
/* Clear the bit to turn off the LED */
*pPORTFIO &= ~port;
} else {
/* Set the bit to turn on the LED */
*pPORTFIO |= port;
}
}
/* Display usage information */
void show_cmd_usage()
{
printf("Usage:\n%s", USAGE_LONG);
}
/* Register information for u-boot to find this command */
U_BOOT_CMD(led, 3, 1, do_bf537led,
"led- Control BF537 stamp LEDs\n", USAGE_LONG);
#endif

25
board/bf537-stamp/config.mk Normal file
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#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
TEXT_BASE = 0x03FC0000

545
board/bf537-stamp/ether_bf537.c Normal file
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/*
* ADI Blackfin 537 MAC Ethernet
*
* Copyright (c) 2005 Analog Device, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
#include <net.h>
#include <command.h>
#include <malloc.h>
#include "ether_bf537.h"
#ifdef CONFIG_POST
#include <post.h>
#endif
#undef DEBUG_ETHERNET
#ifdef DEBUG_ETHERNET
#define DEBUGF(fmt,args...) printf(fmt,##args)
#else
#define DEBUGF(fmt,args...)
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define RXBUF_BASE_ADDR 0xFF900000
#define TXBUF_BASE_ADDR 0xFF800000
#define TX_BUF_CNT 1
#define TOUT_LOOP 1000000
ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx; /* index of the current RX buffer */
static u16 rxIdx; /* index of the current TX buffer */
u8 SrcAddr[6];
u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
/* DMAx_CONFIG values at DMA Restart */
const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 };
#if 0
rxdmacfg.b_DMA_EN = 1; /* enabled */
rxdmacfg.b_WNR = 1; /* write to memory */
rxdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
rxdmacfg.b_DMA2D = 0; /* N/A */
rxdmacfg.b_RESTART= 0; /* N/A */
rxdmacfg.b_DI_SEL = 0; /* N/A */
rxdmacfg.b_DI_EN = 0; /* no interrupt */
rxdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
rxdmacfg.b_FLOW = 7; /* large desc flow */
#endif
const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 };
#if 0
txdmacfg.b_DMA_EN = 1; /* enabled */
txdmacfg.b_WNR = 0; /* read from memory */
txdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
txdmacfg.b_DMA2D = 0; /* N/A */
txdmacfg.b_RESTART= 0; /* N/A */
txdmacfg.b_DI_SEL = 0; /* N/A */
txdmacfg.b_DI_EN = 0; /* no interrupt */
txdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
txdmacfg.b_FLOW = 7; /* large desc flow */
#endif
ADI_ETHER_BUFFER *SetupRxBuffer(int no);
ADI_ETHER_BUFFER *SetupTxBuffer(int no);
static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd);
static void bfin_EMAC_halt(struct eth_device *dev);
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
int length);
static int bfin_EMAC_recv(struct eth_device *dev);
int bfin_EMAC_initialize(bd_t * bis)
{
struct eth_device *dev;
dev = (struct eth_device *)malloc(sizeof(*dev));
if (dev == NULL)
hang();
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "BF537 ETHERNET");
dev->iobase = 0;
dev->priv = 0;
dev->init = bfin_EMAC_init;
dev->halt = bfin_EMAC_halt;
dev->send = bfin_EMAC_send;
dev->recv = bfin_EMAC_recv;
eth_register(dev);
return 1;
}
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
int length)
{
int i;
int result = 0;
unsigned int *buf;
buf = (unsigned int *)packet;
if (length <= 0) {
printf("Ethernet: bad packet size: %d\n", length);
goto out;
}
if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
printf("Ethernet: tx DMA error\n");
goto out;
}
for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx time out\n");
goto out;
}
}
txbuf[txIdx]->FrmData->NoBytes = length;
memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
*pEMAC_OPMODE |= TE;
for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx error\n");
goto out;
}
}
result = txbuf[txIdx]->StatusWord;
txbuf[txIdx]->StatusWord = 0;
if ((txIdx + 1) >= TX_BUF_CNT)
txIdx = 0;
else
txIdx++;
out:
DEBUGF("BFIN EMAC send: length = %d\n", length);
return result;
}
static int bfin_EMAC_recv(struct eth_device *dev)
{
int length = 0;
for (;;) {
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
length = -1;
break;
}
if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
printf("Ethernet: rx dma overrun\n");
break;
}
if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
printf("Ethernet: rx error\n");
break;
}
length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
if (length <= 4) {
printf("Ethernet: bad frame\n");
break;
}
NetRxPackets[rxIdx] =
(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
NetReceive(NetRxPackets[rxIdx], length - 4);
*pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
rxbuf[rxIdx]->StatusWord = 0x00000000;
if ((rxIdx + 1) >= PKTBUFSRX)
rxIdx = 0;
else
rxIdx++;
}
return length;
}
/**************************************************************
*
* Ethernet Initialization Routine
*
*************************************************************/
static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd)
{
u32 opmode;
int dat;
int i;
DEBUGF("Eth_init: ......\n");
txIdx = 0;
rxIdx = 0;
/* Initialize System Register */
if (SetupSystemRegs(&dat) < 0)
return -1;
/* Initialize EMAC address */
SetupMacAddr(SrcAddr);
/* Initialize TX and RX buffer */
for (i = 0; i < PKTBUFSRX; i++) {
rxbuf[i] = SetupRxBuffer(i);
if (i > 0) {
rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
&(rxbuf[i]->Dma[0]);
if (i == (PKTBUFSRX - 1))
rxbuf[i]->Dma[1].NEXT_DESC_PTR =
&(rxbuf[0]->Dma[0]);
}
}
for (i = 0; i < TX_BUF_CNT; i++) {
txbuf[i] = SetupTxBuffer(i);
if (i > 0) {
txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
&(txbuf[i]->Dma[0]);
if (i == (TX_BUF_CNT - 1))
txbuf[i]->Dma[1].NEXT_DESC_PTR =
&(txbuf[0]->Dma[0]);
}
}
/* Set RX DMA */
*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
/* Wait MII done */
PollMdcDone();
/* We enable only RX here */
/* ASTP : Enable Automatic Pad Stripping
PR : Promiscuous Mode for test
PSF : Receive frames with total length less than 64 bytes.
FDMODE : Full Duplex Mode
LB : Internal Loopback for test
RE : Receiver Enable */
if (dat == FDMODE)
opmode = ASTP | FDMODE | PSF;
else
opmode = ASTP | PSF;
opmode |= RE;
#ifdef CONFIG_BFIN_MAC_RMII
opmode |= TE | RMII;
#endif
/* Turn on the EMAC */
*pEMAC_OPMODE = opmode;
return 0;
}
static void bfin_EMAC_halt(struct eth_device *dev)
{
DEBUGF("Eth_halt: ......\n");
/* Turn off the EMAC */
*pEMAC_OPMODE = 0x00000000;
/* Turn off the EMAC RX DMA */
*pDMA1_CONFIG = 0x0000;
*pDMA2_CONFIG = 0x0000;
}
void SetupMacAddr(u8 * MACaddr)
{
char *tmp, *end;
int i;
/* this depends on a little-endian machine */
tmp = getenv("ethaddr");
if (tmp) {
for (i = 0; i < 6; i++) {
MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
if (tmp)
tmp = (*end) ? end + 1 : end;
}
#ifndef CONFIG_NETCONSOLE
printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n",
MACaddr[0], MACaddr[1],
MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]);
#endif
*pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 |
MACaddr[2] << 16 | MACaddr[3] << 24;
*pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8;
}
}
void PollMdcDone(void)
{
/* poll the STABUSY bit */
while (*pEMAC_STAADD & STABUSY) ;
}
void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
{
PollMdcDone();
*pEMAC_STADAT = Data;
*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
STAOP | STAIE | STABUSY;
}
/*********************************************************************************
* Read an off-chip register in a PHY through the MDC/MDIO port *
*********************************************************************************/
u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
{
u16 Data;
PollMdcDone();
*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
STAIE | STABUSY;
PollMdcDone();
Data = (u16) * pEMAC_STADAT;
PHYregs[RegAddr] = Data; /* save shadow copy */
return Data;
}
void SoftResetPHY(void)
{
u16 phydat;
/* set the reset bit */
WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
/* and clear it again */
WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
do {
/* poll until reset is complete */
phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
} while ((phydat & PHY_RESET) != 0);
}
int SetupSystemRegs(int *opmode)
{
u16 sysctl, phydat;
int count = 0;
/* Enable PHY output */
*pVR_CTL |= PHYCLKOE;
/* MDC = 2.5 MHz */
sysctl = SET_MDCDIV(24);
/* Odd word alignment for Receive Frame DMA word */
/* Configure checksum support and rcve frame word alignment */
sysctl |= RXDWA | RXCKS;
*pEMAC_SYSCTL = sysctl;
/* auto negotiation on */
/* full duplex */
/* 100 Mbps */
phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
do {
udelay(1000);
phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
if (count > 3000) {
printf
("Link is down, please check your network connection\n");
return -1;
}
count++;
} while (!(phydat & 0x0004));
phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
if ((phydat & 0x0100) || (phydat & 0x0040))
*opmode = FDMODE;
else
*opmode = 0;
*pEMAC_MMC_CTL = RSTC | CROLL;
/* Initialize the TX DMA channel registers */
*pDMA2_X_COUNT = 0;
*pDMA2_X_MODIFY = 4;
*pDMA2_Y_COUNT = 0;
*pDMA2_Y_MODIFY = 0;
/* Initialize the RX DMA channel registers */
*pDMA1_X_COUNT = 0;
*pDMA1_X_MODIFY = 4;
*pDMA1_Y_COUNT = 0;
*pDMA1_Y_MODIFY = 0;
return 0;
}
ADI_ETHER_BUFFER *SetupRxBuffer(int no)
{
ADI_ETHER_FRAME_BUFFER *frmbuf;
ADI_ETHER_BUFFER *buf;
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
frmbuf =
(ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
memset(frmbuf, 0xfe, RECV_BUFSIZE);
/* set up first desc to point to receive frame buffer */
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
return buf;
}
ADI_ETHER_BUFFER *SetupTxBuffer(int no)
{
ADI_ETHER_FRAME_BUFFER *frmbuf;
ADI_ETHER_BUFFER *buf;
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
frmbuf =
(ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
memset(frmbuf, 0x00, RECV_BUFSIZE);
/* set up first desc to point to receive frame buffer */
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
return buf;
}
#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
int ether_post_test(int flags)
{
uchar buf[64];
int i, value = 0;
int length;
printf("\n--------");
bfin_EMAC_init(NULL, NULL);
/* construct the package */
buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
buf[12] = 0x08; /* Type: ARP */
buf[13] = 0x06;
buf[14] = 0x00; /* Hardware type: Ethernet */
buf[15] = 0x01;
buf[16] = 0x08; /* Protocal type: IP */
buf[17] = 0x00;
buf[18] = 0x06; /* Hardware size */
buf[19] = 0x04; /* Protocol size */
buf[20] = 0x00; /* Opcode: request */
buf[21] = 0x01;
for (i = 0; i < 42; i++)
buf[i + 22] = i;
printf("--------Send 64 bytes......\n");
bfin_EMAC_send(NULL, (volatile void *)buf, 64);
for (i = 0; i < 100; i++) {
udelay(10000);
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
value = 1;
break;
}
}
if (value == 0) {
printf("--------EMAC can't receive any data\n");
eth_halt();
return -1;
}
length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
for (i = 0; i < length; i++) {
if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
printf("--------EMAC receive error data!\n");
eth_halt();
return -1;
}
}
printf("--------receive %d bytes, matched\n", length);
bfin_EMAC_halt(NULL);
return 0;
}
#endif
#endif /* CFG_CMD_NET */

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#define PHYADDR 0x01
#define NO_PHY_REGS 0x20
#define DEFAULT_PHY_PHYID1 0x0007
#define DEFAULT_PHY_PHYID2 0xC0A3
#define PHY_MODECTL 0x00
#define PHY_MODESTAT 0x01
#define PHY_PHYID1 0x02
#define PHY_PHYID2 0x03
#define PHY_ANAR 0x04
#define PHY_ANLPAR 0x05
#define PHY_ANER 0x06
#define PHY_RESET 0x8000
#define PHY_ANEG_EN 0x1000
#define PHY_DUPLEX 0x0100
#define PHY_SPD_SET 0x2000
#define RECV_BUFSIZE (0x614)
typedef volatile u32 reg32;
typedef volatile u16 reg16;
typedef struct ADI_DMA_CONFIG_REG {
u16 b_DMA_EN:1; /* 0 Enabled */
u16 b_WNR:1; /* 1 Direction */
u16 b_WDSIZE:2; /* 2:3 Transfer word size */
u16 b_DMA2D:1; /* 4 DMA mode */
u16 b_RESTART:1; /* 5 Retain FIFO */
u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
u16 b_DI_EN:1; /* 7 Data interrupt enabled */
u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
u16 b_FLOW:3; /* 12:14Flow */
} ADI_DMA_CONFIG_REG;
typedef struct adi_ether_frame_buffer {
u16 NoBytes; /* the no. of following bytes */
u8 Dest[6]; /* destination MAC address */
u8 Srce[6]; /* source MAC address */
u16 LTfield; /* length/type field */
u8 Data[0]; /* payload bytes */
} ADI_ETHER_FRAME_BUFFER;
/* 16 bytes/struct */
typedef struct dma_descriptor {
struct dma_descriptor *NEXT_DESC_PTR;
u32 START_ADDR;
ADI_DMA_CONFIG_REG CONFIG;
} DMA_DESCRIPTOR;
/* 10 bytes/struct in 12 bytes */
typedef struct adi_ether_buffer {
DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
struct adi_ether_buffer *pNext; /* next buffer */
struct adi_ether_buffer *pPrev; /* prev buffer */
u16 IPHdrChksum; /* the IP header checksum */
u16 IPPayloadChksum; /* the IP header and payload checksum */
volatile u32 StatusWord; /* the frame status word */
} ADI_ETHER_BUFFER;
/* 40 bytes/struct in 44 bytes */
void SetupMacAddr(u8 * MACaddr);
void PollMdcDone(void);
void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
void SoftResetPHY(void);
void DumpPHYRegs(void);
int SetupSystemRegs(int *opmode);
/**
* is_zero_ether_addr - Determine if give Ethernet address is all zeros.
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Return true if the address is all zeroes.
*/
static inline int is_zero_ether_addr(const u8 * addr)
{
return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
}
/**
* is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Return true if the address is a multicast address.
* By definition the broadcast address is also a multicast address.
*/
static inline int is_multicast_ether_addr(const u8 * addr)
{
return (0x01 & addr[0]);
}
/**
* is_valid_ether_addr - Determine if the given Ethernet address is valid
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
* a multicast address, and is not FF:FF:FF:FF:FF:FF.
*
* Return true if the address is valid.
*/
static inline int is_valid_ether_addr(const u8 * addr)
{
/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
* explicitly check for it here. */
return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
}

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/*
* U-boot - flash-defines.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __FLASHDEFINES_H__
#define __FLASHDEFINES_H__
#include <common.h>
#define V_ULONG(a) (*(volatile unsigned long *)( a ))
#define V_BYTE(a) (*(volatile unsigned char *)( a ))
#define TRUE 0x1
#define FALSE 0x0
#define BUFFER_SIZE 0x80000
#define NO_COMMAND 0
#define GET_CODES 1
#define RESET 2
#define WRITE 3
#define FILL 4
#define ERASE_ALL 5
#define ERASE_SECT 6
#define READ 7
#define GET_SECTNUM 8
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_MAN_ST 2
#define RESET_VAL 0xF0
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
int get_codes(void);
int poll_toggle_bit(long lOffset);
void reset_flash(void);
int erase_flash(void);
int erase_block_flash(int);
void unlock_flash(long lOffset);
int write_data(long lStart, long lCount, uchar * pnData);
int read_flash(long nOffset, int *pnValue);
int write_flash(long nOffset, int nValue);
void get_sector_number(long lOffset, int *pnSector);
int GetSectorProtectionStatus(flash_info_t * info, int nSector);
int GetOffset(int nBlock);
int AFP_NumSectors = 71;
long AFP_SectorSize2 = 0x10000;
int AFP_SectorSize1 = 0x2000;
#define NUM_SECTORS 71
#define WRITESEQ1 0x0AAA
#define WRITESEQ2 0x0554
#define WRITESEQ3 0x0AAA
#define WRITESEQ4 0x0AAA
#define WRITESEQ5 0x0554
#define WRITESEQ6 0x0AAA
#define WRITEDATA1 0xaa
#define WRITEDATA2 0x55
#define WRITEDATA3 0x80
#define WRITEDATA4 0xaa
#define WRITEDATA5 0x55
#define WRITEDATA6 0x10
#define PriFlashABegin 0
#define SecFlashABegin 8
#define SecFlashBBegin 36
#define PriFlashAOff 0x0
#define PriFlashBOff 0x100000
#define SecFlashAOff 0x10000
#define SecFlashBOff 0x280000
#define INVALIDLOCNSTART 0x20270000
#define INVALIDLOCNEND 0x20280000
#define BlockEraseVal 0x30
#define UNLOCKDATA1 0xaa
#define UNLOCKDATA2 0x55
#define UNLOCKDATA3 0xa0
#define GETCODEDATA1 0xaa
#define GETCODEDATA2 0x55
#define GETCODEDATA3 0x90
#define SecFlashASec1Off 0x200000
#define SecFlashASec2Off 0x204000
#define SecFlashASec3Off 0x206000
#define SecFlashASec4Off 0x208000
#define SecFlashAEndOff 0x210000
#define SecFlashBSec1Off 0x280000
#define SecFlashBSec2Off 0x284000
#define SecFlashBSec3Off 0x286000
#define SecFlashBSec4Off 0x288000
#define SecFlashBEndOff 0x290000
#define SECT32 32
#define SECT33 33
#define SECT34 34
#define SECT35 35
#define SECT36 36
#define SECT37 37
#define SECT38 38
#define SECT39 39
#define FLASH_SUCCESS 0
#define FLASH_FAIL -1
#endif

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/*
* U-boot - flash.c Flash driver for PSD4256GV
*
* Copyright (c) 2005-2007 Analog Devices Inc.
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <malloc.h>
#include <config.h>
#include <asm/io.h>
#include "flash-defines.h"
void flash_reset(void)
{
reset_flash();
}
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
{
int id = 0, i = 0;
static int FlagDev = 1;
id = get_codes();
if (FlagDev) {
FlagDev = 0;
}
info->flash_id = id;
switch (bank_flag) {
case 0:
for (i = PriFlashABegin; i < SecFlashABegin; i++)
info->start[i] = (baseaddr + (i * AFP_SectorSize1));
for (i = SecFlashABegin; i < NUM_SECTORS; i++)
info->start[i] =
(baseaddr + SecFlashAOff +
((i - SecFlashABegin) * AFP_SectorSize2));
info->size = 0x400000;
info->sector_count = NUM_SECTORS;
break;
case 1:
info->start[0] = baseaddr + SecFlashASec1Off;
info->start[1] = baseaddr + SecFlashASec2Off;
info->start[2] = baseaddr + SecFlashASec3Off;
info->start[3] = baseaddr + SecFlashASec4Off;
info->size = 0x10000;
info->sector_count = 4;
break;
case 2:
info->start[0] = baseaddr + SecFlashBSec1Off;
info->start[1] = baseaddr + SecFlashBSec2Off;
info->start[2] = baseaddr + SecFlashBSec3Off;
info->start[3] = baseaddr + SecFlashBSec4Off;
info->size = 0x10000;
info->sector_count = 4;
break;
}
return (info->size);
}
unsigned long flash_init(void)
{
unsigned long size_b;
int i;
size_b = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b = flash_get_size(CFG_FLASH_BASE, &flash_info[0], 0);
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b == 0) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b, size_b >> 20);
}
/* flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */
(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
(flash_info[0].start[2] - 1), &flash_info[0]);
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
(void)flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF,
&flash_info[0]);
#endif
return (size_b);
}
void flash_print_info(flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id) {
case (STM_ID_29W320EB & 0xFFFF):
case (STM_ID_29W320DB & 0xFFFF):
printf("ST Microelectronics ");
break;
default:
printf("Unknown Vendor: (0x%08X) ", info->flash_id);
break;
}
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
return;
}
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int cnt = 0, i;
int prot, sect;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect])
prot++;
}
if (prot)
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
else
printf("\n");
cnt = s_last - s_first + 1;
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
printf("Erasing Flash locations, Please Wait\n");
for (i = s_first; i <= s_last; i++) {
if (info->protect[i] == 0) { /* not protected */
if (erase_block_flash(i) < 0) {
printf("Error Sector erasing \n");
return FLASH_FAIL;
}
}
}
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
if (cnt == FLASH_TOT_SECT) {
printf("Erasing flash, Please Wait \n");
if (erase_flash() < 0) {
printf("Erasing flash failed \n");
return FLASH_FAIL;
}
} else {
printf("Erasing Flash locations, Please Wait\n");
for (i = s_first; i <= s_last; i++) {
if (info->protect[i] == 0) { /* not protected */
if (erase_block_flash(i) < 0) {
printf("Error Sector erasing \n");
return FLASH_FAIL;
}
}
}
}
#endif
printf("\n");
return FLASH_SUCCESS;
}
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int d;
if (addr % 2) {
read_flash(addr - 1 - CFG_FLASH_BASE, &d);
d = (int)((d & 0x00FF) | (*src++ << 8));
write_data(addr - 1, 2, (uchar *) & d);
write_data(addr + 1, cnt - 1, src);
} else
write_data(addr, cnt, src);
return FLASH_SUCCESS;
}
int write_data(long lStart, long lCount, uchar * pnData)
{
long i = 0;
unsigned long ulOffset = lStart - CFG_FLASH_BASE;
int d;
int nSector = 0;
int flag = 0;
if (lCount % 2) {
flag = 1;
lCount = lCount - 1;
}
for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
d = (int)(pnData[i] | pnData[i + 1] << 8);
write_flash(ulOffset, d);
if (poll_toggle_bit(ulOffset) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
if ((i > 0) && (!(i % AFP_SectorSize2)))
printf(".");
}
if (flag) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
d = (int)(pnData[i] | (d & 0xFF00));
write_flash(ulOffset, d);
if (poll_toggle_bit(ulOffset) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
}
return FLASH_SUCCESS;
}
int write_flash(long nOffset, int nValue)
{
long addr;
addr = (CFG_FLASH_BASE + nOffset);
*(unsigned volatile short *)addr = nValue;
sync();
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
if (icache_status())
udelay(CONFIG_CCLK_HZ / 1000000);
#endif
return FLASH_SUCCESS;
}
int read_flash(long nOffset, int *pnValue)
{
unsigned short *pFlashAddr =
(unsigned short *)(CFG_FLASH_BASE + nOffset);
*pnValue = *pFlashAddr;
return TRUE;
}
int poll_toggle_bit(long lOffset)
{
unsigned int u1, u2;
volatile unsigned long *FB =
(volatile unsigned long *)(CFG_FLASH_BASE + lOffset);
while (1) {
u1 = *(volatile unsigned short *)FB;
u2 = *(volatile unsigned short *)FB;
u1 ^= u2;
if (!(u1 & 0x0040))
break;
if (!(u2 & 0x0020))
continue;
else {
u1 = *(volatile unsigned short *)FB;
u2 = *(volatile unsigned short *)FB;
u1 ^= u2;
if (!(u1 & 0x0040))
break;
else {
reset_flash();
return FLASH_FAIL;
}
}
}
return FLASH_SUCCESS;
}
void reset_flash(void)
{
write_flash(WRITESEQ1, RESET_VAL);
/* Wait for 10 micro seconds */
udelay(10);
}
int erase_flash(void)
{
write_flash(WRITESEQ1, WRITEDATA1);
write_flash(WRITESEQ2, WRITEDATA2);
write_flash(WRITESEQ3, WRITEDATA3);
write_flash(WRITESEQ4, WRITEDATA4);
write_flash(WRITESEQ5, WRITEDATA5);
write_flash(WRITESEQ6, WRITEDATA6);
if (poll_toggle_bit(0x0000) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
}
int erase_block_flash(int nBlock)
{
long ulSectorOff = 0x0;
if ((nBlock < 0) || (nBlock > AFP_NumSectors))
return FALSE;
/* figure out the offset of the block in flash */
if ((nBlock >= 0) && (nBlock < SecFlashABegin))
ulSectorOff = nBlock * AFP_SectorSize1;
else if ((nBlock >= SecFlashABegin) && (nBlock < NUM_SECTORS))
ulSectorOff =
SecFlashAOff + (nBlock - SecFlashABegin) * AFP_SectorSize2;
/* no such sector */
else
return FLASH_FAIL;
write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
write_flash(ulSectorOff, BlockEraseVal);
if (poll_toggle_bit(ulSectorOff) < 0)
return FLASH_FAIL;
printf(".");
return FLASH_SUCCESS;
}
void unlock_flash(long ulOffset)
{
unsigned long ulOffsetAddr = ulOffset;
ulOffsetAddr &= 0xFFFF0000;
write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
}
int get_codes()
{
int dev_id = 0;
write_flash(WRITESEQ1, GETCODEDATA1);
write_flash(WRITESEQ2, GETCODEDATA2);
write_flash(WRITESEQ3, GETCODEDATA3);
read_flash(0x0402, &dev_id);
dev_id &= 0x0000FFFF;
reset_flash();
return dev_id;
}
void get_sector_number(long ulOffset, int *pnSector)
{
int nSector = 0;
long lMainEnd = 0x400000;
long lBootEnd = 0x10000;
/* sector numbers for the FLASH A boot sectors */
if (ulOffset < lBootEnd) {
nSector = (int)ulOffset / AFP_SectorSize1;
}
/* sector numbers for the FLASH B boot sectors */
else if ((ulOffset >= lBootEnd) && (ulOffset < lMainEnd)) {
nSector = ((ulOffset / (AFP_SectorSize2)) + 7);
}
/* if it is a valid sector, set it */
if ((nSector >= 0) && (nSector < AFP_NumSectors))
*pnSector = nSector;
}

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/*
* (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
#define CONCAT(a,b,c,d) a ## b ## c ## d
#define PORT(a,b) CONCAT(pPORT,a,b,)
#ifndef CONFIG_NAND_GPIO_PORT
#define CONFIG_NAND_GPIO_PORT F
#endif
/*
* hardware specific access to control-lines
*/
static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
{
register struct nand_chip *this = mtd->priv;
switch (cmd) {
case NAND_CTL_SETCLE:
this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
break;
case NAND_CTL_CLRCLE:
this->IO_ADDR_W = CFG_NAND_BASE;
break;
case NAND_CTL_SETALE:
this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
break;
case NAND_CTL_CLRALE:
this->IO_ADDR_W = CFG_NAND_BASE;
break;
case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE:
break;
}
this->IO_ADDR_R = this->IO_ADDR_W;
/* Drain the writebuffer */
sync();
}
int bfin_device_ready(struct mtd_info *mtd)
{
int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
sync();
return ret;
}
/*
* Board-specific NAND initialization. The following members of the
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
* nand_scan about special functionality. See the defines for further
* explanation
* Members with a "?" were not set in the merged testing-NAND branch,
* so they are not set here either.
*/
void board_nand_init(struct nand_chip *nand)
{
*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
nand->hwcontrol = bfin_hwcontrol;
nand->eccmode = NAND_ECC_SOFT;
nand->dev_ready = bfin_device_ready;
nand->chip_delay = 30;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

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#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_POST
#include <post.h>
#include <watchdog.h>
#if CONFIG_POST & CFG_POST_MEMORY
#define CLKIN 25000000
#define PATTERN1 0x5A5A5A5A
#define PATTERN2 0xAAAAAAAA
#define CCLK_NUM 4
#define SCLK_NUM 3
void post_out_buff(char *buff);
int post_key_pressed(void);
void post_init_pll(int mult, int div);
int post_init_sdram(int sclk);
void post_init_uart(int sclk);
const int pll[CCLK_NUM][SCLK_NUM][2] = {
{{20, 4}, {20, 5}, {20, 10}}, /* CCLK = 500M */
{{16, 4}, {16, 5}, {16, 8}}, /* CCLK = 400M */
{{8, 2}, {8, 4}, {8, 5}}, /* CCLK = 200M */
{{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */
};
const char *const log[CCLK_NUM][SCLK_NUM] = {
{"CCLK-500Mhz SCLK-125Mhz: Writing...\0",
"CCLK-500Mhz SCLK-100Mhz: Writing...\0",
"CCLK-500Mhz SCLK- 50Mhz: Writing...\0",},
{"CCLK-400Mhz SCLK-100Mhz: Writing...\0",
"CCLK-400Mhz SCLK- 80Mhz: Writing...\0",
"CCLK-400Mhz SCLK- 50Mhz: Writing...\0",},
{"CCLK-200Mhz SCLK-100Mhz: Writing...\0",
"CCLK-200Mhz SCLK- 50Mhz: Writing...\0",
"CCLK-200Mhz SCLK- 40Mhz: Writing...\0",},
{"CCLK-100Mhz SCLK-100Mhz: Writing...\0",
"CCLK-100Mhz SCLK- 50Mhz: Writing...\0",
"CCLK-100Mhz SCLK- 25Mhz: Writing...\0",},
};
int memory_post_test(int flags)
{
int addr;
int m, n;
int sclk, sclk_temp;
int ret = 1;
sclk_temp = CLKIN / 1000000;
sclk_temp = sclk_temp * CONFIG_VCO_MULT;
for (sclk = 0; sclk_temp > 0; sclk++)
sclk_temp -= CONFIG_SCLK_DIV;
sclk = sclk * 1000000;
post_init_uart(sclk);
if (post_key_pressed() == 0)
return 0;
for (m = 0; m < CCLK_NUM; m++) {
for (n = 0; n < SCLK_NUM; n++) {
/* Calculate the sclk */
sclk_temp = CLKIN / 1000000;
sclk_temp = sclk_temp * pll[m][n][0];
for (sclk = 0; sclk_temp > 0; sclk++)
sclk_temp -= pll[m][n][1];
sclk = sclk * 1000000;
post_init_pll(pll[m][n][0], pll[m][n][1]);
post_init_sdram(sclk);
post_init_uart(sclk);
post_out_buff("\n\r\0");
post_out_buff(log[m][n]);
for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
*(unsigned long *)addr = PATTERN1;
post_out_buff("Reading...\0");
for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) {
if ((*(unsigned long *)addr) != PATTERN1) {
post_out_buff("Error\n\r\0");
ret = 0;
}
}
post_out_buff("OK\n\r\0");
}
}
if (ret)
post_out_buff("memory POST passed\n\r\0");
else
post_out_buff("memory POST failed\n\r\0");
post_out_buff("\n\r\n\r\0");
return 1;
}
void post_init_uart(int sclk)
{
int divisor;
for (divisor = 0; sclk > 0; divisor++)
sclk -= 57600 * 16;
*pPORTF_FER = 0x000F;
*pPORTH_FER = 0xFFFF;
*pUART_GCTL = 0x00;
*pUART_LCR = 0x83;
sync();
*pUART_DLL = (divisor & 0xFF);
sync();
*pUART_DLH = ((divisor >> 8) & 0xFF);
sync();
*pUART_LCR = 0x03;
sync();
*pUART_GCTL = 0x01;
sync();
}
void post_out_buff(char *buff)
{
int i = 0;
for (i = 0; i < 0x80000; i++) ;
i = 0;
while ((buff[i] != '\0') && (i != 100)) {
while (!(*pUART_LSR & 0x20)) ;
*pUART_THR = buff[i];
sync();
i++;
}
for (i = 0; i < 0x80000; i++) ;
}
/* Using sw10-PF5 as the hotkey */
#define KEY_LOOP 0x80000
#define KEY_DELAY 0x80
int post_key_pressed(void)
{
int i, n;
unsigned short value;
*pPORTF_FER &= ~PF5;
*pPORTFIO_DIR &= ~PF5;
*pPORTFIO_INEN |= PF5;
sync();
post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
for (i = 0; i < KEY_LOOP; i++) {
value = *pPORTFIO & PF5;
if (*pUART0_RBR == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0) {
goto key_pressed;
}
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
post_out_buff("\b2\0");
for (i = 0; i < KEY_LOOP; i++) {
value = *pPORTFIO & PF5;
if (*pUART0_RBR == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0) {
goto key_pressed;
}
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
post_out_buff("\b1\0");
for (i = 0; i < KEY_LOOP; i++) {
value = *pPORTFIO & PF5;
if (*pUART0_RBR == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0) {
goto key_pressed;
}
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
key_pressed:
post_out_buff("\b0");
post_out_buff("\n\r\0");
if (value == 0)
return 0;
post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
return 1;
}
void post_init_pll(int mult, int div)
{
*pSIC_IWR = 0x01;
*pPLL_CTL = (mult << 9);
*pPLL_DIV = div;
asm("CLI R2;");
asm("IDLE;");
asm("STI R2;");
while (!(*pPLL_STAT & 0x20)) ;
}
int post_init_sdram(int sclk)
{
int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
SDRAM_tWR;
int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
if ((sclk > 119402985)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_7;
SDRAM_tRAS_num = 7;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 104477612) && (sclk <= 119402985)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_6;
SDRAM_tRAS_num = 6;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 89552239) && (sclk <= 104477612)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_5;
SDRAM_tRAS_num = 5;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 74626866) && (sclk <= 89552239)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_4;
SDRAM_tRAS_num = 4;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 66666667) && (sclk <= 74626866)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_3;
SDRAM_tRAS_num = 3;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 59701493) && (sclk <= 66666667)) {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_4;
SDRAM_tRAS_num = 4;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
} else if ((sclk > 44776119) && (sclk <= 59701493)) {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_3;
SDRAM_tRAS_num = 3;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
} else if ((sclk > 29850746) && (sclk <= 44776119)) {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_2;
SDRAM_tRAS_num = 2;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
} else if (sclk <= 29850746) {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_1;
SDRAM_tRAS_num = 1;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
} else {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_1;
SDRAM_tRAS_num = 1;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
}
/*SDRAM INFORMATION: */
SDRAM_Tref = 64; /* Refresh period in milliseconds */
SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
SDRAM_CL = CL_3; /* 2 */
SDRAM_SIZE = EBSZ_64;
SDRAM_WIDTH = EBCAW_10;
mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
/* Equation from section 17 (p17-46) of BF533 HRM */
mem_SDRRC =
(((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
(SDRAM_tRAS_num + SDRAM_tRP_num);
/* Enable SCLK Out */
mem_SDGCTL =
(SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
| PSS);
sync();
*pEBIU_SDGCTL |= 0x1000000;
/* Set the SDRAM Refresh Rate control register based on SSCLK value */
*pEBIU_SDRRC = mem_SDRRC;
/* SDRAM Memory Bank Control Register */
*pEBIU_SDBCTL = mem_SDBCTL;
/* SDRAM Memory Global Control Register */
*pEBIU_SDGCTL = mem_SDGCTL;
sync();
return mem_SDRRC;
}
#endif /* CONFIG_POST & CFG_POST_MEMORY */
#endif /* CONFIG_POST */

515
board/bf537-stamp/stm_m25p64.c Normal file
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/****************************************************************************
* SPI flash driver for M25P64
****************************************************************************/
#include <common.h>
#include <linux/ctype.h>
#include <asm/io.h>
#if defined(CONFIG_SPI)
/* Application definitions */
#define NUM_SECTORS 128 /* number of sectors */
#define SECTOR_SIZE 0x10000
#define NOP_NUM 1000
#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /* Settings to the SPI_CTL */
#define TIMOD01 (0x01) /* stes the SPI to work with core instructions */
/* Flash commands */
#define SPI_WREN (0x06) /*Set Write Enable Latch */
#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
#define SPI_RDSR (0x05) /*Read Status Register */
#define SPI_WRSR (0x01) /*Write Status Register */
#define SPI_READ (0x03) /*Read data from memory */
#define SPI_FAST_READ (0x0B) /*Read data from memory */
#define SPI_PP (0x02) /*Program Data into memory */
#define SPI_SE (0xD8) /*Erase one sector in memory */
#define SPI_BE (0xC7) /*Erase all memory */
#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
#define WEL (0x2) /*Check the write enable bit of the SPI status register */
#define TIMEOUT 350000000
typedef enum {
NO_ERR,
POLL_TIMEOUT,
INVALID_SECTOR,
INVALID_BLOCK,
} ERROR_CODE;
void spi_init_f(void);
void spi_init_r(void);
ssize_t spi_read(uchar *, int, uchar *, int);
ssize_t spi_write(uchar *, int, uchar *, int);
char ReadStatusRegister(void);
void Wait_For_SPIF(void);
void SetupSPI(const int spi_setting);
void SPI_OFF(void);
void SendSingleCommand(const int iCommand);
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
ERROR_CODE EraseBlock(int nBlock);
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
ERROR_CODE Wait_For_Status(char Statusbit);
ERROR_CODE Wait_For_WEL(void);
/*
* Function: spi_init_f
* Description: Init SPI-Controller (ROM part)
* return: ---
*/
void spi_init_f(void)
{
}
/*
* Function: spi_init_r
* Description: Init SPI-Controller (RAM part) -
* The malloc engine is ready and we can move our buffers to
* normal RAM
* return: ---
*/
void spi_init_r(void)
{
return;
}
/*
* Function: spi_write
*/
ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
{
unsigned long offset;
int start_block, end_block;
int start_byte, end_byte;
ERROR_CODE result = NO_ERR;
uchar temp[SECTOR_SIZE];
int i, num;
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
/* Get the start block number */
result = GetSectorNumber(offset, &start_block);
if (result == INVALID_SECTOR) {
printf("Invalid sector! ");
return 0;
}
/* Get the end block number */
result = GetSectorNumber(offset + len - 1, &end_block);
if (result == INVALID_SECTOR) {
printf("Invalid sector! ");
return 0;
}
for (num = start_block; num <= end_block; num++) {
ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
start_byte = num * SECTOR_SIZE;
end_byte = (num + 1) * SECTOR_SIZE - 1;
if (start_byte < offset)
start_byte = offset;
if (end_byte > (offset + len))
end_byte = (offset + len - 1);
for (i = start_byte; i <= end_byte; i++)
temp[i - num * SECTOR_SIZE] = buffer[i - offset];
EraseBlock(num);
result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
if (result != NO_ERR)
return 0;
printf(".");
}
return len;
}
/*
* Function: spi_read
*/
ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
{
unsigned long offset;
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
ReadData(offset, len, (int *)buffer);
return len;
}
void SendSingleCommand(const int iCommand)
{
unsigned short dummy;
/* turns on the SPI in single write mode */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
/* sends the actual command to the SPI TX register */
*pSPI_TDBR = iCommand;
sync();
/* The SPI status register will be polled to check the SPIF bit */
Wait_For_SPIF();
dummy = *pSPI_RDBR;
/* The SPI will be turned off */
SPI_OFF();
}
void SetupSPI(const int spi_setting)
{
if (icache_status() || dcache_status())
udelay(CONFIG_CCLK_HZ / 50000000);
/*sets up the PF10 to be the slave select of the SPI */
*pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
*pSPI_FLG = 0xFF02;
*pSPI_BAUD = CONFIG_SPI_BAUD;
*pSPI_CTL = spi_setting;
sync();
*pSPI_FLG = 0xFD02;
sync();
}
void SPI_OFF(void)
{
*pSPI_CTL = 0x0400; /* disable SPI */
*pSPI_FLG = 0;
*pSPI_BAUD = 0;
sync();
udelay(CONFIG_CCLK_HZ / 50000000);
}
void Wait_For_SPIF(void)
{
unsigned short dummyread;
while ((*pSPI_STAT & TXS)) ;
while (!(*pSPI_STAT & SPIF)) ;
while (!(*pSPI_STAT & RXS)) ;
/* Read dummy to empty the receive register */
dummyread = *pSPI_RDBR;
}
ERROR_CODE Wait_For_WEL(void)
{
int i;
char status_register = 0;
ERROR_CODE ErrorCode = NO_ERR;
for (i = 0; i < TIMEOUT; i++) {
status_register = ReadStatusRegister();
if ((status_register & WEL)) {
ErrorCode = NO_ERR;
break;
}
ErrorCode = POLL_TIMEOUT; /* Time out error */
};
return ErrorCode;
}
ERROR_CODE Wait_For_Status(char Statusbit)
{
int i;
char status_register = 0xFF;
ERROR_CODE ErrorCode = NO_ERR;
for (i = 0; i < TIMEOUT; i++) {
status_register = ReadStatusRegister();
if (!(status_register & Statusbit)) {
ErrorCode = NO_ERR;
break;
}
ErrorCode = POLL_TIMEOUT; /* Time out error */
};
return ErrorCode;
}
char ReadStatusRegister(void)
{
char status_register = 0;
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
*pSPI_TDBR = 0; /*send dummy to receive the status register */
sync();
Wait_For_SPIF(); /*wait until the data has been sent */
status_register = *pSPI_RDBR; /*read the status register */
SPI_OFF(); /* Turn off the SPI */
return status_register;
}
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
{
int nSector = 0;
ERROR_CODE ErrorCode = NO_ERR;
if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
ErrorCode = INVALID_SECTOR;
return ErrorCode;
}
nSector = (int)ulOffset / 0x10000;
*pnSector = nSector;
return ErrorCode;
}
ERROR_CODE EraseBlock(int nBlock)
{
unsigned long ulSectorOff = 0x0, ShiftValue;
ERROR_CODE ErrorCode = NO_ERR;
/* if the block is invalid just return */
if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
ErrorCode = INVALID_BLOCK;
return ErrorCode;
}
/* figure out the offset of the block in flash */
if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
ulSectorOff = (nBlock * SECTOR_SIZE);
} else {
ErrorCode = INVALID_BLOCK;
return ErrorCode;
}
/* A write enable instruction must previously have been executed */
SendSingleCommand(SPI_WREN);
/* The status register will be polled to check the write enable latch "WREN" */
ErrorCode = Wait_For_WEL();
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Erase block error\n");
return ErrorCode;
} else
/* Turn on the SPI to send single commands */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
/*
* Send the erase block command to the flash followed by the 24 address
* to point to the start of a sector
*/
*pSPI_TDBR = SPI_SE;
sync();
Wait_For_SPIF();
/* Send the highest byte of the 24 bit address at first */
ShiftValue = (ulSectorOff >> 16);
*pSPI_TDBR = ShiftValue;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the middle byte of the 24 bit address at second */
ShiftValue = (ulSectorOff >> 8);
*pSPI_TDBR = ShiftValue;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the lowest byte of the 24 bit address finally */
*pSPI_TDBR = ulSectorOff;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Turns off the SPI */
SPI_OFF();
/* Poll the status register to check the Write in Progress bit */
/* Sector erase takes time */
ErrorCode = Wait_For_Status(WIP);
/* block erase should be complete */
return ErrorCode;
}
/*
* ERROR_CODE ReadData()
* Read a value from flash for verify purpose
* Inputs: unsigned long ulStart - holds the SPI start address
* int pnData - pointer to store value read from flash
* long lCount - number of elements to read
*/
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
{
unsigned long ShiftValue;
char *cnData;
int i;
/* Pointer cast to be able to increment byte wise */
cnData = (char *)pnData;
/* Start SPI interface */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
#ifdef CONFIG_SPI_FLASH_FAST_READ
/* Send the read command to SPI device */
*pSPI_TDBR = SPI_FAST_READ;
#else
/* Send the read command to SPI device */
*pSPI_TDBR = SPI_READ;
#endif
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the highest byte of the 24 bit address at first */
ShiftValue = (ulStart >> 16);
/* Send the byte to the SPI device */
*pSPI_TDBR = ShiftValue;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the middle byte of the 24 bit address at second */
ShiftValue = (ulStart >> 8);
/* Send the byte to the SPI device */
*pSPI_TDBR = ShiftValue;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the lowest byte of the 24 bit address finally */
*pSPI_TDBR = ulStart;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
#ifdef CONFIG_SPI_FLASH_FAST_READ
/* Send dummy for FAST_READ */
*pSPI_TDBR = 0;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
#endif
/* After the SPI device address has been placed on the MOSI pin the data can be */
/* received on the MISO pin. */
for (i = 0; i < lCount; i++) {
*pSPI_TDBR = 0;
sync();
while (!(*pSPI_STAT & RXS)) ;
*cnData++ = *pSPI_RDBR;
if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
printf(".");
}
/* Turn off the SPI */
SPI_OFF();
return NO_ERR;
}
ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
int *iDataSource, long *lWriteCount)
{
unsigned long ulWAddr;
long lWTransferCount = 0;
int i;
char iData;
char *temp = (char *)iDataSource;
ERROR_CODE ErrorCode = NO_ERR;
/* First, a Write Enable Command must be sent to the SPI. */
SendSingleCommand(SPI_WREN);
/*
* Second, the SPI Status Register will be tested whether the
* Write Enable Bit has been set
*/
ErrorCode = Wait_For_WEL();
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Write Time Out\n");
return ErrorCode;
} else
/* Third, the 24 bit address will be shifted out
* the SPI MOSI bytewise.
* Turns the SPI on
*/
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
*pSPI_TDBR = SPI_PP;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = (ulStartAddr >> 16);
*pSPI_TDBR = ulWAddr;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = (ulStartAddr >> 8);
*pSPI_TDBR = ulWAddr;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = ulStartAddr;
*pSPI_TDBR = ulWAddr;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
/*
* Fourth, maximum number of 256 bytes will be taken from the Buffer
* and sent to the SPI device.
*/
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
iData = *temp;
*pSPI_TDBR = iData;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
temp++;
}
/* Turns the SPI off */
SPI_OFF();
/*
* Sixth, the SPI Write in Progress Bit must be toggled to ensure the
* programming is done before start of next transfer
*/
ErrorCode = Wait_For_Status(WIP);
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Program Time out!\n");
return ErrorCode;
} else
*lWriteCount = lWTransferCount;
return ErrorCode;
}
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
{
unsigned long ulWStart = ulStart;
long lWCount = lCount, lWriteCount;
long *pnWriteCount = &lWriteCount;
ERROR_CODE ErrorCode = NO_ERR;
while (lWCount != 0) {
ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
/*
* After each function call of WriteFlash the counter
* must be adjusted
*/
lWCount -= *pnWriteCount;
/* Also, both address pointers must be recalculated. */
ulWStart += *pnWriteCount;
pnData += *pnWriteCount / 4;
}
/* return the appropriate error code */
return ErrorCode;
}
#endif /* CONFIG_SPI */

190
board/bf537-stamp/u-boot.lds.S Normal file
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@ -0,0 +1,190 @@
/*
* U-boot - u-boot.lds.S
*
* Copyright (c) 2005-2007 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
OUTPUT_ARCH(bfin)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
MEMORY
{
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS; /*0x1000;*/
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
. = CFG_MONITOR_BASE;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector before the environment sector. If it throws */
/* an error during compilation remove an object here to get */
/* it linked after the configuration sector. */
cpu/bf537/start.o (.text)
cpu/bf537/start1.o (.text)
cpu/bf537/traps.o (.text)
cpu/bf537/interrupt.o (.text)
cpu/bf537/serial.o (.text)
common/dlmalloc.o (.text)
/* lib_blackfin/bf533_string.o (.text) */
/* lib_generic/vsprintf.o (.text) */
lib_generic/crc32.o (.text)
/* lib_generic/zlib.o (.text) */
/* board/bf537-stamp/bf537-stamp.o (.text) */
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .text)
*(.fixup)
*(.got1)
} > ram
_etext = .;
PROVIDE (etext = .);
.text_l1 :
{
. = ALIGN(4) ;
_text_l1 = .;
PROVIDE (text_l1 = .);
board/bf537-stamp/post-memory.o (.text)
. = ALIGN(4) ;
_etext_l1 = .;
PROVIDE (etext_l1 = .);
} > l1_code AT > ram
.rodata :
{
. = ALIGN(4);
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata)
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata1)
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata.str1.4)
*(.eh_frame)
. = ALIGN(4);
} > ram
. = ALIGN(4);
_erodata = .;
PROVIDE (erodata = .);
.rodata_l1 :
{
. = ALIGN(4) ;
_rodata_l1 = .;
PROVIDE (rodata_l1 = .);
board/bf537-stamp/post-memory.o (.rodata)
board/bf537-stamp/post-memory.o (.rodata1)
board/bf537-stamp/post-memory.o (.rodata.str1.4)
. = ALIGN(4) ;
_erodata_l1 = .;
PROVIDE(erodata_l1 = .);
} > l1_data AT > ram
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
} > ram
_edata = .;
PROVIDE (edata = .);
___u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) } > ram
___u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
.bss :
{
__bss_start = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
} > ram
_end = . ;
PROVIDE (end = .);
}

58
board/bf561-ezkit/Makefile Normal file
View File

@ -0,0 +1,58 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

73
board/bf561-ezkit/bf561-ezkit.c Normal file
View File

@ -0,0 +1,73 @@
/*
* U-boot - ezkit561.c
*
* Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl>
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <asm/io.h>
int checkboard(void)
{
printf("CPU: ADSP BF561\n");
printf("Board: ADI BF561 EZ-Kit Lite board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
return 0;
}
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
brate = simple_strtoul(tmp, NULL, 16);
printf("Serial Port initialized with Baud rate = %x\n", brate);
printf("SDRAM attributes:\n");
printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
3, 3, 6, 2, 3);
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
#endif
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
return CFG_MAX_RAM_SIZE;
}
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
/* Keep PF12 low to be able to drive the USB-LAN Extender */
*pFIO0_DIR = 0x0000;
*pFIO0_FLAG_C = 0x1000; /* Clear PF12 */
sync();
*pFIO0_POLAR = 0x0000;
sync();
return 0;
}
#endif

25
board/bf561-ezkit/config.mk Normal file
View File

@ -0,0 +1,25 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
TEXT_BASE = 0x03FC0000

153
board/bf561-ezkit/u-boot.lds.S Normal file
View File

@ -0,0 +1,153 @@
/*
* U-boot - u-boot.lds.S
*
* Copyright (c) 2005-2007 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
OUTPUT_ARCH(bfin)
OUTPUT_ARCH(bfin)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
. = CFG_MONITOR_BASE;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector before the environment sector. If it throws */
/* an error during compilation remove an object here to get */
/* it linked after the configuration sector. */
cpu/bf561/start.o (.text)
cpu/bf561/start1.o (.text)
cpu/bf561/traps.o (.text)
cpu/bf561/interrupt.o (.text)
cpu/bf561/serial.o (.text)
common/dlmalloc.o (.text)
/* lib_blackfin/bf533_string.o (.text) */
/* lib_generic/vsprintf.o (.text) */
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
board/bf561-ezkit/bf561-ezkit.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
___u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
___u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

161
board/mpc8641hpcn/pixis.c → board/freescale/common/pixis.c
View File

@ -23,14 +23,25 @@
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <mpc86xx.h>
#include "pixis.h"
static ulong strfractoint(uchar *strptr);
/*
* Simple board reset.
*/
void pixis_reset(void)
{
out8(PIXIS_BASE + PIXIS_RST, 0);
}
/*
* Per table 27, page 58 of MPC8641HPCN spec.
*/
@ -235,7 +246,8 @@ void set_px_go_with_watchdog(void)
}
int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[])
{
u8 tmp;
@ -252,7 +264,7 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
diswd, 1, 0, disable_watchdog,
diswd, 1, 0, pixis_disable_watchdog_cmd,
"diswd - Disable watchdog timer \n",
NULL);
@ -263,7 +275,7 @@ U_BOOT_CMD(
* input: strptr i.e. argv[2]
*/
ulong strfractoint(uchar *strptr)
static ulong strfractoint(uchar *strptr)
{
int i, j, retval;
int mulconst;
@ -319,3 +331,142 @@ ulong strfractoint(uchar *strptr)
return retval;
}
int
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong val;
ulong corepll;
/*
* No args is a simple reset request.
*/
if (argc <= 1) {
pixis_reset();
/* not reached */
}
if (strcmp(argv[1], "cf") == 0) {
/*
* Reset with frequency changed:
* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
*/
if (argc < 5) {
puts(cmdtp->usage);
return 1;
}
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
puts("Resetting board with values from ");
puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
set_px_go();
} else {
puts(cmdtp->usage);
return 1;
}
while (1) ; /* Not reached */
} else if (strcmp(argv[1], "altbank") == 0) {
/*
* Reset using alternate flash bank:
*/
if (argv[2] == 0) {
/*
* Reset from alternate bank without changing
* frequency and without watchdog timer enabled.
* altbank
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if (argc > 2) {
puts(cmdtp->usage);
return 1;
}
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Resetting board to boot from the other bank.\n");
set_px_go();
} else if (strcmp(argv[2], "cf") == 0) {
/*
* Reset with frequency changed
* altbank cf <SYSCLK freq> <COREPLL ratio>
* <MPXPLL ratio>
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
corepll = strfractoint(argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],
NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA\n");
puts("Resetting board with values from ");
puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
puts("to boot from the other bank.\n");
set_px_go_with_watchdog();
} else {
puts(cmdtp->usage);
return 1;
}
while (1) ; /* Not reached */
} else if (strcmp(argv[2], "wd") == 0) {
/*
* Reset from alternate bank without changing
* frequencies but with watchdog timer enabled:
* altbank wd
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA\n");
puts("Resetting board to boot from the other bank.\n");
set_px_go_with_watchdog();
while (1) ; /* Not reached */
} else {
puts(cmdtp->usage);
return 1;
}
} else {
puts(cmdtp->usage);
return 1;
}
return 0;
}
U_BOOT_CMD(
pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
"pixis_reset - Reset the board using the FPGA sequencer\n",
" pixis_reset\n"
" pixis_reset [altbank]\n"
" pixis_reset altbank wd\n"
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
);

4
board/mpc8641hpcn/pixis.h → board/freescale/common/pixis.h
View File

@ -20,6 +20,7 @@
* MA 02111-1307 USA
*/
extern void pixis_reset(void);
extern int set_px_sysclk(ulong sysclk);
extern int set_px_mpxpll(ulong mpxpll);
extern int set_px_corepll(ulong corepll);
@ -28,6 +29,3 @@ extern void read_from_px_regs_altbank(int set);
extern void set_altbank(void);
extern void set_px_go(void);
extern void set_px_go_with_watchdog(void);
extern int disable_watchdog(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[]);
extern ulong strfractoint(uchar *strptr);

49
board/icecube/icecube.c
View File

@ -42,6 +42,53 @@
#include "mt48lc16m16a2-75.h"
# endif
#endif
#ifdef CONFIG_LITE5200B_PM
/* u-boot part of low-power mode implementation */
#define SAVED_ADDR (*(void **)0x00000000)
#define PSC2_4 0x02
void lite5200b_wakeup(void)
{
unsigned char wakeup_pin;
void (*linux_wakeup)(void);
/* check PSC2_4, if it's down "QT" is signaling we have a wakeup
* from low power mode */
*(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
__asm__ volatile ("sync");
wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
if (wakeup_pin & PSC2_4)
return;
/* acknowledge to "QT"
* by holding pin at 1 for 10 uS */
*(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
__asm__ volatile ("sync");
*(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
__asm__ volatile ("sync");
udelay(10);
/* put ram out of self-refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
__asm__ volatile ("sync");
*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
__asm__ volatile ("sync");
*(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
__asm__ volatile ("sync");
udelay(10); /* wait a bit */
/* jump back to linux kernel code */
linux_wakeup = SAVED_ADDR;
printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
linux_wakeup);
linux_wakeup();
}
#else
#define lite5200b_wakeup()
#endif
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
@ -208,6 +255,8 @@ long int initdram (int board_type)
__asm__ volatile ("sync");
}
lite5200b_wakeup();
return dramsize + dramsize2;
}

4
board/mcc200/lcd.c
View File

@ -180,10 +180,6 @@ void lcd_enable (void)
break;
udelay (PSOC_WAIT_TIME);
}
if (!retries) {
printf ("%s Warning: PSoC doesn't respond on "
"RTS NEGATE\n", __FUNCTION__);
}
return;
}

52
board/mpc7448hpc2/Makefile Normal file
View File

@ -0,0 +1,52 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o tsi108_init.o
SOBJS := asm_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
.PHONY: distclean
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude ($obj).depend
#########################################################################

918
board/mpc7448hpc2/asm_init.S Normal file
View File

@ -0,0 +1,918 @@
/*
* (C) Copyright 2004-05; Tundra Semiconductor Corp.
*
* Added automatic detect of SDC settings
* Copyright (c) 2005 Freescale Semiconductor, Inc.
* Maintainer tie-fei.zang@freescale.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* FILENAME: asm_init.s
*
* Originator: Alex Bounine
*
* DESCRIPTION:
* Initialization code for the Tundra Tsi108 bridge chip
*
*/
#include <config.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/processor.h>
#include <tsi108.h>
/*
* Build Configuration Options
*/
/* #define DISABLE_PBM disables usage of PB Master */
/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
/*
* Hardcoded SDC settings
*/
#ifdef SDC_HARDCODED_INIT
/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
#define VAL_SD_REFRESH (0x61A)
#define VAL_SD_TIMING (0x0308336b)
#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */
#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */
#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */
#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */
#endif /* SDC_HARDCODED_INIT */
/*
CPU Configuration:
CPU Address and Data Parity enables.
#define CPU_AP
#define CPU_DP
*/
/*
* Macros
* !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
* expected to work correctly for the CSR space within 32KB range.
*
* LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
* These macros are absolutely identical except their names. This difference
* is provided intentionally for better readable code.
*/
#define LOAD_PTR(reg,const32) \
addis reg,r0,const32@h; ori reg,reg,const32@l
#define LOAD_U32(reg,const32) \
addis reg,r0,const32@h; ori reg,reg,const32@l
/* LOADMEM initializes a register with the contents of a specified 32-bit
* memory location, usually a CSR value.
*/
#define LOAD_MEM(reg,addr32) \
addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
#ifndef SDC_HARDCODED_INIT
sdc_clk_sync:
/* MHz: 0,0,183,100,133,167,200,233 */
.long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
#endif
/*
* board_asm_init() - early initialization function. Coded to be portable to
* dual-CPU configuration.
* Checks CPU number and performs board HW initialization if called for CPU0.
* Registers used: r3,r4,r5,r6,r19,r29
*
* NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
* and the rest of the board. Current implementation demonstrates two
* possible ways to identify CPU number:
* - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
* - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
*/
.globl board_asm_init
board_asm_init:
mflr r19 /* Save LR to be able return later. */
bl icache_enable /* Enable icache to reduce reads from flash. */
/* Initialize pointer to Tsi108 register space */
LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
ori r4,r29,TSI108_PB_REG_OFFSET
/* Check Processor Version Number */
mfspr r3, PVR
rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
cmpli 0,0,r3,0x8000 /* MPC74xx */
bne cont_brd_init
/*
* For MPC744x/5x enable extended BATs[4-7]
* Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
* to disable prefetch
*/
mfspr r5, HID0
oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */
ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */
mtspr HID0, r5
isync
sync
/* Adding code to disable external interventions in MPX bus mode */
mfspr r3, 1014
oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */
mtspr 1014, r3
isync
sync
/* Sri: code to enable FP unit */
mfmsr r3
ori r3, r3, 0x2000
mtmsr r3
isync
sync
/* def CONFIG_DUAL_CPU
* For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
*/
#if(1)
mfspr r3,1014 /* read MSSCR0 */
rlwinm. r3,r3,27,31,31 /* get processor ID number */
mtspr SPRN_PIR,r3 /* Save CPU ID */
sync
bne init_done
b do_tsi108_init
cont_brd_init:
/* An alternative method of checking the processor number (in addition
* to configuration using MSSCR0[ID] bit on MPC74xx).
* Good for IBM PPC750FX/GX.
*/
lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
rlwinm. r3,r3,24,31,31 /* get processor ID number */
bne init_done
#else
cont_brd_init:
#endif /* CONFIG_DUAL_CPU */
/* Initialize Tsi108 chip */
do_tsi108_init:
/*
* Adjust HLP/Flash parameters. By default after reset the HLP port is
* set to support slow devices. Better performance can be achived when
* an optimal parameters are used for specific EPROM device.
* NOTE: This should be performed ASAP for the emulation platform
* because it has 5MHz HLP clocking.
*/
#ifdef CONFIG_TSI108EMU
ori r4,r29,TSI108_HLP_REG_OFFSET
LOAD_U32(r5,0x434422c0)
stw r5,0x08(r4) /* set HLP B0_CTRL0 */
sync
LOAD_U32(r5,0xd0012000)
stw r5,0x0c(r4) /* set HLP B0_CTRL1 */
sync
#endif
/* Initialize PB interface. */
ori r4,r29,TSI108_PB_REG_OFFSET
#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
/* Relocate (if required) Tsi108 registers. Set new value for
* PB_REG_BAR:
* Note we are in the 32-bit address mode.
*/
LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
stw r5,PB_REG_BAR(r4)
andis. r29,r5,0xFFFF
sync
ori r4,r29,TSI108_PB_REG_OFFSET
#endif
/* Set PB Slave configuration register */
LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
lwz r3, PB_RSR(r4) /* get PB bus mode */
xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
stw r5,PB_SCR(r4)
sync
/* Configure PB Arbiter */
lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */
#ifdef DISABLE_PBM
ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
#endif
andc r5,r5,r3 /* Clear the masked bit fields */
ori r5,r5,0x0001 /* Set pipeline depth */
stw r5,PB_ARB_CTRL(r4)
#if (0) /* currently using the default settings for PBM after reset */
LOAD_U32(r5,0x) /* value for PB_MCR */
stw r5,PB_MCR(r4)
sync
LOAD_U32(r5,0x) /* value for PB_MCMD */
stw r5,PB_MCMD(r4)
sync
#endif
/* Disable or enable PVT based on processor bus frequency
* 1. Read CG_PWRUP_STATUS register field bits 18,17,16
* 2. See if the value is < or > 133mhz (18:16 = 100)
* 3. If > enable PVT
*/
LOAD_U32(r3,0xC0002234)
lwz r3,0(r3)
rlwinm r3,r3,16,29,31
cmpi 0,0,r3,0x0004
bgt sdc_init
#ifndef CONFIG_TSI108EMU
/* FIXME: Disable PB calibration control for any real Tsi108 board */
li r5,0x0101 /* disable calibration control */
stw r5,PB_PVT_CTRL2(r4)
sync
#endif
/* Initialize SDRAM controller. */
sdc_init:
#ifndef SDC_HARDCODED_INIT
/* get SDC clock prior doing sdram controller autoconfig */
ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */
lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */
rlwinm r3,r3,12,29,31 /* r3 - SD clk */
lis r5,sdc_clk_sync@h
ori r5,r5,sdc_clk_sync@l
/* Sri: At this point check if r3 = 001. If yes,
* the memory frequency should be same as the
* MPX bus frequency
*/
cmpi 0,0,r3,0x0001
bne get_nsec
lwz r6, CG_PWRUP_STATUS(r4)
rlwinm r6,r6,16,29,31
mr r3,r6
get_nsec:
rlwinm r3,r3,2,0,31
lwzx r9,r5,r3 /* get SD clk rate in nSec */
/* ATTN: r9 will be used by SPD routine */
#endif /* !SDC_HARDCODED_INIT */
ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
/* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
LOAD_U32(r5,0x00)
stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
#ifdef ENABLE_SDRAM_ECC
li r5, 0x01
#endif /* ENABLE_SDRAM_ECC */
stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */
sync
#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
/* First read the CG_PWRUP_STATUS register to get the
* memory speed from bits 22,21,20
*/
LOAD_U32(r3,0xC0002234)
lwz r3,0(r3)
rlwinm r3,r3,12,29,31
/* Now first check for 166, then 200, or default */
cmpi 0,0,r3,0x0005
bne check_for_200mhz
/* set values for 166 Mhz memory speed
* Set refresh rate and timing parameters
*/
LOAD_U32(r5,0x00000515)
stw r5,SD_REFRESH(r4)
LOAD_U32(r5,0x03073368)
stw r5,SD_TIMING(r4)
sync
/* Initialize DIMM0 control and BAR registers */
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D0_CTRL(r4)
LOAD_U32(r5,VAL_SD_D0_BAR)
stw r5,SD_D0_BAR(r4)
sync
/* Initialize DIMM1 control and BAR registers
* (same as dimm 0, next 512MB, disabled)
*/
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D1_CTRL(r4)
LOAD_U32(r5,VAL_SD_D1_BAR)
stw r5,SD_D1_BAR(r4)
sync
b sdc_init_done
check_for_200mhz:
cmpi 0,0,r3,0x0006
bne set_default_values
/* set values for 200Mhz memory speed
* Set refresh rate and timing parameters
*/
LOAD_U32(r5,0x0000061a)
stw r5,SD_REFRESH(r4)
LOAD_U32(r5,0x03083348)
stw r5,SD_TIMING(r4)
sync
/* Initialize DIMM0 control and BAR registers */
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D0_CTRL(r4)
LOAD_U32(r5,VAL_SD_D0_BAR)
stw r5,SD_D0_BAR(r4)
sync
/* Initialize DIMM1 control and BAR registers
* (same as dimm 0, next 512MB, disabled)
*/
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D1_CTRL(r4)
LOAD_U32(r5,VAL_SD_D1_BAR)
stw r5,SD_D1_BAR(r4)
sync
b sdc_init_done
set_default_values:
/* Set refresh rate and timing parameters */
LOAD_U32(r5,VAL_SD_REFRESH)
stw r5,SD_REFRESH(r4)
LOAD_U32(r5,VAL_SD_TIMING)
stw r5,SD_TIMING(r4)
sync
/* Initialize DIMM0 control and BAR registers */
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D0_CTRL(r4)
LOAD_U32(r5,VAL_SD_D0_BAR)
stw r5,SD_D0_BAR(r4)
sync
/* Initialize DIMM1 control and BAR registers
* (same as dimm 0, next 512MB, disabled)
*/
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D1_CTRL(r4)
LOAD_U32(r5,VAL_SD_D1_BAR)
stw r5,SD_D1_BAR(r4)
sync
#else /* !SDC_HARDCODED_INIT */
bl tsi108_sdram_spd /* automatically detect SDC settings */
#endif /* SDC_HARDCODED_INIT */
sdc_init_done:
#ifdef DISABLE_PBM
LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */
#else
LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */
#endif /* DISABLE_PBM */
#ifdef CONFIG_TSI108EMU
oris r5,r5,0x0010 /* set EMULATION_MODE bit */
#endif
stw r5,SD_CTRL(r4)
eieio
sync
/* Enable SDRAM access */
oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */
stw r5,SD_CTRL(r4)
sync
wait_init_complete:
lwz r5,SD_STATUS(r4)
andi. r5,r5,0x0001
/* wait until SDRAM initialization is complete */
beq wait_init_complete
/* Map SDRAM into the processor bus address space */
ori r4,r29,TSI108_PB_REG_OFFSET
/* Setup BARs associated with direct path PB<->SDRAM */
/* PB_SDRAM_BAR1:
* provides a direct path to the main system memory (cacheable SDRAM)
*/
/* BA=0,Size=512MB, ENable, No Addr.Translation */
LOAD_U32(r5, 0x00000011)
stw r5,PB_SDRAM_BAR1(r4)
sync
/* Make sure that PB_SDRAM_BAR1 decoder is set
* (to allow following immediate read from SDRAM)
*/
lwz r5,PB_SDRAM_BAR1(r4)
sync
/* PB_SDRAM_BAR2:
* provides non-cacheable alias (via the direct path) to main
* system memory.
* Size = 512MB, ENable, Addr.Translation - ON,
* BA = 0x0_40000000, TA = 0x0_00000000
*/
LOAD_U32(r5, 0x40010011)
stw r5,PB_SDRAM_BAR2(r4)
sync
/* Make sure that PB_SDRAM_BAR2 decoder is set
* (to allow following immediate read from SDRAM)
*/
lwz r5,PB_SDRAM_BAR2(r4)
sync
init_done:
/* All done. Restore LR and return. */
mtlr r19
blr
#if (0)
/*
* init_cpu1
* This routine enables CPU1 on the dual-processor system.
* Now there is only one processor in the system
*/
.global enable_cpu1
enable_cpu1:
lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */
addi r3,r3,Tsi108_Base@l
lwz r3,0(r3) /* R3 = CSR Base Addr */
ori r4,r3,TSI108_PB_REG_OFFSET
lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
ori r3,r3,0x0200 /* Set M1_EN bit */
stw r3,PB_ARB_CTRL(r4)
blr
#endif
/*
* enable_EI
* Enable CPU core external interrupt
*/
.global enable_EI
enable_EI:
mfmsr r3
ori r3,r3,0x8000 /* set EE bit */
mtmsr r3
blr
/*
* disable_EI
* Disable CPU core external interrupt
*/
.global disable_EI
disable_EI:
mfmsr r3
li r4,-32768 /* aka "li r4,0x8000" */
andc r3,r3,r4 /* clear EE bit */
mtmsr r3
blr
#ifdef ENABLE_SDRAM_ECC
/* enables SDRAM ECC */
.global enable_ECC
enable_ECC:
ori r4,r29,TSI108_SD_REG_OFFSET
lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */
ori r3,r3,0x0001 /* Set ECC_EN bit */
stw r3,SD_ECC_CTRL(r4)
blr
/*
* clear_ECC_err
* Clears all pending SDRAM ECC errors
* (normally after SDRAM scrubbing/initialization)
*/
.global clear_ECC_err
clear_ECC_err:
ori r4,r29,TSI108_SD_REG_OFFSET
ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
stw r3,SD_INT_STATUS(r4)
blr
#endif /* ENABLE_SDRAM_ECC */
#ifndef SDC_HARDCODED_INIT
/* SDRAM SPD Support */
#define SD_I2C_CTRL1 (0x400)
#define SD_I2C_CTRL2 (0x404)
#define SD_I2C_RD_DATA (0x408)
#define SD_I2C_WR_DATA (0x40C)
/*
* SDRAM SPD Support Macros
*/
#define SPD_DIMM0 (0x00000100)
#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */
#define SPD_RDIMM (0x01)
#define SPD_UDIMM (0x02)
#define SPD_CAS_3 0x8
#define SPD_CAS_4 0x10
#define SPD_CAS_5 0x20
#define ERR_NO_DIMM_FOUND (0xdb0)
#define ERR_TRAS_FAIL (0xdb1)
#define ERR_TRCD_FAIL (0xdb2)
#define ERR_TRP_FAIL (0xdb3)
#define ERR_TWR_FAIL (0xdb4)
#define ERR_UNKNOWN_PART (0xdb5)
#define ERR_NRANK_INVALID (0xdb6)
#define ERR_DIMM_SIZE (0xdb7)
#define ERR_ADDR_MODE (0xdb8)
#define ERR_RFRSH_RATE (0xdb9)
#define ERR_DIMM_TYPE (0xdba)
#define ERR_CL_VALUE (0xdbb)
#define ERR_TRFC_FAIL (0xdbc)
/* READ_SPD requirements:
* byte - byte address in SPD device (0 - 255)
* r3 = will return data read from I2C Byte location
* r4 - unchanged (SDC base addr)
* r5 - clobbered in routine (I2C status)
* r10 - number of DDR slot where first SPD device is detected
*/
#define READ_SPD(byte_num) \
addis r3, 0, byte_num@l; \
or r3, r3, r10; \
ori r3, r3, 0x0A; \
stw r3, SD_I2C_CTRL1(r4); \
li r3, I2C_CNTRL2_START; \
stw r3, SD_I2C_CTRL2(r4); \
eieio; \
sync; \
li r3, 0x100; \
1:; \
addic. r3, r3, -1; \
bne 1b; \
2:; \
lwz r5, SD_I2C_CTRL2(r4); \
rlwinm. r3,r5,0,23,23; \
bne 2b; \
rlwinm. r3,r5,0,3,3; \
lwz r3,SD_I2C_RD_DATA(r4)
#define SPD_MIN_RFRSH (0x80)
#define SPD_MAX_RFRSH (0x85)
refresh_rates: /* in nSec */
.long 15625 /* Normal (0x80) */
.long 3900 /* Reduced 0.25x (0x81) */
.long 7800 /* Reduced 0.5x (0x82) */
.long 31300 /* Extended 2x (0x83) */
.long 62500 /* Extended 4x (0x84) */
.long 125000 /* Extended 8x (0x85) */
/*
* tsi108_sdram_spd
*
* Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
* Uses registers: r4 - SDC base address (not changed)
* r9 - SDC clocking period in nSec
* Changes registers: r3,r5,r6,r7,r8,r10,r11
*/
tsi108_sdram_spd:
li r10,SPD_DIMM0
xor r11,r11,r11 /* DIMM Base Address: starts from 0 */
do_first_dimm:
/* Program Refresh Rate Register */
READ_SPD(12) /* get Refresh Rate */
beq check_next_slot
li r5, ERR_RFRSH_RATE
cmpi 0,0,r3,SPD_MIN_RFRSH
ble spd_fail
cmpi 0,0,r3,SPD_MAX_RFRSH
bgt spd_fail
addi r3,r3,-SPD_MIN_RFRSH
rlwinm r3,r3,2,0,31
lis r5,refresh_rates@h
ori r5,r5,refresh_rates@l
lwzx r5,r5,r3 /* get refresh rate in nSec */
divwu r5,r5,r9 /* calculate # of SDC clocks */
stw r5,SD_REFRESH(r4) /* Set refresh rate */
sync
/* Program SD Timing Register */
li r7, 0 /* clear r7 prior parameter collection */
READ_SPD(20) /* get DIMM type: Registered or Unbuffered */
beq spd_read_fail
li r5, ERR_DIMM_TYPE
cmpi 0,0,r3,SPD_UDIMM
beq do_cl
cmpi 0,0,r3,SPD_RDIMM
bne spd_fail
oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */
do_cl:
READ_SPD(18) /* Get CAS Latency */
beq spd_read_fail
li r5,ERR_CL_VALUE
andi. r6,r3,SPD_CAS_3
beq cl_4
li r6,3
b set_cl
cl_4:
andi. r6,r3,SPD_CAS_4
beq cl_5
li r6,4
b set_cl
cl_5:
andi. r6,r3,SPD_CAS_5
beq spd_fail
li r6,5
set_cl:
rlwimi r7,r6,24,5,7
READ_SPD(30) /* Get tRAS */
beq spd_read_fail
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_tras
addi r6,r6,1
set_tras:
li r5,ERR_TRAS_FAIL
cmpi 0,0,r6,0x0F /* max supported value */
bgt spd_fail
rlwimi r7,r6,16,12,15
READ_SPD(29) /* Get tRCD */
beq spd_read_fail
/* right shift tRCD by 2 bits as per DDR2 spec */
rlwinm r3,r3,30,2,31
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_trcd
addi r6,r6,1
set_trcd:
li r5,ERR_TRCD_FAIL
cmpi 0,0,r6,0x07 /* max supported value */
bgt spd_fail
rlwimi r7,r6,12,17,19
READ_SPD(27) /* Get tRP value */
beq spd_read_fail
rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_trp
addi r6,r6,1
set_trp:
li r5,ERR_TRP_FAIL
cmpi 0,0,r6,0x07 /* max supported value */
bgt spd_fail
rlwimi r7,r6,8,21,23
READ_SPD(36) /* Get tWR value */
beq spd_read_fail
rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_twr
addi r6,r6,1
set_twr:
addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */
li r5,ERR_TWR_FAIL
cmpi 0,0,r6,0x07 /* max supported value */
bgt spd_fail
rlwimi r7,r6,5,24,26
READ_SPD(42) /* Get tRFC */
beq spd_read_fail
li r5, ERR_TRFC_FAIL
/* Tsi108 spec: tRFC=(tRFC + 1)/2 */
addi r3,r3,1
rlwinm. r3,r3,31,1,31 /* divide by 2 */
beq spd_fail
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_trfc
addi r6,r6,1
set_trfc:
cmpi 0,0,r6,0x1F /* max supported value */
bgt spd_fail
rlwimi r7,r6,0,27,31
stw r7,SD_TIMING(r4)
sync
/*
* The following two registers are set on per-DIMM basis.
* The SD_REFRESH and SD_TIMING settings are common for both DIMMS
*/
do_each_dimm:
/* Program SDRAM DIMM Control Register */
li r7, 0 /* clear r7 prior parameter collection */
READ_SPD(13) /* Get Primary SDRAM Width */
beq spd_read_fail
cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */
beq do_nbank
oris r7,r7,0x0010 /* Set MEM_WIDTH bit */
do_nbank:
READ_SPD(17) /* Get Number of banks on SDRAM device */
beq spd_read_fail
/* Grendel only distinguish betw. 4 or 8-bank memory parts */
li r5,ERR_UNKNOWN_PART /* non-supported memory part */
cmpi 0,0,r3,4
beq do_nrank
cmpi 0,0,r3,8
bne spd_fail
ori r7,r7,0x1000
do_nrank:
READ_SPD(5) /* Get # of Ranks */
beq spd_read_fail
li r5,ERR_NRANK_INVALID
andi. r6,r3,0x7 /* Use bits [2..0] only */
beq do_addr_mode
cmpi 0,0,r6,1
bgt spd_fail
rlwimi r7,r6,8,23,23
do_addr_mode:
READ_SPD(4) /* Get # of Column Addresses */
beq spd_read_fail
li r5, ERR_ADDR_MODE
andi. r3,r3,0x0f /* cut off reserved bits */
cmpi 0,0,r3,8
ble spd_fail
cmpi 0,0,r3,15
bgt spd_fail
addi r6,r3,-8 /* calculate ADDR_MODE parameter */
rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */
set_dimm_ctrl:
#ifdef SDC_AUTOPRECH_EN
oris r7,r7,0x0001 /* set auto precharge EN bit */
#endif
ori r7,r7,1 /* set ENABLE bit */
cmpi 0,0,r10,SPD_DIMM0
bne 1f
stw r7,SD_D0_CTRL(r4)
sync
b set_dimm_bar
1:
stw r7,SD_D1_CTRL(r4)
sync
/* Program SDRAM DIMMx Base Address Register */
set_dimm_bar:
READ_SPD(5) /* get # of Ranks */
beq spd_read_fail
andi. r7,r3,0x7
addi r7,r7,1
READ_SPD(31) /* Read DIMM rank density */
beq spd_read_fail
rlwinm r5,r3,27,29,31
rlwinm r6,r3,3,24,28
or r5,r6,r5 /* r5 = Normalized Rank Density byte */
lis r8, 0x0080 /* 128MB >> 4 */
mullw r8,r8,r5 /* r8 = (rank_size >> 4) */
mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */
neg r7,r8
rlwinm r7,r7,28,4,31
or r7,r7,r11 /* set ADDR field */
rlwinm r8,r8,12,20,31
add r11,r11,r8 /* set Base Addr for next DIMM */
cmpi 0,0,r10,SPD_DIMM0
bne set_dimm1_size
stw r7,SD_D0_BAR(r4)
sync
li r10,SPD_DIMM1
READ_SPD(0)
bne do_each_dimm
b spd_done
set_dimm1_size:
stw r7,SD_D1_BAR(r4)
sync
spd_done:
blr
check_next_slot:
cmpi 0,0,r10,SPD_DIMM1
beq spd_read_fail
li r10,SPD_DIMM1
b do_first_dimm
spd_read_fail:
ori r3,r0,0xdead
b err_hung
spd_fail:
li r3,0x0bad
sync
err_hung: /* hang here for debugging */
nop
nop
b err_hung
#endif /* !SDC_HARDCODED_INIT */

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#
# Copyright (c) 2005 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Flash address
TEXT_BASE = 0xFF000000
# RAM address
#TEXT_BASE = 0x00400000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float

107
board/mpc7448hpc2/mpc7448hpc2.c Normal file
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/*
* (C) Copyright 2005 Freescale Semiconductor, Inc.
*
* Roy Zang <tie-fei.zang@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* modifications for the Tsi108 Emul Board by avb@Tundra
*/
/*
* board support/init functions for the
* Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
*/
#include <common.h>
#include <74xx_7xx.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup (void *blob, bd_t *bd);
#endif
#undef DEBUG
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern void tsi108_init_f (void);
int display_mem_map (void);
void after_reloc (ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
/*
* Jump to the main U-Boot board init code
*/
board_init_r ((gd_t *) gd, dest_addr);
/* NOTREACHED */
}
/*
* Check Board Identity:
* report board type
*/
int checkboard (void)
{
int l_type = 0;
printf ("BOARD: %s\n", CFG_BOARD_NAME);
return (l_type);
}
/*
* Read Processor ID:
*
* report calling processor number
*/
int read_pid (void)
{
return 0; /* we are on single CPU platform for a while */
}
long int dram_size (int board_type)
{
return 0x20000000; /* 256M bytes */
}
long int initdram (int board_type)
{
return dram_size (board_type);
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup (void *blob, bd_t *bd)
{
u32 *p;
int len;
ft_cpu_setup (blob, bd);
p = ft_get_prop (blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32 (bd->bi_memstart);
*p = cpu_to_be32 (bd->bi_memsize);
}
}
#endif

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/*****************************************************************************
* (C) Copyright 2003; Tundra Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*****************************************************************************/
/*----------------------------------------------------------------------------
* FILENAME: tsi108_init.c
*
* Originator: Alex Bounine
*
* DESCRIPTION:
* Initialization code for the Tundra Tsi108 bridge chip
*---------------------------------------------------------------------------*/
#include <common.h>
#include <74xx_7xx.h>
#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <tsi108.h>
extern void mpicInit (int verbose);
/*
* Configuration Options
*/
typedef struct {
ulong upper;
ulong lower;
} PB2OCN_LUT_ENTRY;
PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
/* 0 - 7 */
{0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
/* 8 - 15 */
{0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
/* 16 - 23 */
{0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
/* 24 - 31 */
{0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
{0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
{0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
{0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
{0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
};
#ifdef CFG_CLK_SPREAD
typedef struct {
ulong ctrl0;
ulong ctrl1;
} PLL_CTRL_SET;
/*
* Clock Generator SPLL0 initialization values
* PLL0 configuration table for various PB_CLKO freq.
* Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
* Fout depends on required PB_CLKO. Based on Fref = 33 MHz
*/
static PLL_CTRL_SET pll0_config[8] = {
{0x00000000, 0x00000000}, /* 0: bypass */
{0x00000000, 0x00000000}, /* 1: reserved */
{0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
{0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
{0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
{0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
{0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
{0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
};
#endif /* CFG_CLK_SPREAD */
/*
* Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
* (based on recommended Tsi108 reference clock 33MHz)
*/
static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
/*
* get_board_bus_clk ()
*
* returns the bus clock in Hz.
*/
unsigned long get_board_bus_clk (void)
{
ulong i;
/* Detect PB clock freq. */
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
return pb_clk_sel[i] * 1000000;
}
/*
* board_early_init_f ()
*
* board-specific initialization executed from flash
*/
int board_early_init_f (void)
{
DECLARE_GLOBAL_DATA_PTR;
ulong i;
gd->mem_clk = 0;
i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
CG_PWRUP_STATUS);
i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
switch (i) {
case 0: /* external clock */
printf ("Using external clock\n");
break;
case 1: /* system clock */
gd->mem_clk = gd->bus_clk;
break;
case 4: /* 133 MHz */
case 5: /* 166 MHz */
case 6: /* 200 MHz */
gd->mem_clk = pb_clk_sel[i] * 1000000;
break;
default:
printf ("Invalid DDR2 clock setting\n");
return -1;
}
printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
return 0;
}
/*
* board_early_init_r() - Tsi108 initialization function executed right after
* relocation. Contains code that cannot be executed from flash.
*/
int board_early_init_r (void)
{
ulong temp, i;
ulong reg_val;
volatile ulong *reg_ptr;
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
for (i = 0; i < 32; i++) {
*reg_ptr++ = 0x00000201; /* SWAP ENABLED */
*reg_ptr++ = 0x00;
}
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
0x80000001);
__asm__ __volatile__ ("sync");
/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
* read from SDRAM)
*/
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
__asm__ __volatile__ ("sync");
/*
* Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
* processor bus address space. Immediately after reset LUT and address
* translation are disabled for this BAR. Now we have to initialize LUT
* and switch from the BOOT mode to the normal operation mode.
*
* The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
* and covers 512MB of address space. To allow larger aperture we also
* have to relocate register window of Tsi108
*
* Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
* mode.
*
* initialize pointer to LUT associated with PB_OCN_BAR1
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
for (i = 0; i < 32; i++) {
*reg_ptr++ = pb2ocn_lut1[i].lower;
*reg_ptr++ = pb2ocn_lut1[i].upper;
}
__asm__ __volatile__ ("sync");
/* Base addresses for CS0, CS1, CS2, CS3 */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
0x00000000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
0x00100000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
0x00200000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
0x00300000);
__asm__ __volatile__ ("sync");
/* Masks for HLP banks */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
/* Set CTRL0 values for banks */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
0x7FFC44C2);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
0x7FFC44C0);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
0x7FFC44C0);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
0x7FFC44C2);
__asm__ __volatile__ ("sync");
/* Set banks to latched mode, enabled, and other default settings */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
/*
* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
0xE0000011);
__asm__ __volatile__ ("sync");
/* Make sure that OCN_BAR2 decoder is set (to allow following
* immediate read from SDRAM)
*/
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
__asm__ __volatile__ ("sync");
/*
* SRI: At this point we have enabled the HLP banks. That means we can
* now read from the NVRAM and initialize the environment variables.
* We will over-ride the env_init called in board_init_f
* This is really a work-around because, the HLP bank 1
* where NVRAM resides is not visible during board_init_f
* (lib_ppc/board.c)
* Alternatively, we could use the I2C EEPROM at start-up to configure
* and enable all HLP banks and not just HLP 0 as is being done for
* Taiga Rev. 2.
*/
env_init ();
#ifndef DISABLE_PBM
/*
* For IBM processors we have to set Address-Only commands generated
* by PBM that are different from ones set after reset.
*/
temp = get_cpu_type ();
if ((CPU_750FX == temp) || (CPU_750GX == temp))
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
0x00009955);
#endif /* DISABLE_PBM */
#ifdef CONFIG_PCI
/*
* Initialize PCI/X block
*/
/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_PFAB_BAR0_UPPER, 0);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
0xFB000001);
__asm__ __volatile__ ("sync");
/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
temp = in32(CFG_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
temp &= ~0xFF00; /* Clear the BUS_NUM field */
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
temp);
/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
0);
__asm__ __volatile__ ("sync");
/* This register is on the PCI side to interpret the address it receives
* and maps it as a IO address.
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
0xFA000001);
__asm__ __volatile__ ("sync");
/*
* Map PCI/X Memory Space
*
* Transactions directed from OCM to PCI Memory Space are directed
* from PB to PCI
* unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
* If address remapping is required the corresponding PCI_PFAB_MEM32
* and PCI_PFAB_PFMx register groups have to be configured.
*
* Map the path from the PCI/X bus into the system memory
*
* The memory mapped window assotiated with PCI P2O_BAR2 provides
* access to the system memory without address remapping.
* All system memory is opened for accesses initiated by PCI/X bus
* masters.
*
* Initialize LUT associated with PCI P2O_BAR2
*
* set pointer to LUT associated with PCI P2O_BAR2
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
#ifdef DISABLE_PBM
/* In case when PBM is disabled (no HW supported cache snoopng on PB)
* P2O_BAR2 is directly mapped into the system memory without address
* translation.
*/
reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
for (i = 0; i < 32; i++) {
*reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
*reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
}
/* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
reg_val = 0x00007500;
#else
reg_val = 0x00000002; /* Destination port = PBM */
for (i = 0; i < 32; i++) {
*reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
*reg_ptr++ = 0x40000000;
/* offset = 16MB, address translation is enabled to allow byte swapping */
reg_val += 0x01000000;
}
/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
reg_val = 0x00007100;
#endif
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__ ("sync");
/* Set 64-bit PCI bus address for system memory
* ( 0 is the best choice for easy mapping)
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
0x00000000);
__asm__ __volatile__ ("sync");
#ifndef DISABLE_PBM
/*
* The memory mapped window assotiated with PCI P2O_BAR3 provides
* access to the system memory using SDRAM OCN port and address
* translation. This is alternative way to access SDRAM from PCI
* required for Tsi108 emulation testing.
* All system memory is opened for accesses initiated by
* PCI/X bus masters.
*
* Initialize LUT associated with PCI P2O_BAR3
*
* set pointer to LUT associated with PCI P2O_BAR3
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
reg_val = 0x00000004; /* Destination port = SDC */
for (i = 0; i < 32; i++) {
*reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
*reg_ptr++ = 0;
/* offset = 16MB, address translation is enabled to allow byte swapping */
reg_val += 0x01000000;
}
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
reg_val =
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_P2O_PAGE_SIZES);
reg_val &= ~0x00FF;
reg_val |= 0x0071;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__ ("sync");
/* Set 64-bit base PCI bus address for window (0x20000000) */
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
0x20000000);
__asm__ __volatile__ ("sync");
#endif /* !DISABLE_PBM */
#ifdef ENABLE_PCI_CSR_BAR
/* open if required access to Tsi108 CSRs from the PCI/X bus */
/* enable BAR0 on the PCI/X bus */
reg_val = in32(CFG_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
reg_val |= 0x02;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
reg_val);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
CFG_TSI108_CSR_BASE);
__asm__ __volatile__ ("sync");
#endif
/*
* Finally enable PCI/X Bus Master and Memory Space access
*/
reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
reg_val |= 0x06;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
__asm__ __volatile__ ("sync");
#endif /* CONFIG_PCI */
/*
* Initialize MPIC outputs (interrupt pins):
* Interrupt routing on the Grendel Emul. Board:
* PB_INT[0] -> INT (CPU0)
* PB_INT[1] -> INT (CPU1)
* PB_INT[2] -> MCP (CPU0)
* PB_INT[3] -> MCP (CPU1)
* Set interrupt controller outputs as Level_Sensitive/Active_Low
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
__asm__ __volatile__ ("sync");
/*
* Ensure that Machine Check exception is enabled
* We need it to support PCI Bus probing (configuration reads)
*/
reg_val = mfmsr ();
mtmsr(reg_val | MSR_ME);
return 0;
}
/*
* Needed to print out L2 cache info
* used in the misc_init_r function
*/
unsigned long get_l2cr (void)
{
unsigned long l2controlreg;
asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
return l2controlreg;
}
/*
* misc_init_r()
*
* various things to do after relocation
*
*/
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
ulong i;
/* Ensure that Spread-Spectrum is disabled */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x002e0044); /* D = 0.25% */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
0x00000039); /* BWADJ */
/* Initialize PLL0: CG_PB_CLKO */
/* Detect PB clock freq. */
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
/* Wait and set SSEN for both PLL0 and 1 */
udelay (1000);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x802e0044); /* D=0.25% */
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
0x80000000 | pll0_config[i].ctrl0);
#endif /* CFG_CLK_SPREAD */
#ifdef CFG_L2
l2cache_enable ();
#endif
printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
/*
* All the information needed to print the cache details is avaiblable
* at this point i.e. above call to l2cache_enable is the very last
* thing done with regards to enabling diabling the cache.
* So this seems like a good place to print all this information
*/
printf ("CACHE: ");
switch (get_cpu_type()) {
case CPU_7447A:
printf ("L1 Instruction cache - 32KB 8-way");
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("L1 Data cache - 32KB 8-way");
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("Unified L2 cache - 512KB 8-way");
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("\n");
break;
case CPU_7448:
printf ("L1 Instruction cache - 32KB 8-way");
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("L1 Data cache - 32KB 8-way");
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("Unified L2 cache - 1MB 8-way");
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
break;
default:
break;
}
return 0;
}

136
board/mpc7448hpc2/u-boot.lds Normal file
View File

@ -0,0 +1,136 @@
/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board.
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

41
board/mpc8360emds/mpc8360emds.c
View File

@ -31,6 +31,10 @@
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GETH1 */
@ -658,22 +662,45 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc,
" - disables injects\n" " - re-inits memory");
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
&& defined(CONFIG_OF_BOARD_SETUP)
/*
* Prototypes of functions that we use.
*/
void ft_cpu_setup(void *blob, bd_t *bd);
#ifdef CONFIG_PCI
void ft_pci_setup(void *blob, bd_t *bd);
#endif
void
ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_LIBFDT)
int nodeoffset;
int tmp[2];
nodeoffset = fdt_path_offset (fdt, "/memory");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(bd->bi_memstart);
tmp[1] = cpu_to_be32(bd->bi_memsize);
fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp));
}
#else
u32 *p;
int len;
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
}
#endif
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
}
#endif /* CONFIG_OF_x */

20
board/mpc8360emds/pci.c
View File

@ -21,6 +21,10 @@
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#endif
#include <asm/fsl_i2c.h>
@ -299,6 +303,22 @@ void pci_init_board(void)
}
#endif /* CONFIG_PCISLAVE */
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
nodeoffset = fdt_path_offset (fdt, "/" OF_SOC "/pci@8500");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(hose[0].first_busno);
tmp[1] = cpu_to_be32(hose[0].last_busno);
err = fdt_setprop(fdt, nodeoffset, "bus-range", tmp, sizeof(tmp));
}
}
#endif /* CONFIG_OF_LIBFDT */
#ifdef CONFIG_OF_FLAT_TREE
void
ft_pci_setup(void *blob, bd_t *bd)

4
board/mpc8641hpcn/Makefile
View File

@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o pixis.o sys_eeprom.o
COBJS := $(BOARD).o sys_eeprom.o \
../freescale/common/pixis.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

113
board/mpc8641hpcn/mpc8641hpcn.c
View File

@ -1,9 +1,5 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
* Copyright 2006, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -25,18 +21,18 @@
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <spd.h>
#include <asm/io.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup(void *blob, bd_t *bd);
#endif
#include "pixis.h"
#include "../freescale/common/pixis.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
@ -258,109 +254,6 @@ ft_board_setup(void *blob, bd_t *bd)
#endif
void
mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char cmd;
ulong val;
ulong corepll;
/*
* No args is a simple reset request.
*/
if (argc <= 1) {
out8(PIXIS_BASE + PIXIS_RST, 0);
/* not reached */
}
cmd = argv[1][1];
switch (cmd) {
case 'f': /* reset with frequency changed */
if (argc < 5)
goto my_usage;
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
set_px_go();
} else
goto my_usage;
while (1) ; /* Not reached */
case 'l':
if (argv[2][1] == 'f') {
read_from_px_regs(0);
read_from_px_regs_altbank(0);
/* reset with frequency changed */
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
corepll = strfractoint(argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],
NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
set_px_go_with_watchdog();
} else
goto my_usage;
while (1) ; /* Not reached */
} else if (argv[2][1] == 'd') {
/*
* Reset from alternate bank without changing
* frequencies but with watchdog timer enabled.
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog();
while (1) ; /* Not reached */
} else {
/*
* Reset from next bank without changing
* frequency and without watchdog timer enabled.
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if (argc > 2)
goto my_usage;
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Resetting board to boot from the other bank....\n");
set_px_go();
}
default:
goto my_usage;
}
my_usage:
puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
puts(" reset altbank [wd]\n");
puts("For example: reset cf 40 2.5 10\n");
puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
}
/*
* get_board_sys_clk
* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ

2
board/mpc8641hpcn/u-boot.lds
View File

@ -120,10 +120,12 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;

3
board/nc650/config.mk
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
# (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
# (C) Copyright 2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
@ -27,4 +27,3 @@
#
TEXT_BASE = 0x40700000
BOARDLIBS = $(obj)drivers/nand/libnand.a

6
board/nc650/nc650.c
View File

@ -177,16 +177,14 @@ long int initdram (int board_type)
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);

2
board/uc101/uc101.c
View File

@ -221,6 +221,8 @@ long int initdram (int board_type)
int checkboard (void)
{
puts ("Board: MAN UC101\n");
/* clear the Display */
*(char *)(CFG_DISP_CWORD) = 0x80;
return 0;
}

65
board/xilinx/ml401/Makefile Normal file
View File

@ -0,0 +1,65 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
$(shell mkdir -p $(obj)../xilinx_enet)
endif
INCS := -I../common -I../xilinx_enet
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
../common/xbasic_types.o ../common/xdma_channel.o \
../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
../common/xversion.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

32
board/xilinx/ml401/config.mk Normal file
View File

@ -0,0 +1,32 @@
#
# (C) Copyright 2007 Michal Simek
#
# Michal SIMEK <monstr@monstr.eu>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
#
TEXT_BASE = 0x12000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift

49
board/xilinx/ml401/ml401.c Normal file
View File

@ -0,0 +1,49 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This is a board specific file. It's OK to include board specific
* header files */
#include <common.h>
#include <config.h>
void do_reset (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) =
++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
#endif
#ifdef CFG_RESET_ADDRESS
puts ("Reseting board\n");
asm ("bra r0");
#endif
}
int gpio_init (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
#endif
return 0;
}

67
board/xilinx/ml401/u-boot.lds Normal file
View File

@ -0,0 +1,67 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(microblaze)
ENTRY(_start)
SECTIONS
{
.text ALIGN(0x4):
{
__text_start = .;
cpu/microblaze/start.o (.text)
*(.text)
__text_end = .;
}
.rodata ALIGN(0x4):
{
__rodata_start = .;
*(.rodata)
__rodata_end = .;
}
.data ALIGN(0x4):
{
__data_start = .;
*(.data)
__data_end = .;
}
.u_boot_cmd ALIGN(0x4):
{
. = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
.bss ALIGN(0x4):
{
__bss_start = .;
*(.bss)
__bss_end = .;
}
__end = . ;
}

67
board/xilinx/ml401/xparameters.h Normal file
View File

@ -0,0 +1,67 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 6.3 EDK_Gmm.12.3
*/
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 66666667
/* Interrupt controller is intc_0 */
#define XILINX_INTC_BASEADDR 0xd1000fc0
#define XILINX_INTC_NUM_INTR_INPUTS 12
/* Timer pheriphery is opb_timer_0 */
#define XILINX_TIMER_BASEADDR 0xa2000000
#define XILINX_TIMER_IRQ 0
/* Uart pheriphery is console_uart */
#define XILINX_UART_BASEADDR 0xa0000000
#define XILINX_UART_BAUDRATE 115200
/* GPIO is opb_gpio_0*/
#define XILINX_GPIO_BASEADDR 0x90000000
/* Flash Memory is opb_emc_0 */
#define XILINX_FLASH_START 0x28000000
#define XILINX_FLASH_SIZE 0x00800000
/* Main Memory is plb_ddr_0 */
#define XILINX_RAM_START 0x10000000
#define XILINX_RAM_SIZE 0x10000000
/* Sysace Controller is opb_sysace_0 */
#define XILINX_SYSACE_BASEADDR 0xCF000000
#define XILINX_SYSACE_HIGHADDR 0xCF0001FF
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is opb_ethernet_0 */
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1

4
board/xilinx/xilinx_enet/emac_adapter.c
View File

@ -147,7 +147,11 @@ eth_rx(void)
RecvFrameLength = PKTSIZE;
Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
if (Result == XST_SUCCESS) {
#ifndef CONFIG_EMACLITE
NetReceive((uchar *)etherrxbuff, RecvFrameLength);
#else
NetReceive(etherrxbuff, RecvFrameLength);
#endif
return (1);
} else {
return (0);

65
board/xilinx/xupv2p/Makefile Normal file
View File

@ -0,0 +1,65 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
$(shell mkdir -p $(obj)../xilinx_enet)
endif
INCS := -I../common -I../xilinx_enet
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
../common/xbasic_types.o ../common/xdma_channel.o \
../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
../common/xversion.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

32
board/xilinx/xupv2p/config.mk Normal file
View File

@ -0,0 +1,32 @@
#
# (C) Copyright 2007 Michal Simek
#
# Michal SIMEK <monstr@monstr.eu>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
#
TEXT_BASE = 0x38000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift

67
board/xilinx/xupv2p/u-boot.lds Normal file
View File

@ -0,0 +1,67 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(microblaze)
ENTRY(_start)
SECTIONS
{
.text ALIGN(0x4):
{
__text_start = .;
cpu/microblaze/start.o (.text)
*(.text)
__text_end = .;
}
.rodata ALIGN(0x4):
{
__rodata_start = .;
*(.rodata)
__rodata_end = .;
}
.data ALIGN(0x4):
{
__data_start = .;
*(.data)
__data_end = .;
}
.u_boot_cmd ALIGN(0x4):
{
. = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
.bss ALIGN(0x4):
{
__bss_start = .;
*(.bss)
__bss_end = .;
}
__end = . ;
}

64
board/xilinx/xupv2p/xparameters.h Normal file
View File

@ -0,0 +1,64 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
*/
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 100000000
/* Interrupt controller is opb_intc_0 */
#define XILINX_INTC_BASEADDR 0x41200000
#define XILINX_INTC_NUM_INTR_INPUTS 11
/* Timer pheriphery is opb_timer_1 */
#define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 1
/* Uart pheriphery is RS232_Uart_1 */
#define XILINX_UART_BASEADDR 0x40600000
#define XILINX_UART_BAUDRATE 115200
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
/* FLASH doesn't exist none */
/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
#define XILINX_RAM_START 0x30000000
#define XILINX_RAM_SIZE 0x10000000
/* Sysace Controller is SysACE_CompactFlash */
#define XILINX_SYSACE_BASEADDR 0x41800000
#define XILINX_SYSACE_HIGHADDR 0x4180ffff
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is Ethernet_MAC */
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1

49
board/xilinx/xupv2p/xupv2p.c Normal file
View File

@ -0,0 +1,49 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This is a board specific file. It's OK to include board specific
* header files */
#include <common.h>
#include <config.h>
void do_reset (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) =
++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
#endif
#ifdef CFG_RESET_ADDRESS
puts ("Reseting board\n");
asm ("bra r0");
#endif
}
int gpio_init (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
#endif
return 0;
}

4
common/Makefile
View File

@ -32,7 +32,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
cmd_cache.o cmd_console.o \
cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \
cmd_eeprom.o cmd_elf.o cmd_ext2.o \
cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
cmd_fat.o cmd_fdc.o cmd_fdt.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
cmd_load.o cmd_log.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
@ -45,7 +45,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
env_nvram.o env_nowhere.o \
exports.o \
flash.o fpga.o ft_build.o \
fdt_support.o flash.o fpga.o ft_build.o \
hush.o kgdb.o lcd.o lists.o lynxkdi.o \
memsize.o miiphybb.o miiphyutil.o \
s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \

26
common/cmd_bdinfo.c
View File

@ -180,6 +180,32 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
#elif defined(CONFIG_MICROBLAZE) /* ! PPC, which leaves Microblaze */
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int i;
bd_t *bd = gd->bd;
print_num ("mem start ", (ulong)bd->bi_memstart);
print_num ("mem size ", (ulong)bd->bi_memsize);
print_num ("flash start ", (ulong)bd->bi_flashstart);
print_num ("flash size ", (ulong)bd->bi_flashsize);
print_num ("flash offset ", (ulong)bd->bi_flashoffset);
#if defined(CFG_SRAM_BASE)
print_num ("sram start ", (ulong)bd->bi_sramstart);
print_num ("sram size ", (ulong)bd->bi_sramsize);
#endif
#if defined(CFG_CMD_NET)
puts ("ethaddr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
puts ("\nip_addr = ");
print_IPaddr (bd->bi_ip_addr);
#endif
printf ("\nbaudrate = %d bps\n", (ulong)bd->bi_baudrate);
return 0;
}
#else /* ! PPC, which leaves MIPS */

140
common/cmd_bootm.c
View File

@ -34,7 +34,12 @@
#include <environment.h>
#include <asm/byteorder.h>
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_LIBFDT)
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
@ -242,26 +247,26 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
len_ptr = (ulong *)data;
#if defined(__PPC__)
if (hdr->ih_arch != IH_CPU_PPC)
#elif defined(__ARM__)
#if defined(__ARM__)
if (hdr->ih_arch != IH_CPU_ARM)
#elif defined(__avr32__)
if (hdr->ih_arch != IH_CPU_AVR32)
#elif defined(__bfin__)
if (hdr->ih_arch != IH_CPU_BLACKFIN)
#elif defined(__I386__)
if (hdr->ih_arch != IH_CPU_I386)
#elif defined(__mips__)
if (hdr->ih_arch != IH_CPU_MIPS)
#elif defined(__nios__)
if (hdr->ih_arch != IH_CPU_NIOS)
#elif defined(__M68K__)
if (hdr->ih_arch != IH_CPU_M68K)
#elif defined(__microblaze__)
if (hdr->ih_arch != IH_CPU_MICROBLAZE)
#elif defined(__mips__)
if (hdr->ih_arch != IH_CPU_MIPS)
#elif defined(__nios__)
if (hdr->ih_arch != IH_CPU_NIOS)
#elif defined(__nios2__)
if (hdr->ih_arch != IH_CPU_NIOS2)
#elif defined(__blackfin__)
if (hdr->ih_arch != IH_CPU_BLACKFIN)
#elif defined(__avr32__)
if (hdr->ih_arch != IH_CPU_AVR32)
#elif defined(__PPC__)
if (hdr->ih_arch != IH_CPU_PPC)
#else
# error Unknown CPU type
#endif
@ -467,7 +472,7 @@ U_BOOT_CMD(
"[addr [arg ...]]\n - boot application image stored in memory\n"
"\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
"\t'arg' can be the address of an initrd image\n"
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
"\tWhen booting a Linux kernel which requires a flat device-tree\n"
"\ta third argument is required which is the address of the of the\n"
"\tdevice-tree blob. To boot that kernel without an initrd image,\n"
@ -529,7 +534,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
bd_t *kbd;
void (*kernel)(bd_t *, ulong, ulong, ulong, ulong);
image_header_t *hdr = &header;
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
char *of_flat_tree = NULL;
ulong of_data = 0;
#endif
@ -622,7 +627,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
* Check if there is an initrd image
*/
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
/* Look for a '-' which indicates to ignore the ramdisk argument */
if (argc >= 3 && strcmp(argv[2], "-") == 0) {
debug ("Skipping initrd\n");
@ -739,12 +744,15 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
len = data = 0;
}
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
if(argc > 3) {
of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
hdr = (image_header_t *)of_flat_tree;
if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
#if defined(CONFIG_OF_LIBFDT)
if (fdt_check_header(of_flat_tree) == 0) {
#else
if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
#endif
#ifndef CFG_NO_FLASH
if (addr2info((ulong)of_flat_tree) != NULL)
of_data = (ulong)of_flat_tree;
@ -787,7 +795,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
printf("ERROR: uImage is not uncompressed\n");
return;
}
#if defined(CONFIG_OF_LIBFDT)
if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) == 0) {
#else
if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
#endif
printf ("ERROR: uImage data is not a flat device tree\n");
return;
}
@ -824,12 +836,20 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
of_data += 4 - tail;
}
#if defined(CONFIG_OF_LIBFDT)
if (fdt_check_header((void *)of_data) != 0) {
#else
if (((struct boot_param_header *)of_data)->magic != OF_DT_HEADER) {
#endif
printf ("ERROR: image is not a flat device tree\n");
return;
}
#if defined(CONFIG_OF_LIBFDT)
if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) {
#else
if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
#endif
printf ("ERROR: flat device tree size does not agree with image\n");
return;
}
@ -913,7 +933,52 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
unlock_ram_in_cache();
#endif
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_LIBFDT)
/* move of_flat_tree if needed */
if (of_data) {
int err;
ulong of_start, of_len;
of_len = be32_to_cpu(fdt_totalsize(of_data));
/* position on a 4K boundary before the initrd/kbd */
if (initrd_start)
of_start = initrd_start - of_len;
else
of_start = (ulong)kbd - of_len;
of_start &= ~(4096 - 1); /* align on page */
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
of_data, of_data + of_len - 1, of_len, of_len);
of_flat_tree = (char *)of_start;
printf (" Loading Device Tree to %08lx, end %08lx ... ",
of_start, of_start + of_len - 1);
err = fdt_open_into((void *)of_start, (void *)of_data, of_len);
if (err != 0) {
printf ("libfdt: %s " __FILE__ " %d\n", fdt_strerror(err), __LINE__);
}
/*
* Add the chosen node if it doesn't exist, add the env and bd_t
* if the user wants it (the logic is in the subroutines).
*/
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
return;
}
#ifdef CONFIG_OF_HAS_UBOOT_ENV
if (fdt_env(of_flat_tree) < 0) {
printf("Failed creating the /u-boot-env node, aborting.\n");
return;
}
#endif
#ifdef CONFIG_OF_HAS_BD_T
if (fdt_bd_t(of_flat_tree) < 0) {
printf("Failed creating the /bd_t node, aborting.\n");
return;
}
#endif
}
#endif
#if defined(CONFIG_OF_FLAT_TREE)
/* move of_flat_tree if needed */
if (of_data) {
ulong of_start, of_len;
@ -942,13 +1007,13 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
* r6: Start of command line string
* r7: End of command line string
*/
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
if (!of_flat_tree) /* no device tree; boot old style */
#endif
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
/* does not return */
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
/*
* Linux Kernel Parameters (passing device tree):
* r3: ptr to OF flat tree, followed by the board info data
@ -957,8 +1022,28 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
* r6: NULL
* r7: NULL
*/
#if defined(CONFIG_OF_FLAT_TREE)
ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
/* ft_dump_blob(of_flat_tree); */
#endif
#if defined(CONFIG_OF_LIBFDT)
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
return;
}
#ifdef CONFIG_OF_HAS_UBOOT_ENV
if (fdt_env(of_flat_tree) < 0) {
printf("Failed creating the /u-boot-env node, aborting.\n");
return;
}
#endif
#ifdef CONFIG_OF_HAS_BD_T
if (fdt_bd_t(of_flat_tree) < 0) {
printf("Failed creating the /bd_t node, aborting.\n");
return;
}
#endif
#endif /* if defined(CONFIG_OF_LIBFDT) */
(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
#endif
@ -1354,19 +1439,20 @@ print_type (image_header_t *hdr)
case IH_CPU_ALPHA: arch = "Alpha"; break;
case IH_CPU_ARM: arch = "ARM"; break;
case IH_CPU_AVR32: arch = "AVR32"; break;
case IH_CPU_BLACKFIN: arch = "Blackfin"; break;
case IH_CPU_I386: arch = "Intel x86"; break;
case IH_CPU_IA64: arch = "IA64"; break;
case IH_CPU_MIPS: arch = "MIPS"; break;
case IH_CPU_M68K: arch = "M68K"; break;
case IH_CPU_MICROBLAZE: arch = "Microblaze"; break;
case IH_CPU_MIPS64: arch = "MIPS 64 Bit"; break;
case IH_CPU_MIPS: arch = "MIPS"; break;
case IH_CPU_NIOS2: arch = "Nios-II"; break;
case IH_CPU_NIOS: arch = "Nios"; break;
case IH_CPU_PPC: arch = "PowerPC"; break;
case IH_CPU_S390: arch = "IBM S390"; break;
case IH_CPU_SH: arch = "SuperH"; break;
case IH_CPU_SPARC: arch = "SPARC"; break;
case IH_CPU_SPARC64: arch = "SPARC 64 Bit"; break;
case IH_CPU_M68K: arch = "M68K"; break;
case IH_CPU_MICROBLAZE: arch = "Microblaze"; break;
case IH_CPU_NIOS: arch = "Nios"; break;
case IH_CPU_NIOS2: arch = "Nios-II"; break;
case IH_CPU_SPARC: arch = "SPARC"; break;
default: arch = "Unknown Architecture"; break;
}

635
common/cmd_fdt.c Normal file
View File

@ -0,0 +1,635 @@
/*
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
* Based on code written by:
* Pantelis Antoniou <pantelis.antoniou@gmail.com> and
* Matthew McClintock <msm@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <linux/ctype.h>
#include <linux/types.h>
#ifdef CONFIG_OF_LIBFDT
#include <asm/global_data.h>
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#define MAX_LEVEL 32 /* how deeply nested we will go */
#define SCRATCHPAD 1024 /* bytes of scratchpad memory */
/*
* Global data (for the gd->bd)
*/
DECLARE_GLOBAL_DATA_PTR;
/*
* Scratchpad memory.
*/
static char data[SCRATCHPAD];
/*
* Function prototypes/declarations.
*/
static int fdt_valid(void);
static void print_data(const void *data, int len);
/*
* Flattened Device Tree command, see the help for parameter definitions.
*/
int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char op;
if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/*
* Figure out which subcommand was given
*/
op = argv[1][0];
/********************************************************************
* Set the address of the fdt
********************************************************************/
if (op == 'a') {
/*
* Set the address [and length] of the fdt.
*/
fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16);
if (!fdt_valid()) {
return 1;
}
if (argc >= 4) {
int len;
int err;
/*
* Optional new length
*/
len = simple_strtoul(argv[3], NULL, 16);
if (len < fdt_totalsize(fdt)) {
printf ("New length %d < existing length %d, ignoring.\n",
len, fdt_totalsize(fdt));
} else {
/*
* Open in place with a new length.
*/
err = fdt_open_into(fdt, fdt, len);
if (err != 0) {
printf ("libfdt: %s\n", fdt_strerror(err));
}
}
}
/********************************************************************
* Move the fdt
********************************************************************/
} else if (op == 'm') {
struct fdt_header *newaddr;
int len;
int err;
if (argc != 5) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/*
* Set the address and length of the fdt.
*/
fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16);
if (!fdt_valid()) {
return 1;
}
newaddr = (struct fdt_header *)simple_strtoul(argv[3], NULL, 16);
len = simple_strtoul(argv[4], NULL, 16);
if (len < fdt_totalsize(fdt)) {
printf ("New length %d < existing length %d, aborting.\n",
len, fdt_totalsize(fdt));
return 1;
}
/*
* Copy to the new location.
*/
err = fdt_open_into(fdt, newaddr, len);
if (err != 0) {
printf ("libfdt: %s\n", fdt_strerror(err));
return 1;
}
fdt = newaddr;
/********************************************************************
* Set the value of a node in the fdt.
********************************************************************/
} else if (op == 's') {
char *pathp; /* path */
char *prop; /* property */
struct fdt_property *nodep; /* node struct pointer */
char *newval; /* value from the user (as a string) */
char *vp; /* temporary value pointer */
char *cp; /* temporary char pointer */
int nodeoffset; /* node offset from libfdt */
int len; /* new length of the property */
int oldlen; /* original length of the property */
unsigned long tmp; /* holds converted values */
int ret; /* return value */
/*
* Parameters: Node path, property, value.
*/
if (argc < 5) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
pathp = argv[2];
prop = argv[3];
newval = argv[4];
if (strcmp(pathp, "/") == 0) {
nodeoffset = 0;
} else {
nodeoffset = fdt_path_offset (fdt, pathp);
if (nodeoffset < 0) {
/*
* Not found or something else bad happened.
*/
printf ("libfdt: %s\n", fdt_strerror(nodeoffset));
return 1;
}
}
nodep = fdt_getprop (fdt, nodeoffset, prop, &oldlen);
if (oldlen < 0) {
printf ("libfdt %s\n", fdt_strerror(oldlen));
return 1;
} else if (oldlen == 0) {
/*
* The specified property has no value
*/
printf("%s has no value, cannot set one (yet).\n", prop);
return 1;
} else {
/*
* Convert the new property
*/
vp = data;
if (*newval == '<') {
/*
* Bigger values than bytes.
*/
len = 0;
newval++;
while ((*newval != '>') && (*newval != '\0')) {
cp = newval;
tmp = simple_strtoul(cp, &newval, 16);
if ((newval - cp) <= 2) {
*vp = tmp & 0xFF;
vp += 1;
len += 1;
} else if ((newval - cp) <= 4) {
*(uint16_t *)vp = __cpu_to_be16(tmp);
vp += 2;
len += 2;
} else if ((newval - cp) <= 8) {
*(uint32_t *)vp = __cpu_to_be32(tmp);
vp += 4;
len += 4;
} else {
printf("Sorry, I could not convert \"%s\"\n", cp);
return 1;
}
while (*newval == ' ')
newval++;
}
if (*newval != '>') {
printf("Unexpected character '%c'\n", *newval);
return 1;
}
} else if (*newval == '[') {
/*
* Byte stream. Convert the values.
*/
len = 0;
newval++;
while ((*newval != ']') && (*newval != '\0')) {
tmp = simple_strtoul(newval, &newval, 16);
*vp++ = tmp & 0xFF;
len++;
while (*newval == ' ')
newval++;
}
if (*newval != ']') {
printf("Unexpected character '%c'\n", *newval);
return 1;
}
} else {
/*
* Assume it is a string. Copy it into our data area for
* convenience (including the terminating '\0').
*/
len = strlen(newval) + 1;
strcpy(data, newval);
}
ret = fdt_setprop(fdt, nodeoffset, prop, data, len);
if (ret < 0) {
printf ("libfdt %s\n", fdt_strerror(ret));
return 1;
}
}
/********************************************************************
* Print (recursive) / List (single level)
********************************************************************/
} else if ((op == 'p') || (op == 'l')) {
/*
* Recursively print (a portion of) the fdt.
*/
static int offstack[MAX_LEVEL];
static char tabs[MAX_LEVEL+1] = "\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t";
int depth = MAX_LEVEL; /* how deep to print */
char *pathp; /* path */
char *prop; /* property */
void *nodep; /* property node pointer */
int nodeoffset; /* node offset from libfdt */
int nextoffset; /* next node offset from libfdt */
uint32_t tag; /* tag */
int len; /* length of the property */
int level = 0; /* keep track of nesting level */
/*
* list is an alias for print, but limited to 1 level
*/
if (op == 'l') {
depth = 1;
}
/*
* Get the starting path. The root node is an oddball,
* the offset is zero and has no name.
*/
pathp = argv[2];
if (argc > 3)
prop = argv[3];
else
prop = NULL;
if (strcmp(pathp, "/") == 0) {
nodeoffset = 0;
printf("/");
} else {
nodeoffset = fdt_path_offset (fdt, pathp);
if (nodeoffset < 0) {
/*
* Not found or something else bad happened.
*/
printf ("libfdt %s\n", fdt_strerror(nodeoffset));
return 1;
}
}
/*
* The user passed in a property as well as node path. Print only
* the given property and then return.
*/
if (prop) {
nodep = fdt_getprop (fdt, nodeoffset, prop, &len);
if (len == 0) {
printf("%s %s\n", pathp, prop); /* no property value */
return 0;
} else if (len > 0) {
printf("%s=", prop);
print_data (nodep, len);
printf("\n");
return 0;
} else {
printf ("libfdt %s\n", fdt_strerror(len));
return 1;
}
}
/*
* The user passed in a node path and no property, print the node
* and all subnodes.
*/
offstack[0] = nodeoffset;
while(level >= 0) {
tag = fdt_next_tag(fdt, nodeoffset, &nextoffset, &pathp);
switch(tag) {
case FDT_BEGIN_NODE:
if(level <= depth)
printf("%s%s {\n", &tabs[MAX_LEVEL - level], pathp);
level++;
offstack[level] = nodeoffset;
if (level >= MAX_LEVEL) {
printf("Aaaiii <splat> nested too deep.\n");
return 1;
}
break;
case FDT_END_NODE:
level--;
if(level <= depth)
printf("%s};\n", &tabs[MAX_LEVEL - level]);
if (level == 0) {
level = -1; /* exit the loop */
}
break;
case FDT_PROP:
nodep = fdt_getprop (fdt, offstack[level], pathp, &len);
if (len < 0) {
printf ("libfdt %s\n", fdt_strerror(len));
return 1;
} else if (len == 0) {
/* the property has no value */
if(level <= depth)
printf("%s%s;\n", &tabs[MAX_LEVEL - level], pathp);
} else {
if(level <= depth) {
printf("%s%s=", &tabs[MAX_LEVEL - level], pathp);
print_data (nodep, len);
printf(";\n");
}
}
break;
case FDT_NOP:
break;
case FDT_END:
return 1;
default:
if(level <= depth)
printf("Unknown tag 0x%08X\n", tag);
return 1;
}
nodeoffset = nextoffset;
}
/********************************************************************
* Remove a property/node
********************************************************************/
} else if (op == 'r') {
int nodeoffset; /* node offset from libfdt */
int err;
/*
* Get the path. The root node is an oddball, the offset
* is zero and has no name.
*/
if (strcmp(argv[2], "/") == 0) {
nodeoffset = 0;
} else {
nodeoffset = fdt_path_offset (fdt, argv[2]);
if (nodeoffset < 0) {
/*
* Not found or something else bad happened.
*/
printf ("libfdt %s\n", fdt_strerror(nodeoffset));
return 1;
}
}
/*
* Do the delete. A fourth parameter means delete a property,
* otherwise delete the node.
*/
if (argc > 3) {
err = fdt_delprop(fdt, nodeoffset, argv[3]);
if (err < 0) {
printf("fdt_delprop libfdt: %s\n", fdt_strerror(err));
return err;
}
} else {
err = fdt_del_node(fdt, nodeoffset);
if (err < 0) {
printf("fdt_del_node libfdt: %s\n", fdt_strerror(err));
return err;
}
}
/********************************************************************
* Create a chosen node
********************************************************************/
} else if (op == 'c') {
fdt_chosen(fdt, 0, 0, 1);
/********************************************************************
* Create a u-boot-env node
********************************************************************/
} else if (op == 'e') {
fdt_env(fdt);
/********************************************************************
* Create a bd_t node
********************************************************************/
} else if (op == 'b') {
fdt_bd_t(fdt);
/********************************************************************
* Unrecognized command
********************************************************************/
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
return 0;
}
/********************************************************************/
static int fdt_valid(void)
{
int err;
if (fdt == NULL) {
printf ("The address of the fdt is invalid (NULL).\n");
return 0;
}
err = fdt_check_header(fdt);
if (err == 0)
return 1; /* valid */
if (err < 0) {
printf("libfdt: %s", fdt_strerror(err));
/*
* Be more informative on bad version.
*/
if (err == -FDT_ERR_BADVERSION) {
if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) {
printf (" - too old, fdt $d < %d",
fdt_version(fdt), FDT_FIRST_SUPPORTED_VERSION);
fdt = NULL;
}
if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) {
printf (" - too new, fdt $d > %d",
fdt_version(fdt), FDT_LAST_SUPPORTED_VERSION);
fdt = NULL;
}
return 0;
}
printf("\n");
return 0;
}
return 1;
}
/********************************************************************/
/*
* OF flat tree handling
* Written by: Pantelis Antoniou <pantelis.antoniou@gmail.com>
* Updated by: Matthew McClintock <msm@freescale.com>
* Converted to libfdt by: Gerald Van Baren <vanbaren@cideas.com>
*/
static int is_printable_string(const void *data, int len)
{
const char *s = data;
/* zero length is not */
if (len == 0)
return 0;
/* must terminate with zero */
if (s[len - 1] != '\0')
return 0;
/* printable or a null byte (concatenated strings) */
while (((*s == '\0') || isprint(*s)) && (len > 0)) {
/*
* If we see a null, there are three possibilities:
* 1) If len == 1, it is the end of the string, printable
* 2) Next character also a null, not printable.
* 3) Next character not a null, continue to check.
*/
if (s[0] == '\0') {
if (len == 1)
return 1;
if (s[1] == '\0')
return 0;
}
s++;
len--;
}
/* Not the null termination, or not done yet: not printable */
if (*s != '\0' || (len != 0))
return 0;
return 1;
}
static void print_data(const void *data, int len)
{
int j;
const u8 *s;
/* no data, don't print */
if (len == 0)
return;
/*
* It is a string, but it may have multiple strings (embedded '\0's).
*/
if (is_printable_string(data, len)) {
puts("\"");
j = 0;
while (j < len) {
if (j > 0)
puts("\", \"");
puts(data);
j += strlen(data) + 1;
data += strlen(data) + 1;
}
puts("\"");
return;
}
switch (len) {
case 1: /* byte */
printf("<%02x>", (*(u8 *) data) & 0xff);
break;
case 2: /* half-word */
printf("<%04x>", be16_to_cpu(*(u16 *) data) & 0xffff);
break;
case 4: /* word */
printf("<%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
break;
case 8: /* double-word */
#if __WORDSIZE == 64
printf("<%016llx>", be64_to_cpu(*(uint64_t *) data));
#else
printf("<%08x ", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
data += 4;
printf("%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
#endif
break;
default: /* anything else... hexdump */
printf("[");
for (j = 0, s = data; j < len; j++)
printf("%02x%s", s[j], j < len - 1 ? " " : "");
printf("]");
break;
}
}
/********************************************************************/
U_BOOT_CMD(
fdt, 5, 0, do_fdt,
"fdt - flattened device tree utility commands\n",
"addr <addr> [<length>] - Set the fdt location to <addr>\n"
"fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr>\n"
"fdt print <path> [<prop>] - Recursive print starting at <path>\n"
"fdt list <path> [<prop>] - Print one level starting at <path>\n"
"fdt set <path> <prop> [<val>] - Set <property> [to <val>]\n"
"fdt mknode <path> <node> - Create a new node after <path>\n"
"fdt rm <path> [<prop>] - Delete the node or <property>\n"
"fdt chosen - Add/update the \"/chosen\" branch in the tree\n"
#ifdef CONFIG_OF_HAS_UBOOT_ENV
"fdt env - Add/replace the \"/u-boot-env\" branch in the tree\n"
#endif
#ifdef CONFIG_OF_HAS_BD_T
"fdt bd_t - Add/replace the \"/bd_t\" branch in the tree\n"
#endif
"Hints:\n"
" * Set a larger length with the fdt addr command to add to the blob.\n"
" * If the property you are setting/printing has a '#' character,\n"
" you MUST escape it with a \\ character or quote it with \" or\n"
" it will be ignored as a comment.\n"
" * If the value has spaces in it, you MUST escape the spaces with\n"
" \\ characters or quote it with \"\"\n"
"Examples: fdt print / # print the whole tree\n"
" fdt print /cpus \"#address-cells\"\n"
" fdt set /cpus \"#address-cells\" \"[00 00 00 01]\"\n"
);
#endif /* CONFIG_OF_LIBFDT */

3
common/cmd_i2c.c
View File

@ -969,7 +969,7 @@ U_BOOT_CMD(
"i2c sdram chip - print SDRAM configuration information\n"
#endif /* CFG_CMD_SDRAM */
);
#else /* CONFIG_I2C_CMD_TREE */
#endif /* CONFIG_I2C_CMD_TREE */
U_BOOT_CMD(
imd, 4, 1, do_i2c_md, \
"imd - i2c memory display\n", \
@ -1024,6 +1024,5 @@ U_BOOT_CMD(
" (valid chip values 50..57)\n"
);
#endif
#endif /* CONFIG_I2C_CMD_TREE */
#endif /* CFG_CMD_I2C */

21
common/cmd_ide.c
View File

@ -423,7 +423,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
part = simple_strtoul(++ep, NULL, 16);
}
if (get_partition_info (ide_dev_desc, part, &info)) {
if (get_partition_info (&ide_dev_desc[dev], part, &info)) {
SHOW_BOOT_PROGRESS (-1);
return 1;
}
@ -513,9 +513,11 @@ void ide_init (void)
#endif
unsigned char c;
int i, bus;
#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3)
unsigned int ata_reset_time;
#endif
#ifdef CONFIG_AMIGAONEG3SE
unsigned int max_bus_scan;
unsigned int ata_reset_time;
char *s;
#endif
#ifdef CONFIG_IDE_8xx_PCCARD
@ -617,10 +619,9 @@ void ide_init (void)
udelay (100000); /* 100 ms */
ide_outb (dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
udelay (100000); /* 100 ms */
#ifdef CONFIG_AMIGAONEG3SE
ata_reset_time = ATA_RESET_TIME;
s = getenv("ide_reset_timeout");
if (s) ata_reset_time = 2*simple_strtol(s, NULL, 10);
#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3)
if ((s = getenv("ide_reset_timeout")) != NULL)
ata_reset_time = simple_strtol(s, NULL, 10);
#endif
i = 0;
do {
@ -628,7 +629,7 @@ void ide_init (void)
c = ide_inb (dev, ATA_STATUS);
i++;
#ifdef CONFIG_AMIGAONEG3SE
#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3)
if (i > (ata_reset_time * 100)) {
#else
if (i > (ATA_RESET_TIME * 100)) {
@ -1343,7 +1344,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
++n;
++blknr;
buffer += ATA_SECTORWORDS;
buffer += ATA_BLOCKSIZE;
}
IDE_READ_E:
ide_led (DEVICE_LED(device), 0); /* LED off */
@ -1427,7 +1428,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
c = ide_inb (device, ATA_STATUS); /* clear IRQ */
++n;
++blknr;
buffer += ATA_SECTORWORDS;
buffer += ATA_BLOCKSIZE;
}
WR_OUT:
ide_led (DEVICE_LED(device), 0); /* LED off */
@ -2051,7 +2052,7 @@ ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
n+=cnt;
blkcnt-=cnt;
blknr+=cnt;
buffer+=cnt*(ATAPI_READ_BLOCK_SIZE/4); /* ulong blocksize in ulong */
buffer+=(cnt*ATAPI_READ_BLOCK_SIZE);
} while (blkcnt > 0);
return (n);
}

2
common/cmd_scsi.c
View File

@ -248,7 +248,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
part = simple_strtoul(++ep, NULL, 16);
}
if (get_partition_info (scsi_dev_desc, part, &info)) {
if (get_partition_info (&scsi_dev_desc[dev], part, &info)) {
printf("error reading partinfo\n");
return 1;
}

347
common/fdt_support.c Normal file
View File

@ -0,0 +1,347 @@
/*
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/ctype.h>
#include <linux/types.h>
#ifdef CONFIG_OF_LIBFDT
#include <asm/global_data.h>
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
/*
* Global data (for the gd->bd)
*/
DECLARE_GLOBAL_DATA_PTR;
/********************************************************************/
int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
{
bd_t *bd = gd->bd;
int nodeoffset;
int err;
u32 tmp; /* used to set 32 bit integer properties */
char *str; /* used to set string properties */
ulong clock;
err = fdt_check_header(fdt);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
if (initrd_start && initrd_end) {
struct fdt_reserve_entry re;
int used;
int total;
int j;
err = fdt_num_reservemap(fdt, &used, &total);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
if (used >= total) {
printf("fdt_chosen: no room in the reserved map (%d of %d)\n",
used, total);
return -1;
}
/*
* Look for an existing entry and update it. If we don't find
* the entry, we will j be the next available slot.
*/
for (j = 0; j < used; j++) {
err = fdt_get_reservemap(fdt, j, &re);
if (re.address == initrd_start) {
break;
}
}
err = fdt_replace_reservemap_entry(fdt, j,
initrd_start, initrd_end - initrd_start + 1);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
}
/*
* Find the "chosen" node.
*/
nodeoffset = fdt_path_offset (fdt, "/chosen");
/*
* If we have a "chosen" node already the "force the writing"
* is not set, our job is done.
*/
if ((nodeoffset >= 0) && !force)
return 0;
/*
* No "chosen" node in the blob: create it.
*/
if (nodeoffset < 0) {
/*
* Create a new node "/chosen" (offset 0 is root level)
*/
nodeoffset = fdt_add_subnode(fdt, 0, "chosen");
if (nodeoffset < 0) {
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
return nodeoffset;
}
}
/*
* Update pre-existing properties, create them if non-existant.
*/
str = getenv("bootargs");
if (str != NULL) {
err = fdt_setprop(fdt, nodeoffset, "bootargs", str, strlen(str)+1);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
if (initrd_start && initrd_end) {
tmp = __cpu_to_be32(initrd_start);
err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp));
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
tmp = __cpu_to_be32(initrd_end);
err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp));
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
#ifdef OF_STDOUT_PATH
err = fdt_setprop(fdt, nodeoffset, "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
#endif
nodeoffset = fdt_path_offset (fdt, "/cpus");
if (nodeoffset >= 0) {
clock = cpu_to_be32(bd->bi_intfreq);
err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
#ifdef OF_TBCLK
nodeoffset = fdt_path_offset (fdt, "/cpus/" OF_CPU "/timebase-frequency");
if (nodeoffset >= 0) {
clock = cpu_to_be32(OF_TBCLK);
err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
#endif
return err;
}
/********************************************************************/
#ifdef CONFIG_OF_HAS_UBOOT_ENV
/* Function that returns a character from the environment */
extern uchar(*env_get_char) (int);
int fdt_env(void *fdt)
{
int nodeoffset;
int err;
int k, nxt;
int i;
static char tmpenv[256];
err = fdt_check_header(fdt);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
/*
* See if we already have a "u-boot-env" node, delete it if so.
* Then create a new empty node.
*/
nodeoffset = fdt_path_offset (fdt, "/u-boot-env");
if (nodeoffset >= 0) {
err = fdt_del_node(fdt, nodeoffset);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
}
/*
* Create a new node "/u-boot-env" (offset 0 is root level)
*/
nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env");
if (nodeoffset < 0) {
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
return nodeoffset;
}
for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
char *s, *lval, *rval;
/*
* Find the end of the name=definition
*/
for (nxt = i; env_get_char(nxt) != '\0'; ++nxt)
;
s = tmpenv;
for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k)
*s++ = env_get_char(k);
*s++ = '\0';
lval = tmpenv;
/*
* Find the first '=': it separates the name from the value
*/
s = strchr(tmpenv, '=');
if (s != NULL) {
*s++ = '\0';
rval = s;
} else
continue;
err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
}
return 0;
}
#endif /* ifdef CONFIG_OF_HAS_UBOOT_ENV */
/********************************************************************/
#ifdef CONFIG_OF_HAS_BD_T
#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) }
static const struct {
const char *name;
int offset;
} bd_map[] = {
BDM(memstart),
BDM(memsize),
BDM(flashstart),
BDM(flashsize),
BDM(flashoffset),
BDM(sramstart),
BDM(sramsize),
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
|| defined(CONFIG_E500)
BDM(immr_base),
#endif
#if defined(CONFIG_MPC5xxx)
BDM(mbar_base),
#endif
#if defined(CONFIG_MPC83XX)
BDM(immrbar),
#endif
#if defined(CONFIG_MPC8220)
BDM(mbar_base),
BDM(inpfreq),
BDM(pcifreq),
BDM(pevfreq),
BDM(flbfreq),
BDM(vcofreq),
#endif
BDM(bootflags),
BDM(ip_addr),
BDM(intfreq),
BDM(busfreq),
#ifdef CONFIG_CPM2
BDM(cpmfreq),
BDM(brgfreq),
BDM(sccfreq),
BDM(vco),
#endif
#if defined(CONFIG_MPC5xxx)
BDM(ipbfreq),
BDM(pcifreq),
#endif
BDM(baudrate),
};
int fdt_bd_t(void *fdt)
{
bd_t *bd = gd->bd;
int nodeoffset;
int err;
u32 tmp; /* used to set 32 bit integer properties */
int i;
err = fdt_check_header(fdt);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
/*
* See if we already have a "bd_t" node, delete it if so.
* Then create a new empty node.
*/
nodeoffset = fdt_path_offset (fdt, "/bd_t");
if (nodeoffset >= 0) {
err = fdt_del_node(fdt, nodeoffset);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
}
/*
* Create a new node "/bd_t" (offset 0 is root level)
*/
nodeoffset = fdt_add_subnode(fdt, 0, "bd_t");
if (nodeoffset < 0) {
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
return nodeoffset;
}
/*
* Use the string/pointer structure to create the entries...
*/
for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) {
tmp = cpu_to_be32(getenv("bootargs"));
err = fdt_setprop(fdt, nodeoffset, bd_map[i].name, &tmp, sizeof(tmp));
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
/*
* Add a couple of oddball entries...
*/
err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
return 0;
}
#endif /* ifdef CONFIG_OF_HAS_BD_T */
#endif /* CONFIG_OF_LIBFDT */

4
common/serial.c
View File

@ -41,7 +41,7 @@ struct serial_device *default_serial_console (void)
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
@ -91,7 +91,7 @@ void serial_initialize (void)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
serial_register(&serial0_device);
serial_register(&serial1_device);
#endif

2
config.mk
View File

@ -70,7 +70,7 @@ endif
endif
ifeq ($(ARCH),blackfin)
PLATFORM_CPPFLAGS+= -D__BLACKFIN__ -mno-underscore
PLATFORM_CPPFLAGS+= -D__BLACKFIN__
endif
ifdef ARCH

46
cpu/74xx_7xx/cpu.c
View File

@ -44,6 +44,10 @@
#include <74xx_7xx.h>
#include <asm/cache.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#ifdef CONFIG_AMIGAONEG3SE
#include "../board/MAI/AmigaOneG3SE/via686.h"
#include "../board/MAI/AmigaOneG3SE/memio.h"
@ -101,6 +105,10 @@ get_cpu_type(void)
type = CPU_7457;
break;
case 0x8003:
type = CPU_7447A;
break;
case 0x8004:
type = CPU_7448;
break;
@ -156,6 +164,10 @@ int checkcpu (void)
str = "MPC7410";
break;
case CPU_7447A:
str = "MPC7447A";
break;
case CPU_7448:
str = "MPC7448";
break;
@ -264,20 +276,19 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* For the 7400 the TB clock runs at 1/4 the cpu bus speed.
*/
#ifdef CONFIG_AMIGAONEG3SE
#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK)
unsigned long get_tbclk(void)
{
return (gd->bus_clk / 4);
}
#else /* ! CONFIG_AMIGAONEG3SE */
#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/
unsigned long get_tbclk (void)
{
return CFG_BUS_HZ / 4;
}
#endif /* CONFIG_AMIGAONEG3SE */
#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
void
@ -289,3 +300,30 @@ watchdog_reset(void)
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_OF_FLAT_TREE
void
ft_cpu_setup (void *blob, bd_t *bd)
{
u32 *p;
ulong clock;
int len;
clock = bd->bi_busfreq;
p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32 (clock);
#if defined(CONFIG_TSI108_ETH)
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len);
memcpy (p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_HAS_ETH1)
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len);
memcpy (p, bd->bi_enet1addr, 6);
#endif
}
#endif
/* ------------------------------------------------------------------------- */

1
cpu/74xx_7xx/cpu_init.c
View File

@ -43,6 +43,7 @@ cpu_init_f (void)
case CPU_7450:
case CPU_7455:
case CPU_7457:
case CPU_7447A:
case CPU_7448:
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);

56
cpu/74xx_7xx/speed.c
View File

@ -31,6 +31,8 @@
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long get_board_bus_clk (void);
static const int hid1_multipliers_x_10[] = {
25, /* 0000 - 2.5x */
75, /* 0001 - 7.5x */
@ -50,6 +52,42 @@ static const int hid1_multipliers_x_10[] = {
0 /* 1111 - off */
};
/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */
static const int hid1_74xx_multipliers_x_10[] = {
115, /* 00000 - 11.5x */
170, /* 00001 - 17x */
75, /* 00010 - 7.5x */
150, /* 00011 - 15x */
70, /* 00100 - 7x */
180, /* 00101 - 18x */
10, /* 00110 - bypass */
200, /* 00111 - 20x */
20, /* 01000 - 2x */
210, /* 01001 - 21x */
65, /* 01010 - 6.5x */
130, /* 01011 - 13x */
85, /* 01100 - 8.5x */
240, /* 01101 - 24x */
95, /* 01110 - 9.5x */
90, /* 01111 - 9x */
30, /* 10000 - 3x */
105, /* 10001 - 10.5x */
55, /* 10010 - 5.5x */
110, /* 10011 - 11x */
40, /* 10100 - 4x */
100, /* 10101 - 10x */
50, /* 10110 - 5x */
120, /* 10111 - 12x */
80, /* 11000 - 8x */
140, /* 11001 - 14x */
60, /* 11010 - 6x */
160, /* 11011 - 16x */
135, /* 11100 - 13.5x */
280, /* 11101 - 28x */
0, /* 11110 - off */
125 /* 11111 - 12.5x */
};
static const int hid1_fx_multipliers_x_10[] = {
00, /* 0000 - off */
00, /* 0001 - off */
@ -89,22 +127,30 @@ int get_clocks (void)
{
ulong clock = 0;
#ifdef CFG_BUS_CLK
gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
#else
gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
#endif
/* calculate the clock frequency based upon the CPU type */
switch (get_cpu_type()) {
case CPU_7447A:
case CPU_7448:
case CPU_7455:
case CPU_7457:
/*
* It is assumed that the PLL_EXT line is zero.
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
clock = (gd->bus_clk / 10) *
hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
break;
case CPU_750GX:
case CPU_750FX:
clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
clock = gd->bus_clk *
hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
break;
case CPU_7450:
@ -121,7 +167,8 @@ int get_clocks (void)
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28];
clock = (gd->bus_clk / 10) *
hid1_multipliers_x_10[get_hid1 () >> 28];
break;
case CPU_UNKNOWN:
@ -131,7 +178,6 @@ int get_clocks (void)
}
gd->cpu_clk = clock;
gd->bus_clk = CFG_BUS_CLK;
return (0);
}

2
cpu/at32ap/Makefile
View File

@ -30,7 +30,7 @@ LIB := $(obj)lib$(CPU).a
START := start.o
SOBJS := entry.o
COBJS := cpu.o hsdramc.o exception.o cache.o
COBJS += interrupts.o device.o pm.o pio.o
COBJS += interrupts.o pio.o atmel_mci.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))

2
cpu/at32ap/at32ap7000/Makefile
View File

@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(SOC).a
COBJS := hebi.o devices.o
COBJS := gpio.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

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