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powerpc/p2020ds: Integrated with P2020DS DDR change and enabled hwconfig 

Enabled SPD
Enabled DDR2
Enabled hwconfig

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
york 2010-07-02 22:25:58 +00:00 committed by Kumar Gala
parent 5fb8a8a731
commit 394c46caf9
4 changed files with 39 additions and 31 deletions
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1
Makefile
View File

@ -1788,6 +1788,7 @@ P2010RDB_config \
P2010RDB_NAND_config \
P2010RDB_SDCARD_config \
P2010RDB_SPIFLASH_config \
P2020DS_DDR2_config \
P2020RDB_config \
P2020RDB_NAND_config \
P2020RDB_SDCARD_config \

56
board/freescale/p2020ds/ddr.c
View File

@ -12,7 +12,7 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
{
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
}
@ -22,7 +22,7 @@ unsigned int fsl_ddr_get_mem_data_rate(void)
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num)
{
unsigned int i;
@ -51,27 +51,26 @@ typedef struct {
* cpo 2-0x1E (30)
*/
/* XXX: these values need to be checked for all interleaving modes. */
/* XXX: No reliable dual-rank 800 MHz setting has been found. It may
* seem reliable, but errors will appear when memory intensive
* program is run. */
/* XXX: Single rank at 800 MHz is OK. */
const board_specific_parameters_t board_specific_parameters[][20] = {
{
/* memory controller 0 */
/* lo| hi| num| clk| cpo|wrdata|2T */
/* mhz| mhz|ranks|adjst| | delay| */
{ 0, 333, 2, 6, 7, 3, 0},
{334, 400, 2, 6, 9, 3, 0},
{401, 549, 2, 6, 11, 3, 0},
{550, 680, 2, 1, 10, 5, 0},
{681, 850, 2, 1, 12, 5, 1},
{ 0, 333, 1, 6, 7, 3, 0},
{334, 400, 1, 6, 9, 3, 0},
{401, 549, 1, 6, 11, 3, 0},
{550, 680, 1, 1, 10, 5, 0},
{681, 850, 1, 1, 12, 5, 0}
#ifdef CONFIG_FSL_DDR2
{ 0, 333, 2, 4, 0x1f, 2, 0},
{334, 400, 2, 4, 0x1f, 2, 0},
{401, 549, 2, 4, 0x1f, 2, 0},
{550, 680, 2, 4, 0x1f, 3, 0},
{681, 850, 2, 4, 0x1f, 4, 0},
{ 0, 333, 1, 4, 0x1f, 2, 0},
{334, 400, 1, 4, 0x1f, 2, 0},
{401, 549, 1, 4, 0x1f, 2, 0},
{550, 680, 1, 4, 0x1f, 3, 0},
{681, 850, 1, 4, 0x1f, 4, 0}
#else
{ 0, 850, 2, 4, 0x1f, 4, 0},
{ 0, 850, 1, 4, 0x1f, 4, 0}
#endif
},
};
@ -92,18 +91,8 @@ void fsl_ddr_board_options(memctl_options_t *popts,
* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
*/
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i&1) { /* odd CS */
popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 0;
} else { /* even CS */
if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 4;
} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
popts->cs_local_opts[i].odt_rd_cfg = 3;
popts->cs_local_opts[i].odt_wr_cfg = 3;
}
}
popts->cs_local_opts[i].odt_wr_cfg = 1;
}
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
@ -127,4 +116,13 @@ void fsl_ddr_board_options(memctl_options_t *popts,
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
popts->wrlvl_en = 1;
/* Write leveling override */
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xa;
popts->wrlvl_start = 0x7;
/* Rtt and Rtt_WR override */
popts->rtt_override = 1;
popts->rtt_override_value = DDR3_RTT_120_OHM;
popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
}

7
board/freescale/p2020ds/p2020ds.c
View File

@ -69,13 +69,16 @@ int checkboard(void)
return 0;
}
const char *board_hwconfig = "foo:bar=baz";
const char *cpu_hwconfig = "foo:bar=baz";
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
puts("Initializing....");
#ifdef CONFIG_SPD_EEPROM
#ifdef CONFIG_DDR_SPD
dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
@ -94,7 +97,7 @@ phys_size_t initdram(int board_type)
return dram_size;
}
#if !defined(CONFIG_SPD_EEPROM)
#if !defined(CONFIG_DDR_SPD)
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/

6
include/configs/P2020DS.h
View File

@ -92,7 +92,11 @@
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#ifdef CONFIG_MK_DDR2
#define CONFIG_FSL_DDR2
#else
#define CONFIG_FSL_DDR3 1
#endif
#undef CONFIG_FSL_DDR_INTERACTIVE
/* ECC will be enabled based on perf_mode environment variable */
@ -109,6 +113,7 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
/* I2C addresses of SPD EEPROMs */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
@ -228,6 +233,7 @@
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#ifdef CONFIG_FSL_NGPIXIS