Added support for the mgsuvd board from keymile.
Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
Wolfgang Denk
parent
bf05293973
commit
381e4e6397
1
MAKEALL
1
MAKEALL
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@ -107,6 +107,7 @@ LIST_8xx=" \
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lwmon \
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MBX \
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MBX860T \
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mgsuvd \
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MHPC \
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MPC86xADS \
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MPC885ADS \
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3
Makefile
3
Makefile
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@ -853,6 +853,9 @@ MBX_config \
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MBX860T_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
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mgsuvd_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd
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MHPC_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2007
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# Heiko Schocher, DENX Software Engineering, hs@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,28 @@
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#
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# (C) Copyright 2007
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# Heiko Schocher, DENX Software Engineering, hs@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# mgsvud boards
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#
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TEXT_BASE = 0xf0000000
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@ -0,0 +1,216 @@
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/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <mpc8xx.h>
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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const uint sdram_table[] =
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{
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0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
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0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x08 Burst Read */
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0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
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0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
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/* 0x10 Load mode register */
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0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x18 Single Write */
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0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
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0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
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/* 0x20 Burst Write */
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0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
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0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
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0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x30 Precharge all and Refresh */
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0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
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0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x3C Exception */
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0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
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};
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int checkboard (void)
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{
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puts ("Board: Keymile mgsuvd\n");
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return (0);
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}
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size;
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upmconfig (UPMB, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR;
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/*
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* The following value is used as an address (i.e. opcode) for
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* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
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* the port size is 32bit the SDRAM does NOT "see" the lower two
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* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
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* MICRON SDRAMs:
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* -> 0 00 010 0 010
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* | | | | +- Burst Length = 4
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* | | | +----- Burst Type = Sequential
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* | | +------- CAS Latency = 2
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* | +----------- Operating Mode = Standard
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* +-------------- Write Burst Mode = Programmed Burst Length
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*/
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memctl->memc_mar = CFG_MAR;
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/*
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* Map controller banks 1 to the SDRAM banks 1 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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memctl->memc_mbmr = CFG_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mbmr |= MBMR_PTBE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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*/
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size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
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return (size);
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}
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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/*
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* update "memory" property in the blob
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*/
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void ft_blob_update(void *blob, bd_t *bd)
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{
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int ret, nodeoffset = 0;
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ulong brg_data[1] = {0};
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ulong memory_data[2] = {0};
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ulong flash_data[4] = {0};
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memory_data[0] = cpu_to_be32(bd->bi_memstart);
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memory_data[1] = cpu_to_be32(bd->bi_memsize);
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nodeoffset = fdt_path_offset (blob, "/memory");
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if (nodeoffset >= 0) {
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ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
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sizeof(memory_data));
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if (ret < 0)
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printf("ft_blob_update): cannot set /memory/reg "
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"property err:%s\n", fdt_strerror(ret));
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}
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else {
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/* memory node is required in dts */
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printf("ft_blob_update(): cannot find /memory node "
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"err:%s\n", fdt_strerror(nodeoffset));
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}
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flash_data[2] = cpu_to_be32(bd->bi_flashstart);
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flash_data[3] = cpu_to_be32(bd->bi_flashsize);
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nodeoffset = fdt_path_offset (blob, "/localbus");
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if (nodeoffset >= 0) {
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ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
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sizeof(flash_data));
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if (ret < 0)
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printf("ft_blob_update): cannot set /localbus/ranges "
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"property err:%s\n", fdt_strerror(ret));
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}
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else {
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/* memory node is required in dts */
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printf("ft_blob_update(): cannot find /localbus node "
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"err:%s\n", fdt_strerror(nodeoffset));
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}
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/* BRG */
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brg_data[0] = cpu_to_be32(bd->bi_busfreq);
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nodeoffset = fdt_path_offset (blob, "/soc866/cpm");
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if (nodeoffset >= 0) {
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ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data,
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sizeof(brg_data));
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if (ret < 0)
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printf("ft_blob_update): cannot set /soc866/cpm/brg-frequency "
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"property err:%s\n", fdt_strerror(ret));
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}
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else {
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/* memory node is required in dts */
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printf("ft_blob_update(): cannot find /localbus node "
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"err:%s\n", fdt_strerror(nodeoffset));
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}
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/* MAC Adresse */
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nodeoffset = fdt_path_offset (blob, "/soc866/cpm/scc");
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if (nodeoffset >= 0) {
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ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
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sizeof(uchar) * 6);
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if (ret < 0)
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printf("ft_blob_update): cannot set /soc866/cpm/scc/mac-address "
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"property err:%s\n", fdt_strerror(ret));
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}
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else {
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/* memory node is required in dts */
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printf("ft_blob_update(): cannot find /localbus node "
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"err:%s\n", fdt_strerror(nodeoffset));
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}
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup( blob, bd);
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ft_blob_update(blob, bd);
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}
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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@ -0,0 +1,144 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
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*/
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OUTPUT_ARCH(powerpc)
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
|
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SECTIONS
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{
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||||
/* Read-only sections, merged into text segment: */
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||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mpc8xx/start.o (.text)
|
||||
cpu/mpc8xx/traps.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_ppc/ppcstring.o (.text)
|
||||
lib_generic/vsprintf.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
lib_ppc/cache.o (.text)
|
||||
lib_ppc/time.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.ppcenv)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -39,6 +39,12 @@
|
|||
#include <mpc8xx.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#include <fdt_support.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static char *cpu_warning = "\n " \
|
||||
|
|
@ -632,3 +638,13 @@ void reset_8xx_watchdog (volatile immap_t * immr)
|
|||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
void ft_cpu_setup (void *blob, bd_t *bd)
|
||||
{
|
||||
char * cpu_path = "/cpus/" OF_CPU;
|
||||
|
||||
do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
|
||||
do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
|
||||
do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
|
||||
}
|
||||
#endif /* CONFIG_OF_LIBFDT */
|
||||
|
|
|
|||
|
|
@ -1120,6 +1120,32 @@ typedef struct scc_enet {
|
|||
#define SICR_ENET_CLKRT ((uint)0x0000003d)
|
||||
#endif /* CONFIG_MBX */
|
||||
|
||||
/*** MGSUVD *********************************************************/
|
||||
|
||||
/* The MGSUVD Service Module uses SCC3 for Ethernet */
|
||||
|
||||
#ifdef CONFIG_MGSUVD
|
||||
#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
|
||||
#define CPM_CR_ENET CPM_CR_CH_SCC3
|
||||
#define SCC_ENET 2
|
||||
#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
|
||||
#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
|
||||
#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
|
||||
#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
|
||||
|
||||
#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
|
||||
|
||||
#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
|
||||
#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
|
||||
|
||||
/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
|
||||
* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
|
||||
*/
|
||||
#define SICR_ENET_MASK ((uint)0x00FF0000)
|
||||
#define SICR_ENET_CLKRT ((uint)0x00250000)
|
||||
#endif /* CONFIG_MGSUVD */
|
||||
|
||||
|
||||
/*** MHPC ********************************************************/
|
||||
|
||||
#if defined(CONFIG_MHPC)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,325 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
|
||||
#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
|
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ 66000000
|
||||
|
||||
#define CFG_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
|
||||
#define CFG_SMC_DPMEM_OFFSET 0x1fc0
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
|
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"addcon=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr} ${bootfile}; " \
|
||||
"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\
|
||||
"bootm ${kernel_addr} - ${fdt_addr}\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"bootfile=/tftpboot/mgsuvd/uImage\0" \
|
||||
"fdt_addr=400000\0" \
|
||||
"kernel_addr=200000\0" \
|
||||
"fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"update=protect off f0000000 +${filesize};" \
|
||||
"erase f0000000 +${filesize};" \
|
||||
"cp.b 200000 f0000000 ${filesize};" \
|
||||
"protect on f0000000 +${filesize}\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* but print image timestmps */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFFF00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xf0000000
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_FLASH_SIZE 32
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
|
||||
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#define CFG_SYPCR 0xffffff89
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_SIUMCR 0x00610480
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK 0x01800000
|
||||
#define CFG_SCCR 0x01800000
|
||||
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing: Default value of OR0 after reset
|
||||
*/
|
||||
#define CFG_OR0_PRELIM 0xfe000954
|
||||
#define CFG_BR0_PRELIM 0xf0000401
|
||||
|
||||
/*
|
||||
* BR1 and OR1 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00
|
||||
|
||||
#define CFG_OR1_PRELIM 0xfc000800
|
||||
#define CFG_BR1_PRELIM (0x000000C0 | 0x01)
|
||||
|
||||
#define CFG_MPTPR 0x0200
|
||||
/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
|
||||
1 Write loop Cycle (not used), 1 Timer Loop Cycle */
|
||||
#define CFG_MBMR 0x10964111
|
||||
#define CFG_MAR 0x00000088
|
||||
|
||||
/*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
*/
|
||||
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
||||
/* HS HS noch zu setzen */
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CONFIG_SCC3_ENET
|
||||
#define CONFIG_ETHPRIME "SCC ETHERNET"
|
||||
#define CONFIG_HAS_ETH0
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#define OF_CPU "PowerPC,866@0"
|
||||
#define OF_SOC "soc@f0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue