sciphone_g2: Support for saving BBT in NAND
This implementation allows U-Boot to save BBT table in NAND. Without this option BBT table is created everytime when first nand command is executed (except "nand dump"). Full scanning of NAND takes long time and unnecessarily delays start of platform. NOTE! This option is disabled by defaut as at startup it deletes last two blocks of NAND. Most of people run code from RAM and don't have NAND memory dumped yet. If you don't like to wait on first nand command, you should define MT62XX_NAND_BBT_IN_NAND. Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
This commit is contained in:
Marcin Mielczarczyk
parent
0e81308435
commit
37d226f1e9
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@ -92,6 +92,38 @@
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*/
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#define ECC_SPARE_BYTE_POS 8
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/*
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* Below tables describe layout of BBT (Bad Block Table) in OOB area.
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* U-Boot's default layout overlaps with MTK's HW ECC position, that's
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* why redefinition is placed here.
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*/
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#ifdef MT62XX_NAND_BBT_IN_NAND
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static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
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static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
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static struct nand_bbt_descr bbt_main_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
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| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
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.offs = 0, /* offset changed as default one overlaps with HW ECC */
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.len = 4,
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.veroffs = 14, /* offset changed as default one overlaps with HW ECC */
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.maxblocks = 4,
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.pattern = bbt_pattern
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};
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static struct nand_bbt_descr bbt_mirror_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
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| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
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.offs = 0, /* offset changed as default one overlaps with HW ECC */
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.len = 4,
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.veroffs = 14, /* offset changed as default one overlaps with HW ECC */
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.maxblocks = 4,
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.pattern = mirror_pattern
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};
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#endif
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/*
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* Macro which counts zeroes until first set bit.
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* This is used to avoid dividing, so no additional library is needed.
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@ -245,27 +277,27 @@ static uint8_t mt62xx_nand_read_byte(struct mtd_info *mtd)
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return byte;
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}
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static void mt62xx_nand_write_ecc(struct mtd_info *mtd, int len)
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static void mt62xx_nand_write_buf_ecc(struct mtd_info *mtd, const uint8_t *buffer)
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{
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int i, ecc_nr, ecc_blocks;
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struct nand_chip *chip = mtd->priv;
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uint8_t ecc[8];
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uint8_t *buf = (uint8_t *)buffer;
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/*
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* After this write ECC calculations will
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* be available in NFI_PAR_P and NFI_PAR_C registers.
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*/
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writel(*((uint32_t *)buf), chip->IO_ADDR_W);
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/*
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* Two ECC blocks are combined on MT62xx platform,
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* that's why writesize is multiplied by 2.
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* that's why there is division by 2.
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*/
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ecc_blocks = (mtd->writesize * 2) >> COUNT_ZEROES(chip->ecc.size);
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ecc_blocks = (mtd->writesize >> COUNT_ZEROES(chip->ecc.size))/2;
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buf += ECC_SPARE_BYTE_POS;
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for (ecc_nr = 0; ecc_nr < ecc_blocks; ++ecc_nr) {
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int ecc_p, ecc_c, pos = 0;
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/*
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* After first write in this loop, ECC calculations will
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* be available in NFI_PAR_P and NFI_PAR_C registers.
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*/
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for (i = 0; i < ECC_SPARE_BYTE_POS/4; ++i)
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writel(~0, chip->IO_ADDR_W);
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int ecc_p, ecc_c;
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/*
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* Read calculated ECC bytes and write them
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@ -274,18 +306,11 @@ static void mt62xx_nand_write_ecc(struct mtd_info *mtd, int len)
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for (i = 0; i < 2; ++i) {
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ecc_p = readw((uint32_t *)MTK_NFI_PAR_0P + ecc_nr*2 + i*2);
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ecc_c = readw((uint32_t *)MTK_NFI_PAR_0C + ecc_nr*2 + i*2);
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ecc[pos++] = ecc_p >> 4;
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ecc[pos++] = ((ecc_p & 0x0F) << 4) | (ecc_c >> 8);
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ecc[pos++] = ecc_c & 0xFF;
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*(buf++) = ecc_p >> 4;
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*(buf++) = ((ecc_p & 0x0F) << 4) | (ecc_c >> 8);
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*(buf++) = ecc_c & 0xFF;
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}
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/* Fill rest of buffer with 0xFF */
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while (pos < sizeof(ecc))
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ecc[pos++] = 0xFF;
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/* Write calculated ECC bytes */
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for (i = 0; i < sizeof(ecc)/4; ++i)
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writel(((uint32_t *)ecc)[i], chip->IO_ADDR_W);
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buf += 16;
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}
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}
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@ -294,7 +319,7 @@ static void mt62xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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{
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uint32_t *buf_32 = (uint32_t *)buf;
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struct nand_chip *chip = mtd->priv;
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int i;
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int i = 0;
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/* Writing in spare area? */
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if (readw(MTK_NFI_ADDRCNTR) >= mtd->writesize) {
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@ -303,14 +328,14 @@ static void mt62xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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* additional read/write cycle, ECC calculations
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* are handled here.
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*/
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mt62xx_nand_write_ecc(mtd, len);
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} else {
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if (len % 4)
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nand_print("Length parameter is not aligned\n");
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mt62xx_nand_write_buf_ecc(mtd, buf);
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for (i = 0; i < len/4; ++i)
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writel(buf_32[i], chip->IO_ADDR_W);
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/* Increment index as above function already written 32 bytes */
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i++;
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}
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for (; i < len/4; ++i)
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writel(buf_32[i], chip->IO_ADDR_W);
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}
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static int mt62xx_nand_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
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@ -418,6 +443,18 @@ int board_nand_init(struct nand_chip *chip)
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chip->write_buf = mt62xx_nand_write_buf;
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chip->select_chip = mt62xx_nand_select_chip;
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/*
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* Below option allows U-Boot to save BBT table in NAND.
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* Without this option BBT table is created everytime when first nand
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* command is executed (except "nand dump"). Full scanning of NAND
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* takes long time and unnecessarily delays start of platform.
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*/
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#ifdef MT62XX_NAND_BBT_IN_NAND
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chip->options |= NAND_USE_FLASH_BBT;
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chip->bbt_td = &bbt_main_descr;
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chip->bbt_md = &bbt_mirror_descr;
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#endif
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/* ECC settings */
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.calculate = mt62xx_nand_ecc_calculate;
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@ -126,6 +126,19 @@
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/*
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* Below option allows U-Boot to save BBT table in NAND.
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* Without this option BBT table is created everytime when first nand
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* command is executed (except "nand dump"). Full scanning of NAND
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* takes long time and unnecessarily delays start of platform.
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*
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* NOTE! This option is disabled by defaut as at startup it deletes last
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* two blocks of NAND. Most of people run code from RAM and don't have
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* NAND memory dumped yet. If you don't like to wait on first nand
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* command, you should enable below option.
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*/
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//#define MT62XX_NAND_BBT_IN_NAND
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/* Enable support for mmc. */
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#define CONFIG_MMC 1
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