* Patch by Gleb Natapov, 14 Sep 2003:
enable watchdog support for all MPC824x boards that have a watchdog * On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the "Non-octet Aligned Frame" errors we see at 100 Mbps * Patch by Sharad Gupta, 14 Sep 2003: fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
This commit is contained in:
wdenk
parent
200f8c7a4c
commit
35656de729
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@ -2,6 +2,15 @@
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Changes for U-Boot 1.0.0:
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======================================================================
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* Patch by Gleb Natapov, 14 Sep 2003:
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enable watchdog support for all MPC824x boards that have a watchdog
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* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
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"Non-octet Aligned Frame" errors we see at 100 Mbps
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* Patch by Sharad Gupta, 14 Sep 2003:
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fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
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* Patch by llandre, 11 Sep 2003:
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update configuration for PPChameleonEVB board
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@ -427,7 +427,11 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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#ifndef CONFIG_FEC_10MBIT
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miiphy_write(phyAddr, 0x4, 0x01e1);
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#else
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miiphy_write(phyAddr, 0x4, 0x061);/* Advertise 10FDX */
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#endif
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/*
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* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
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@ -48,9 +48,11 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
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{
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*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
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eieio();
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udelay(10);
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*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
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eieio();
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*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
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udelay(10);
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return 0;
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}
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@ -59,9 +61,11 @@ static int mpc5200_write_config_dword(struct pci_controller *hose,
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{
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*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
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eieio();
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udelay(10);
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out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
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eieio();
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*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
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udelay(10);
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return 0;
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}
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@ -382,6 +382,14 @@ init_5xxx_core:
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mtspr DBAT2L, r0
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mtspr DBAT3U, r0
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mtspr DBAT3L, r0
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mtspr DBAT4U, r0
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mtspr DBAT4L, r0
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mtspr DBAT5U, r0
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mtspr DBAT5L, r0
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mtspr DBAT6U, r0
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mtspr DBAT6L, r0
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mtspr DBAT7U, r0
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mtspr DBAT7L, r0
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mtspr IBAT0U, r0
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mtspr IBAT0L, r0
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mtspr IBAT1U, r0
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@ -390,6 +398,14 @@ init_5xxx_core:
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mtspr IBAT2L, r0
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mtspr IBAT3U, r0
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mtspr IBAT3L, r0
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mtspr IBAT4U, r0
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mtspr IBAT4L, r0
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mtspr IBAT5U, r0
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mtspr IBAT5L, r0
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mtspr IBAT6U, r0
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mtspr IBAT6L, r0
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mtspr IBAT7U, r0
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mtspr IBAT7L, r0
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SYNC
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/* invalidate all tlb's */
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@ -27,6 +27,7 @@
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#include <asm/processor.h>
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#include <asm/pci_io.h>
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#include <commproc.h>
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#include <watchdog.h>
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#include "drivers/epic.h"
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/****************************************************************************/
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@ -149,15 +150,9 @@ void timer_interrupt (struct pt_regs *regs)
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timestamp++;
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#if defined(CONFIG_WATCHDOG)
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#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
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if ((timestamp % (CFG_HZ / 2)) == 0) {
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#if defined(CONFIG_OXC)
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{
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extern void oxc_wdt_reset (void);
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oxc_wdt_reset ();
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}
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#endif
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WATCHDOG_RESET ();
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}
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_SHOW_ACTIVITY) && defined(CONFIG_OXC)
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@ -95,14 +95,14 @@
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#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
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#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
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#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
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#define SPRN_DBAT4L 0x238 /* Data BAT 4 Lower Register */
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#define SPRN_DBAT4U 0x239 /* Data BAT 4 Upper Register */
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#define SPRN_DBAT5L 0x23A /* Data BAT 5 Lower Register */
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#define SPRN_DBAT5U 0x23B /* Data BAT 5 Upper Register */
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#define SPRN_DBAT6L 0x23C /* Data BAT 6 Lower Register */
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#define SPRN_DBAT6U 0x23D /* Data BAT 6 Upper Register */
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#define SPRN_DBAT7L 0x23E /* Data BAT 7 Lower Register */
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#define SPRN_DBAT7U 0x23F /* Data BAT 7 Lower Register */
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#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
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#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
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#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
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#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
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#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
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#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
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#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
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#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
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#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
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#define DBCR_EDM 0x80000000
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#define DBCR_IDM 0x40000000
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@ -203,14 +203,14 @@
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#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
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#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
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#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
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#define SPRN_IBAT4L 0x230 /* Instruction BAT 4 Lower Register */
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#define SPRN_IBAT4U 0x231 /* Instruction BAT 4 Upper Register */
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#define SPRN_IBAT5L 0x232 /* Instruction BAT 5 Lower Register */
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#define SPRN_IBAT5U 0x233 /* Instruction BAT 5 Upper Register */
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#define SPRN_IBAT6L 0x234 /* Instruction BAT 6 Lower Register */
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#define SPRN_IBAT6U 0x235 /* Instruction BAT 6 Upper Register */
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#define SPRN_IBAT7L 0x236 /* Instruction BAT 7 Lower Register */
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#define SPRN_IBAT7U 0x237 /* Instruction BAT 7 Lower Register */
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#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
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#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
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#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
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#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
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#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
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#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
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#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
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#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
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#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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#define ICCR_NOCACHE 0 /* Noncacheable */
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#define ICCR_CACHE 1 /* Cacheable */
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@ -179,6 +179,7 @@
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* Ethernet configuration
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*/
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#define CONFIG_MPC5XXX_FEC 1
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#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
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/*
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* GPIO configuration
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