Add support for friendly-arm SBC-2410X board
Patch by JinHua Luo, 01 Sep 2005
This commit is contained in:
Wolfgang Denk
parent
e644670b68
commit
32cb2c70c4
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Add support for friendly-arm SBC-2410X board
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Patch by JinHua Luo, 01 Sep 2005
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* Fix multi-part image support on i386 platform.
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Patch by David Updegraff, 19 Aug 2005
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7
MAKEALL
7
MAKEALL
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@ -181,9 +181,10 @@ LIST_ARM9=" \
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ap966 cp920t cp922_XA10 cp926ejs \
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cp946es cp966 lpd7a400 mp2usb \
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mx1ads mx1fs2 netstar omap1510inn \
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omap1610h2 omap1610inn omap730p2 scb9328 \
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smdk2400 smdk2410 trab VCMA9 \
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versatile versatileab versatilepb voiceblue
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omap1610h2 omap1610inn omap730p2 sbc2410x \
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scb9328 smdk2400 smdk2410 trab \
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VCMA9 versatile versatileab versatilepb \
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voiceblue \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -1623,6 +1623,9 @@ omap730p2_cs3boot_config : unconfig
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fi;
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@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
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sbc2410x_config: unconfig
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@./mkconfig $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
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scb9328_config : unconfig
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@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := sbc2410x.o flash.o
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SOBJS := lowlevel_init.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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@ -0,0 +1,23 @@
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
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#
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# see http://www.samsung.com/ for more information on SAMSUNG
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#
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#
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# SMDK2410 has 1 bank of 64 MB DRAM
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#
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# 3000'0000 to 3400'0000
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#
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# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
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# optionally with a ramdisk at 3080'0000
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#
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# we load ourself to 33F8'0000
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#
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# download area is 3300'0000
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TEXT_BASE = 0x33F80000
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@ -0,0 +1,431 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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ulong myflush (void);
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#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
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#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#define CMD_READ_ARRAY 0x000000F0
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#define CMD_UNLOCK1 0x000000AA
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#define CMD_UNLOCK2 0x00000055
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#define CMD_ERASE_SETUP 0x00000080
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#define CMD_ERASE_CONFIRM 0x00000030
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#define CMD_PROGRAM 0x000000A0
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#define CMD_UNLOCK_BYPASS 0x00000020
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#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
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#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
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#define BIT_ERASE_DONE 0x00000080
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#define BIT_RDY_MASK 0x00000080
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#define BIT_PROGRAM_ERROR 0x00000020
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#define BIT_TIMEOUT 0x80000000 /* our flag */
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#define READY 1
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#define ERR 2
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#define TMO 4
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/*-----------------------------------------------------------------------
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*/
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ulong flash_init (void)
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{
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int i, j;
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ulong size = 0;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
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ulong flashbase = 0;
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flash_info[i].flash_id =
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#if defined(CONFIG_AMD_LV400)
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(AMD_MANUFACT & FLASH_VENDMASK) |
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(AMD_ID_LV400B & FLASH_TYPEMASK);
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#elif defined(CONFIG_AMD_LV800)
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(AMD_MANUFACT & FLASH_VENDMASK) |
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(AMD_ID_LV800B & FLASH_TYPEMASK);
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#else
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#error "Unknown flash configured"
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#endif
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flash_info[i].size = FLASH_BANK_SIZE;
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flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
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memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
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if (i == 0)
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flashbase = PHYS_FLASH_1;
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else
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panic ("configured too many flash banks!\n");
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for (j = 0; j < flash_info[i].sector_count; j++) {
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if (j <= 3) {
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/* 1st one is 16 KB */
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if (j == 0) {
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flash_info[i].start[j] =
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flashbase + 0;
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}
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/* 2nd and 3rd are both 8 KB */
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if ((j == 1) || (j == 2)) {
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flash_info[i].start[j] =
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flashbase + 0x4000 + (j -
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1) *
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0x2000;
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}
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/* 4th 32 KB */
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if (j == 3) {
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flash_info[i].start[j] =
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flashbase + 0x8000;
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}
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} else {
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flash_info[i].start[j] =
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flashbase + (j - 3) * MAIN_SECT_SIZE;
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}
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}
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size += flash_info[i].size;
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}
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flash_protect (FLAG_PROTECT_SET,
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CFG_FLASH_BASE,
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CFG_FLASH_BASE + monitor_flash_len - 1,
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&flash_info[0]);
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flash_protect (FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
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return size;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t * info)
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{
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int i;
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switch (info->flash_id & FLASH_VENDMASK) {
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case (AMD_MANUFACT & FLASH_VENDMASK):
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printf ("AMD: ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case (AMD_ID_LV400B & FLASH_TYPEMASK):
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printf ("1x Amd29LV400BB (4Mbit)\n");
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break;
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case (AMD_ID_LV800B & FLASH_TYPEMASK):
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printf ("1x Amd29LV800BB (8Mbit)\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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goto Done;
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; i++) {
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if ((i % 5) == 0) {
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printf ("\n ");
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}
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printf (" %08lX%s", info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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Done:;
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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ushort result;
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int iflag, cflag, prot, sect;
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int rc = ERR_OK;
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int chip;
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/* first look for protection bits */
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if (info->flash_id == FLASH_UNKNOWN)
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return ERR_UNKNOWN_FLASH_TYPE;
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if ((s_first < 0) || (s_first > s_last)) {
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return ERR_INVAL;
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}
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if ((info->flash_id & FLASH_VENDMASK) !=
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(AMD_MANUFACT & FLASH_VENDMASK)) {
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return ERR_UNKNOWN_FLASH_VENDOR;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot)
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return ERR_PROTECTED;
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/*
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* Disable interrupts which might cause a timeout
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* here. Remember that our exception vectors are
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* at address 0 in the flash, and we don't want a
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* (ticker) exception to happen while the flash
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* chip is in programming mode.
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*/
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cflag = icache_status ();
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icache_disable ();
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iflag = disable_interrupts ();
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
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printf ("Erasing sector %2d ... ", sect);
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked ();
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if (info->protect[sect] == 0) { /* not protected */
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vu_short *addr = (vu_short *) (info->start[sect]);
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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*addr = CMD_ERASE_CONFIRM;
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/* wait until flash is ready */
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chip = 0;
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do {
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result = *addr;
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/* check timeout */
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if (get_timer_masked () >
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CFG_FLASH_ERASE_TOUT) {
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
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chip = TMO;
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break;
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}
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if (!chip
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&& (result & 0xFFFF) & BIT_ERASE_DONE)
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chip = READY;
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if (!chip
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&& (result & 0xFFFF) & BIT_PROGRAM_ERROR)
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chip = ERR;
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} while (!chip);
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
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if (chip == ERR) {
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rc = ERR_PROG_ERROR;
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goto outahere;
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}
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if (chip == TMO) {
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rc = ERR_TIMOUT;
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goto outahere;
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}
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printf ("ok.\n");
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} else { /* it was protected */
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printf ("protected!\n");
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}
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}
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if (ctrlc ())
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printf ("User Interrupt!\n");
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outahere:
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/* allow flash to settle - wait 10 ms */
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udelay_masked (10000);
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if (iflag)
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enable_interrupts ();
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if (cflag)
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icache_enable ();
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return rc;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash
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*/
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volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
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{
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vu_short *addr = (vu_short *) dest;
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ushort result;
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int rc = ERR_OK;
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int cflag, iflag;
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int chip;
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/*
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* Check if Flash is (sufficiently) erased
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*/
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result = *addr;
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if ((result & data) != data)
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return ERR_NOT_ERASED;
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|
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/*
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* Disable interrupts which might cause a timeout
|
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* here. Remember that our exception vectors are
|
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* at address 0 in the flash, and we don't want a
|
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* (ticker) exception to happen while the flash
|
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* chip is in programming mode.
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*/
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cflag = icache_status ();
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icache_disable ();
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iflag = disable_interrupts ();
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
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*addr = CMD_PROGRAM;
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*addr = data;
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked ();
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/* wait until flash is ready */
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chip = 0;
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do {
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result = *addr;
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|
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/* check timeout */
|
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if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
|
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chip = ERR | TMO;
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break;
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}
|
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if (!chip && ((result & 0x80) == (data & 0x80)))
|
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chip = READY;
|
||||
|
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if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
|
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result = *addr;
|
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|
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if ((result & 0x80) == (data & 0x80))
|
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chip = READY;
|
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else
|
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chip = ERR;
|
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}
|
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|
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} while (!chip);
|
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|
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*addr = CMD_READ_ARRAY;
|
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|
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if (chip == ERR || *addr != data)
|
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rc = ERR_PROG_ERROR;
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|
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if (iflag)
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enable_interrupts ();
|
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|
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if (cflag)
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icache_enable ();
|
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return rc;
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}
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|
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/*-----------------------------------------------------------------------
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* Copy memory to flash.
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||||
*/
|
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|
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp;
|
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int l;
|
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int i, rc;
|
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ushort data;
|
||||
|
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wp = (addr & ~1); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
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data = 0;
|
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for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
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data = (data >> 8) | (*(uchar *) cp << 8);
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}
|
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for (; i < 2 && cnt > 0; ++i) {
|
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data = (data >> 8) | (*src++ << 8);
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||||
--cnt;
|
||||
++cp;
|
||||
}
|
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for (; cnt == 0 && i < 2; ++i, ++cp) {
|
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data = (data >> 8) | (*(uchar *) cp << 8);
|
||||
}
|
||||
|
||||
if ((rc = write_hword (info, wp, data)) != 0) {
|
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return (rc);
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}
|
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wp += 2;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 2) {
|
||||
data = *((vu_short *) src);
|
||||
if ((rc = write_hword (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 2;
|
||||
wp += 2;
|
||||
cnt -= 2;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
|
||||
data = (data >> 8) | (*src++ << 8);
|
||||
--cnt;
|
||||
}
|
||||
for (; i < 2; ++i, ++cp) {
|
||||
data = (data >> 8) | (*(uchar *) cp << 8);
|
||||
}
|
||||
|
||||
return write_hword (info, wp, data);
|
||||
}
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Memory Setup stuff - taken from blob memsetup.S
|
||||
*
|
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
|
||||
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
|
||||
*
|
||||
* Modified for the Samsung SMDK2410 by
|
||||
* (C) Copyright 2002
|
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
*
|
||||
* Modified for the friendly-arm SBC-2410X by
|
||||
* (C) Copyright 2005
|
||||
* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
/*
|
||||
* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
|
||||
*
|
||||
* Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
|
||||
*/
|
||||
|
||||
#define BWSCON 0x48000000
|
||||
|
||||
/* BWSCON */
|
||||
#define DW8 (0x0)
|
||||
#define DW16 (0x1)
|
||||
#define DW32 (0x2)
|
||||
#define WAIT (0x1<<2)
|
||||
#define UBLB (0x1<<3)
|
||||
|
||||
#define B1_BWSCON (DW16)
|
||||
#define B2_BWSCON (DW16)
|
||||
#define B3_BWSCON (DW16 + WAIT + UBLB)
|
||||
#define B4_BWSCON (DW16)
|
||||
#define B5_BWSCON (DW16)
|
||||
#define B6_BWSCON (DW32)
|
||||
#define B7_BWSCON (DW32)
|
||||
|
||||
#define B0_Tacs 0x0
|
||||
#define B0_Tcos 0x0
|
||||
#define B0_Tacc 0x7
|
||||
#define B0_Tcoh 0x0
|
||||
#define B0_Tah 0x0
|
||||
#define B0_Tacp 0x0
|
||||
#define B0_PMC 0x0
|
||||
|
||||
#define B1_Tacs 0x0
|
||||
#define B1_Tcos 0x0
|
||||
#define B1_Tacc 0x7
|
||||
#define B1_Tcoh 0x0
|
||||
#define B1_Tah 0x0
|
||||
#define B1_Tacp 0x0
|
||||
#define B1_PMC 0x0
|
||||
|
||||
#define B2_Tacs 0x0
|
||||
#define B2_Tcos 0x0
|
||||
#define B2_Tacc 0x7
|
||||
#define B2_Tcoh 0x0
|
||||
#define B2_Tah 0x0
|
||||
#define B2_Tacp 0x0
|
||||
#define B2_PMC 0x0
|
||||
|
||||
#define B3_Tacs 0xc
|
||||
#define B3_Tcos 0x7
|
||||
#define B3_Tacc 0xf
|
||||
#define B3_Tcoh 0x1
|
||||
#define B3_Tah 0x0
|
||||
#define B3_Tacp 0x0
|
||||
#define B3_PMC 0x0
|
||||
|
||||
#define B4_Tacs 0x0
|
||||
#define B4_Tcos 0x0
|
||||
#define B4_Tacc 0x7
|
||||
#define B4_Tcoh 0x0
|
||||
#define B4_Tah 0x0
|
||||
#define B4_Tacp 0x0
|
||||
#define B4_PMC 0x0
|
||||
|
||||
#define B5_Tacs 0xc
|
||||
#define B5_Tcos 0x7
|
||||
#define B5_Tacc 0xf
|
||||
#define B5_Tcoh 0x1
|
||||
#define B5_Tah 0x0
|
||||
#define B5_Tacp 0x0
|
||||
#define B5_PMC 0x0
|
||||
|
||||
#define B6_MT 0x3 /* SDRAM */
|
||||
#define B6_Trcd 0x1
|
||||
#define B6_SCAN 0x1 /* 9bit */
|
||||
|
||||
#define B7_MT 0x3 /* SDRAM */
|
||||
#define B7_Trcd 0x1 /* 3clk */
|
||||
#define B7_SCAN 0x1 /* 9bit */
|
||||
|
||||
/* REFRESH parameter */
|
||||
#define REFEN 0x1 /* Refresh enable */
|
||||
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
|
||||
#define Trp 0x0 /* 2clk */
|
||||
#define Trc 0x3 /* 7clk */
|
||||
#define Tchr 0x2 /* 3clk */
|
||||
#define REFCNT 0x0459
|
||||
/**************************************/
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
/* memory control configuration */
|
||||
/* make r0 relative the current location so that it */
|
||||
/* reads SMRDATA out of FLASH rather than memory ! */
|
||||
ldr r0, =SMRDATA
|
||||
ldr r1, _TEXT_BASE
|
||||
sub r0, r0, r1
|
||||
ldr r1, =BWSCON /* Bus Width Status Controller */
|
||||
add r2, r0, #13*4
|
||||
0:
|
||||
ldr r3, [r0], #4
|
||||
str r3, [r1], #4
|
||||
cmp r2, r0
|
||||
bne 0b
|
||||
|
||||
/* everything is fine now */
|
||||
mov pc, lr
|
||||
|
||||
.ltorg
|
||||
/* the literal pools origin */
|
||||
|
||||
SMRDATA:
|
||||
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
|
||||
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
|
||||
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
|
||||
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
|
||||
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
|
||||
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
|
||||
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
|
||||
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
|
||||
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
|
||||
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
|
||||
.word 0xb2
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
*
|
||||
* (C) Copyright 2005
|
||||
* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <s3c2410.h>
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
#include <linux/mtd/nand.h>
|
||||
#endif
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define FCLK_SPEED 1
|
||||
|
||||
#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
|
||||
#define M_MDIV 0xC3
|
||||
#define M_PDIV 0x4
|
||||
#define M_SDIV 0x1
|
||||
#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
|
||||
#define M_MDIV 0x5c
|
||||
#define M_PDIV 0x4
|
||||
#define M_SDIV 0x0
|
||||
#endif
|
||||
|
||||
#define USB_CLOCK 1
|
||||
|
||||
#if USB_CLOCK==0
|
||||
#define U_M_MDIV 0xA1
|
||||
#define U_M_PDIV 0x3
|
||||
#define U_M_SDIV 0x1
|
||||
#elif USB_CLOCK==1
|
||||
#define U_M_MDIV 0x48
|
||||
#define U_M_PDIV 0x3
|
||||
#define U_M_SDIV 0x2
|
||||
#endif
|
||||
|
||||
static inline void delay (unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0" (loops));
|
||||
}
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
|
||||
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||
|
||||
/* to reduce PLL lock time, adjust the LOCKTIME register */
|
||||
clk_power->LOCKTIME = 0xFFFFFF;
|
||||
|
||||
/* configure MPLL */
|
||||
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
|
||||
|
||||
/* some delay between MPLL and UPLL */
|
||||
delay (4000);
|
||||
|
||||
/* configure UPLL */
|
||||
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
|
||||
|
||||
/* some delay between MPLL and UPLL */
|
||||
delay (8000);
|
||||
|
||||
/* set up the I/O ports */
|
||||
gpio->GPACON = 0x007FFFFF;
|
||||
gpio->GPBCON = 0x00044556;
|
||||
gpio->GPBUP = 0x000007FF;
|
||||
gpio->GPCCON = 0xAAAAAAAA;
|
||||
gpio->GPCUP = 0x0000FFFF;
|
||||
gpio->GPDCON = 0xAAAAAAAA;
|
||||
gpio->GPDUP = 0x0000FFFF;
|
||||
gpio->GPECON = 0xAAAAAAAA;
|
||||
gpio->GPEUP = 0x0000FFFF;
|
||||
gpio->GPFCON = 0x000055AA;
|
||||
gpio->GPFUP = 0x000000FF;
|
||||
gpio->GPGCON = 0xFF95FF3A;
|
||||
gpio->GPGUP = 0x0000FFFF;
|
||||
gpio->GPHCON = 0x0016FAAA;
|
||||
gpio->GPHUP = 0x000007FF;
|
||||
|
||||
gpio->EXTINT0=0x22222222;
|
||||
gpio->EXTINT1=0x22222222;
|
||||
gpio->EXTINT2=0x22222222;
|
||||
|
||||
/* arch number of SMDK2410-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0x30000100;
|
||||
|
||||
icache_enable();
|
||||
dcache_enable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
extern ulong nand_probe(ulong physadr);
|
||||
|
||||
static inline void NF_Reset(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
NF_SetCE(NFCE_LOW);
|
||||
NF_Cmd(0xFF); /* reset command */
|
||||
for(i = 0; i < 10; i++); /* tWB = 100ns. */
|
||||
NF_WaitRB(); /* wait 200~500us; */
|
||||
NF_SetCE(NFCE_HIGH);
|
||||
}
|
||||
|
||||
static inline void NF_Init(void)
|
||||
{
|
||||
#if 1
|
||||
#define TACLS 0
|
||||
#define TWRPH0 3
|
||||
#define TWRPH1 0
|
||||
#else
|
||||
#define TACLS 0
|
||||
#define TWRPH0 4
|
||||
#define TWRPH1 2
|
||||
#endif
|
||||
|
||||
NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
|
||||
/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
|
||||
/* 1 1 1 1, 1 xxx, r xxx, r xxx */
|
||||
/* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
|
||||
|
||||
NF_Reset();
|
||||
}
|
||||
|
||||
void nand_init(void)
|
||||
{
|
||||
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
|
||||
|
||||
NF_Init();
|
||||
#ifdef DEBUG
|
||||
printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
|
||||
#endif
|
||||
printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
|
||||
}
|
||||
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm920t/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -176,7 +176,9 @@ ulong get_tbclk (void)
|
|||
|
||||
#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
|
||||
tbclk = timer_load_val * 100;
|
||||
#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9)
|
||||
#elif defined(CONFIG_SBC2410X) || \
|
||||
defined(CONFIG_SMDK2410) || \
|
||||
defined(CONFIG_VCMA9)
|
||||
tbclk = CFG_HZ;
|
||||
#else
|
||||
# error "tbclk not configured"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
* Gary Jennejohn <gj@denx.de>
|
||||
* David Mueller <d.mueller@elsoft.ch>
|
||||
*
|
||||
* Modified for the friendly-arm SBC-2410X by
|
||||
* (C) Copyright 2005
|
||||
* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
|
||||
*
|
||||
* Configuation settings for the friendly-arm SBC-2410X board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
|
||||
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
|
||||
#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
|
||||
|
||||
/* input clock of PLL */
|
||||
#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
|
||||
|
||||
|
||||
#define USE_920T_MMU 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
|
||||
#define CS8900_BASE 0x19000300
|
||||
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
|
||||
|
||||
/************************************************************
|
||||
* RTC
|
||||
************************************************************/
|
||||
#define CONFIG_RTC_S3C24X0 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/***********************************************************
|
||||
* Command definition
|
||||
***********************************************************/
|
||||
#define CONFIG_COMMANDS \
|
||||
(CONFIG_CMD_DFL | \
|
||||
CFG_CMD_CACHE | \
|
||||
/*CFG_CMD_NAND |*/ \
|
||||
/*CFG_CMD_EEPROM |*/ \
|
||||
/*CFG_CMD_I2C |*/ \
|
||||
/*CFG_CMD_USB |*/ \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_ELF)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
|
||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.0.69
|
||||
#define CONFIG_SERVERIP 192.168.0.1
|
||||
/*#define CONFIG_BOOTFILE "elinos-lart" */
|
||||
#define CONFIG_BOOTCOMMAND "dhcp; bootm"
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
/* what's this ? it's not used anywhere */
|
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x33000000 /* default load address */
|
||||
|
||||
/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
|
||||
/* it to wrap 100 times (total 1562500) to get 1 sec. */
|
||||
#define CFG_HZ 1562500
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
|
||||
|
||||
#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
|
||||
#ifdef CONFIG_AMD_LV800
|
||||
#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
|
||||
#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AMD_LV400
|
||||
#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
|
||||
#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
|
||||
#endif
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND flash settings
|
||||
*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define NAND_WAIT_READY(nand) NF_WaitRB()
|
||||
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
|
||||
#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
|
||||
#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
|
||||
#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
|
||||
#define WRITE_NAND(d, adr) NF_Write(d)
|
||||
#define READ_NAND(adr) NF_Read()
|
||||
/* the following functions are NOP's because S3C24X0 handles this in hardware */
|
||||
#define NAND_CTL_CLRALE(nandptr)
|
||||
#define NAND_CTL_SETALE(nandptr)
|
||||
#define NAND_CTL_CLRCLE(nandptr)
|
||||
#define NAND_CTL_SETCLE(nandptr)
|
||||
/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
|
||||
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
|
||||
#define CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
#ifdef CONFIG_CMDLINE_EDITING
|
||||
#undef CONFIG_AUTO_COMPLETE
|
||||
#else
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue