* Patch by Yuli Barcohen, 09 Jun 2004:
Add support for Analogue&Micro Adder87x and the older AdderII board. * Patch by Ming-Len Wu, 09 Jun 2004: Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
This commit is contained in:
wdenk
parent
e63c8ee3dc
commit
2d24a3a787
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@ -2,6 +2,12 @@
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|||
Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Yuli Barcohen, 09 Jun 2004:
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Add support for Analogue&Micro Adder87x and the older AdderII board.
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* Patch by Ming-Len Wu, 09 Jun 2004:
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Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
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* Patch by Sam Song, 09 Jun 2004:
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- Add support for RPXlite_DW board
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- Update FLASH driver for 4*AM29DL323DB90VI
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28
CREDITS
28
CREDITS
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@ -39,6 +39,7 @@ E: yuli@arabellasw.com
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D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
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D: Support for Zephyr Engineering ZPC.1900 board.
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D: Support for Interphase iSPAN boards.
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D: Support for Analogue&Micro Adder boards.
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W: http://www.arabellasw.com
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N: Jerry van Baren
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@ -307,6 +308,10 @@ N: Erwin Rol
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E: erwin@muffin.org
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D: boot support for RTEMS
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N: Paul Ruhland
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E: pruhland@rochester.rr.com
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D: Port to Logic Zoom LH7A40x SDK board(s)
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N: Neil Russell
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E: caret@c-side.com
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D: Author of LiMon-1.4.2, which contributed some ideas
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@ -347,13 +352,22 @@ N: David Updegraff
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E: dave@cray.com
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D: Port to Cray L1 board; DHCP vendor extensions
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N: Christian Vejlbo
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E: christian.vejlbo@tellabs.com
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D: FADS860T ethernet support
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N: Martin Winistoerfer
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E: martinwinistoerfer@gmx.ch
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D: Port to MPC555/556 microcontrollers and support for cmi board
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N: Christian Vejlbo
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E: christian.vejlbo@tellabs.com
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D: FADS860T ethernet support
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N: Ming-Len Wu
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E: minglen_wu@techware.com.tw
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D: Motorola MX1ADS board support
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W: http://www.techware.com.tw/
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N: Xianghua Xiao
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E: x.xiao@motorola.com
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D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
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N: John Zhan
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E: zhanz@sinovee.com
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@ -363,11 +377,3 @@ N: Alex Zuepke
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E: azu@sysgo.de
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D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
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W: www.elinos.com
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N: Xianghua Xiao
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E: x.xiao@motorola.com
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D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
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N: Paul Ruhland
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E: pruhland@rochester.rr.com
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D: Port to Logic Zoom LH7A40x SDK board(s)
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@ -27,6 +27,7 @@ Pantelis Antoniou <panto@intracom.gr>
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Yuli Barcohen <yuli@arabellasw.com>
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Adder MPC87x/MPC852T
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ISPAN MPC8260
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MPC8260ADS MPC826x/MPC827x/MPC8280
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ZPC1900 MPC8265
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|
|
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10
MAKEALL
10
MAKEALL
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@ -33,6 +33,7 @@ LIST_5xxx=" \
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#########################################################################
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LIST_8xx=" \
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Adder GENIETV MBX860T RBC823 \
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AdderII GTH MHPC rmu \
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ADS860 hermes MPC86xADS RPXClassic \
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AMX860 IAD210 MPC885ADS RPXlite \
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@ -49,7 +50,6 @@ LIST_8xx=" \
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FPS850L LANTEC QS850 TQM855L \
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GEN860T lwmon QS860T TQM860L \
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GEN860T_SC MBX R360MPI v37 \
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GENIETV MBX860T RBC823 \
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"
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#########################################################################
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@ -139,10 +139,10 @@ LIST_ARM7="B2 ep7312 impa7"
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LIST_ARM9=" \
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at91rm9200dk integratorcp integratorap \
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lpd7a400 omap1510inn omap1610h2 \
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omap1610inn omap730p2 smdk2400 \
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smdk2410 trab VCMA9 \
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versatile \
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lpd7a400 mx1ads omap1510inn \
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omap1610h2 omap1610inn omap730p2 \
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smdk2400 smdk2410 trab \
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VCMA9 versatile \
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"
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#########################################################################
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|
|
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38
Makefile
38
Makefile
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@ -262,6 +262,14 @@ PM520_config: unconfig
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## MPC8xx Systems
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#########################################################################
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Adder_config \
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Adder87x_config \
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Adder852_config \
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: unconfig
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$(if $(findstring 852,$@), \
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@echo "#define CONFIG_MPC852T" > include/config.h)
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@./mkconfig -a Adder ppc mpc8xx adder
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AdderII_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx adderII
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@ -1048,17 +1056,14 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
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xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
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SX1_config : unconfig
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@./mkconfig $(@:_config=) arm arm925t sx1
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integratorcp_config : unconfig
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@./mkconfig $(@:_config=) arm arm926ejs integratorcp
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integratorap_config : unconfig
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@./mkconfig $(@:_config=) arm arm926ejs integratorap
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versatile_config : unconfig
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@./mkconfig $(@:_config=) arm arm926ejs versatile
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lpd7a400_config: unconfig
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@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
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omap1510inn_config : unconfig
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@./mkconfig $(@:_config=) arm arm925t omap1510inn
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@ -1104,6 +1109,12 @@ smdk2400_config : unconfig
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smdk2410_config : unconfig
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@./mkconfig $(@:_config=) arm arm920t smdk2410
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SX1_config : unconfig
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@./mkconfig $(@:_config=) arm arm925t sx1
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mx1ads_config : unconfig
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@./mkconfig $(@:_config=) arm mc9328 mx1ads
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# TRAB default configuration: 8 MB Flash, 32 MB RAM
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trab_config \
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trab_bigram_config \
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@ -1132,8 +1143,8 @@ trab_old_config: unconfig
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VCMA9_config : unconfig
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@./mkconfig $(@:_config=) arm arm920t vcma9 mpl
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lpd7a400_config: unconfig
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@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
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versatile_config : unconfig
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@./mkconfig $(@:_config=) arm arm926ejs versatile
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#########################################################################
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## S3C44B0 Systems
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@ -1142,16 +1153,23 @@ lpd7a400_config: unconfig
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B2_config : unconfig
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@./mkconfig $(@:_config=) arm s3c44b0 B2 dave
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#########################################################################
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## MC9328 (Dragonball) Systems
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#########################################################################
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mx1ads_config : unconfig
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@./mkconfig $(@:_config=) arm mc9328 mx1ads
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#########################################################################
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## ARM720T Systems
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#########################################################################
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impa7_config : unconfig
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@./mkconfig $(@:_config=) arm arm720t impa7
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ep7312_config : unconfig
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@./mkconfig $(@:_config=) arm arm720t ep7312
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impa7_config : unconfig
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@./mkconfig $(@:_config=) arm arm720t impa7
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modnet50_config : unconfig
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@./mkconfig $(@:_config=) arm arm720t modnet50
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@ -0,0 +1,46 @@
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#
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# Copyright (C) 2004 Arabella Software Ltd.
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# Yuli Barcohen <yuli@arabellasw.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
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||||
#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o
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$(LIB): $(OBJS) $(SOBJS)
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||||
$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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||||
distclean: clean
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rm -f $(LIB) core *.bak .depend
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||||
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||||
#########################################################################
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||||
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||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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||||
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||||
-include .depend
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||||
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||||
#########################################################################
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||||
|
|
@ -0,0 +1,107 @@
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|||
/*
|
||||
* Copyright (C) 2004 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* Support for Analogue&Micro Adder boards family.
|
||||
* Tested on AdderII and Adder87x.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
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||||
#include <mpc8xx.h>
|
||||
|
||||
/*
|
||||
* SDRAM is single Samsung K4S643232F-T70 chip.
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||||
* Minimal CPU frequency is 40MHz.
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||||
*/
|
||||
static uint sdram_table[] = {
|
||||
/* Single read (offset 0x00 in UPM RAM) */
|
||||
0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
|
||||
0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
|
||||
|
||||
/* Burst read (offset 0x08 in UPM RAM) */
|
||||
0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
|
||||
0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
|
||||
0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
|
||||
0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
|
||||
|
||||
/* Single write (offset 0x18 in UPM RAM) */
|
||||
0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
|
||||
0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
|
||||
|
||||
/* Burst write (offset 0x20 in UPM RAM) */
|
||||
0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
|
||||
0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
|
||||
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
|
||||
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
|
||||
|
||||
/* Refresh (offset 0x30 in UPM RAM) */
|
||||
0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
|
||||
0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
|
||||
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
|
||||
|
||||
/* Exception (offset 0x3C in UPM RAM) */
|
||||
0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
|
||||
};
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long int msize = CFG_SDRAM_SIZE;
|
||||
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
|
||||
|
||||
/* Configure SDRAM refresh */
|
||||
memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
|
||||
|
||||
memctl->memc_mamr = (94 << 24) | CFG_MAMR;
|
||||
memctl->memc_mar = 0x0;
|
||||
udelay(200);
|
||||
|
||||
/* Run precharge from location 0x15 */
|
||||
memctl->memc_mcr = 0x80002115;
|
||||
udelay(200);
|
||||
|
||||
/* Run 8 refresh cycles */
|
||||
memctl->memc_mcr = 0x80002830;
|
||||
udelay(200);
|
||||
|
||||
memctl->memc_mar = 0x88;
|
||||
udelay(200);
|
||||
|
||||
/* Run MRS pattern from location 0x16 */
|
||||
memctl->memc_mcr = 0x80002116;
|
||||
udelay(200);
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
||||
int checkboard( void )
|
||||
{
|
||||
puts("Board: Adder");
|
||||
#if defined(CONFIG_MPC885_FAMILY)
|
||||
puts("87x\n");
|
||||
#elif defined(CONFIG_MPC866_FAMILY)
|
||||
puts("II\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#
|
||||
# Copyright (C) 2004 Arabella Software Ltd.
|
||||
# Yuli Barcohen <yuli@arabellasw.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Analogue&Micro Adder boards family
|
||||
#
|
||||
TEXT_BASE = 0xFE000000
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Modified by Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc8xx/start.o (.text)
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
ENTRY(_start)
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#/*
|
||||
#* board/mx1ads/Makefile
|
||||
#*
|
||||
#* (c) Copyright 2004
|
||||
#* Techware Information Technology, Inc.
|
||||
#* http://www.techware.com.tw/
|
||||
#*
|
||||
#* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
#*
|
||||
#* This program is free software; you can redistribute it and/or
|
||||
#* modify it under the terms of the GNU General Public License as
|
||||
#* published by the Free Software Foundation; either version 2 of
|
||||
#* the License, or (at your option) any later version.
|
||||
#*
|
||||
#* This program is distributed in the hope that it will be useful,
|
||||
#* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
#* GNU General Public License for more details.
|
||||
#*
|
||||
#* You should have received a copy of the GNU General Public License
|
||||
#* along with this program; if not, write to the Free Software
|
||||
#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
#* MA 02111-1307 USA
|
||||
#*/
|
||||
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := mx1ads.o syncflash.o
|
||||
SOBJS := memsetup.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
#/*
|
||||
#* board/mx1ads/config.mk
|
||||
#*
|
||||
#* (c) Copyright 2004
|
||||
#* Techware Information Technology, Inc.
|
||||
#* http://www.techware.com.tw/
|
||||
#*
|
||||
#* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
#*
|
||||
#* This program is free software; you can redistribute it and/or
|
||||
#* modify it under the terms of the GNU General Public License as
|
||||
#* published by the Free Software Foundation; either version 2 of
|
||||
#* the License, or (at your option) any later version.
|
||||
#*
|
||||
#* This program is distributed in the hope that it will be useful,
|
||||
#* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
#* GNU General Public License for more details.
|
||||
#*
|
||||
#* You should have received a copy of the GNU General Public License
|
||||
#* along with this program; if not, write to the Free Software
|
||||
#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
#* MA 02111-1307 USA
|
||||
#*/
|
||||
|
||||
|
||||
TEXT_BASE = 0x08400000
|
||||
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* board/mx1ads/memsetup.S
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
#define SDCTL0 0x221000
|
||||
#define SDCTL1 0x221004
|
||||
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
|
||||
.globl memsetup
|
||||
memsetup:
|
||||
/* memory controller init */
|
||||
|
||||
ldr r1, =SDCTL0
|
||||
|
||||
/* Set Precharge Command */
|
||||
|
||||
ldr r3, =0x92120200
|
||||
/* ldr r3, =0x92120251
|
||||
*/
|
||||
str r3, [r1]
|
||||
|
||||
/* Issue Precharge All Commad */
|
||||
ldr r3, =0x8200000
|
||||
ldr r2, [r3]
|
||||
|
||||
/* Set AutoRefresh Command */
|
||||
ldr r3, =0xA2120200
|
||||
str r3, [r1]
|
||||
|
||||
/* Issue AutoRefresh Command */
|
||||
ldr r3, =0x8000000
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
ldr r2, [r3]
|
||||
|
||||
/* Set Mode Register */
|
||||
ldr r3, =0xB2120200
|
||||
str r3, [r1]
|
||||
|
||||
/* Issue Mode Register Command */
|
||||
ldr r3, =0x08111800 /* Mode Register Value */
|
||||
ldr r2, [r3]
|
||||
|
||||
/* Set Normal Mode */
|
||||
ldr r3, =0x82124200
|
||||
str r3, [r1]
|
||||
|
||||
/* everything is fine now */
|
||||
mov pc, lr
|
||||
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* board/mx1ads/mx1ads.c
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <mc9328.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define FCLK_SPEED 1
|
||||
|
||||
#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
|
||||
#define M_MDIV 0xC3
|
||||
#define M_PDIV 0x4
|
||||
#define M_SDIV 0x1
|
||||
#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
|
||||
#define M_MDIV 0xA1
|
||||
#define M_PDIV 0x3
|
||||
#define M_SDIV 0x1
|
||||
#endif
|
||||
|
||||
#define USB_CLOCK 1
|
||||
|
||||
#if USB_CLOCK==0
|
||||
#define U_M_MDIV 0xA1
|
||||
#define U_M_PDIV 0x3
|
||||
#define U_M_SDIV 0x1
|
||||
#elif USB_CLOCK==1
|
||||
#define U_M_MDIV 0x48
|
||||
#define U_M_PDIV 0x3
|
||||
#define U_M_SDIV 0x2
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
|
||||
static inline void delay (unsigned long loops) {
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0" (loops));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
|
||||
void SetAsynchMode(void) {
|
||||
__asm__ (
|
||||
"mrc p15,0,r0,c1,c0,0 \n"
|
||||
"mov r2, #0xC0000000 \n"
|
||||
"orr r0,r2,r0 \n"
|
||||
"mcr p15,0,r0,c1,c0,0 \n"
|
||||
);
|
||||
}
|
||||
|
||||
static u32 mc9328sid;
|
||||
|
||||
int board_init (void) {
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
volatile unsigned int tmp;
|
||||
|
||||
mc9328sid = MX1_SIDR;
|
||||
|
||||
MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
|
||||
|
||||
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
|
||||
/* MX1_CS1L = 0x11110601; */
|
||||
|
||||
|
||||
MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
|
||||
|
||||
/* MX1_MPCTL0 = 0x003f1437; *//* setting for 192 MHz MCU PLL CLK */
|
||||
|
||||
|
||||
|
||||
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
|
||||
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
|
||||
*/
|
||||
MX1_CSCR = 0xAF000403;
|
||||
|
||||
MX1_CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
|
||||
MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
|
||||
|
||||
/* setup cs4 for cs8900 ethernet */
|
||||
|
||||
MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
|
||||
MX1_CS4L = 0x00001501;
|
||||
|
||||
MX1_GIUS_A &= 0xFF3FFFFF;
|
||||
MX1_GPR_A &= 0xFF3FFFFF;
|
||||
|
||||
tmp = *(unsigned int *)(0x1500000C);
|
||||
tmp = *(unsigned int *)(0x1500000C);
|
||||
|
||||
/* setup timer 1 as system timer */
|
||||
|
||||
MX1_TPRER1 = 0x1f; /* divide by 32 */
|
||||
MX1_TCTL1 = 0x19; /* clock in from 32k Osc. */
|
||||
|
||||
|
||||
SetAsynchMode();
|
||||
|
||||
gd->bd->bi_arch_number = 160; /* Arch number of MX1ADS Board */
|
||||
|
||||
gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
|
||||
|
||||
icache_enable();
|
||||
dcache_enable();
|
||||
|
||||
/* set PERCLKs */
|
||||
MX1_PCDR = 0x00000055; /* set PERCLKS */
|
||||
|
||||
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
|
||||
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
|
||||
* all sources selected as normal interrupt
|
||||
*/
|
||||
MX1_INTTYPEH = 0;
|
||||
MX1_INTTYPEL = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int board_late_init(void) {
|
||||
|
||||
setenv("stdout", "serial");
|
||||
setenv("stderr", "serial");
|
||||
|
||||
switch (mc9328sid) {
|
||||
case 0x0005901d :
|
||||
printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
|
||||
break;
|
||||
case 0x04d4c01d :
|
||||
printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
|
||||
break;
|
||||
case 0x00d4c01d :
|
||||
printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
|
||||
break;
|
||||
|
||||
default :
|
||||
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int dram_init (void) {
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
/*
|
||||
* board/mx1ads/syncflash.c
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mc9328.h>
|
||||
|
||||
typedef unsigned long * p_u32;
|
||||
|
||||
/* 4Mx16x2 IAM=0 CSD1 */
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/* Following Setting is for CSD1 */
|
||||
#define SFCTL 0x00221004
|
||||
#define reg_SFCTL __REG(SFCTL)
|
||||
|
||||
#define SYNCFLASH_A10 (0x00100000)
|
||||
|
||||
#define CMD_NORMAL (0x81020300) /* Normal Mode */
|
||||
#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
|
||||
#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
|
||||
#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
|
||||
#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
|
||||
#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
|
||||
|
||||
#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
|
||||
|
||||
/* LCR Command */
|
||||
#define LCR_READSTATUS (0x0001C000) /* 0x70 */
|
||||
#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
|
||||
#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
|
||||
#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
|
||||
#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
|
||||
|
||||
|
||||
/* Get Status register */
|
||||
u32 SF_SR(void) {
|
||||
u32 tmp,tmp1;
|
||||
|
||||
reg_SFCTL = CMD_PROGRAM;
|
||||
tmp = __REG(CFG_FLASH_BASE);
|
||||
|
||||
reg_SFCTL = CMD_NORMAL;
|
||||
|
||||
reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
|
||||
tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/* check if SyncFlash is ready */
|
||||
u8 SF_Ready(void) {
|
||||
u32 tmp;
|
||||
|
||||
tmp = SF_SR();
|
||||
|
||||
if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
|
||||
printf ("SyncFlash Error code %08x\n",tmp);
|
||||
};
|
||||
|
||||
if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
|
||||
printf ("SyncFlash Error code %08x\n",tmp);
|
||||
|
||||
};
|
||||
|
||||
if (tmp == 0x00800080) /* Test Bit 7 of SR */
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Issue the precharge all command */
|
||||
void SF_PrechargeAll(void) {
|
||||
|
||||
u32 tmp;
|
||||
|
||||
reg_SFCTL = CMD_PREC; /* Set Precharge Command */
|
||||
tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
|
||||
|
||||
}
|
||||
|
||||
/* set SyncFlash to normal mode */
|
||||
void SF_Normal(void) {
|
||||
|
||||
SF_PrechargeAll();
|
||||
|
||||
reg_SFCTL = CMD_NORMAL;
|
||||
}
|
||||
|
||||
/* Erase SyncFlash */
|
||||
void SF_Erase(u32 RowAddress) {
|
||||
u32 tmp;
|
||||
|
||||
reg_SFCTL = CMD_NORMAL;
|
||||
tmp = __REG(RowAddress);
|
||||
|
||||
reg_SFCTL = CMD_PREC;
|
||||
tmp = __REG(RowAddress);
|
||||
|
||||
reg_SFCTL = CMD_LCR; /* Set LCR mode */
|
||||
__REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
|
||||
|
||||
reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
|
||||
__REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
|
||||
|
||||
while(!SF_Ready());
|
||||
}
|
||||
|
||||
|
||||
void SF_NvmodeErase(void) {
|
||||
SF_PrechargeAll();
|
||||
|
||||
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
|
||||
__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
|
||||
|
||||
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
|
||||
__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
|
||||
|
||||
while(!SF_Ready());
|
||||
}
|
||||
|
||||
void SF_NvmodeWrite(void) {
|
||||
SF_PrechargeAll();
|
||||
|
||||
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
|
||||
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
|
||||
|
||||
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
|
||||
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
|
||||
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************************/
|
||||
|
||||
ulong flash_init(void) {
|
||||
int i, j;
|
||||
u32 tmp;
|
||||
|
||||
/* Turn on CSD1 for negating RESETSF of SyncFLash */
|
||||
|
||||
reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
|
||||
udelay(200);
|
||||
|
||||
reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
|
||||
tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
|
||||
|
||||
SF_Normal();
|
||||
|
||||
i = 0;
|
||||
|
||||
flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
|
||||
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
|
||||
|
||||
memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
|
||||
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
|
||||
}
|
||||
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_FLASH_BASE,
|
||||
CFG_FLASH_BASE + monitor_flash_len - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
return FLASH_BANK_SIZE;
|
||||
}
|
||||
|
||||
|
||||
void flash_print_info (flash_info_t *info) {
|
||||
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (FLASH_MAN_MT & FLASH_VENDMASK):
|
||||
printf("Micron: ");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
|
||||
printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Chip Type\n");
|
||||
return;
|
||||
break;
|
||||
}
|
||||
|
||||
printf(" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf(" Sector Start Addresses: ");
|
||||
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) {
|
||||
int iflag, cflag, prot, sect;
|
||||
int rc = ERR_OK;
|
||||
|
||||
/* first look for protection bits */
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return ERR_UNKNOWN_FLASH_TYPE;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last))
|
||||
return ERR_INVAL;
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
|
||||
prot = 0;
|
||||
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf("protected!\n");
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status();
|
||||
icache_disable();
|
||||
iflag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
|
||||
|
||||
printf("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
|
||||
reset_timer_masked();
|
||||
|
||||
SF_NvmodeErase();
|
||||
SF_NvmodeWrite();
|
||||
|
||||
SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect));
|
||||
SF_Normal();
|
||||
|
||||
printf("ok.\n");
|
||||
}
|
||||
|
||||
if (ctrlc())
|
||||
printf("User Interrupt!\n");
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts();
|
||||
|
||||
if (cflag)
|
||||
icache_enable();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash.
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
|
||||
int i;
|
||||
|
||||
for(i = 0; i < cnt; i += 4) {
|
||||
|
||||
SF_PrechargeAll();
|
||||
|
||||
reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
|
||||
__REG(addr + i) = __REG((u32)src + i);
|
||||
|
||||
while(!SF_Ready());
|
||||
}
|
||||
|
||||
SF_Normal();
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* board/mx1ads/u-boot.lds
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/mc9328/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
OBJS = serial.o interrupts.o cpu.o
|
||||
|
||||
all: .depend $(START) $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||
-mshort-load-bytes -msoft-float
|
||||
|
||||
PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* CPU specific code
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <arm920t.h>
|
||||
|
||||
/* read co-processor 15, register #1 (control register) */
|
||||
static unsigned long read_p15_c1 (void)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
|
||||
: "=r" (value)
|
||||
:
|
||||
: "memory");
|
||||
|
||||
#ifdef MMU_DEBUG
|
||||
printf ("p15/c1 is = %08lx\n", value);
|
||||
#endif
|
||||
return value;
|
||||
}
|
||||
|
||||
/* write to co-processor 15, register #1 (control register) */
|
||||
static void write_p15_c1 (unsigned long value)
|
||||
{
|
||||
#ifdef MMU_DEBUG
|
||||
printf ("write %08lx to p15/c1\n", value);
|
||||
#endif
|
||||
__asm__ __volatile__(
|
||||
"mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
|
||||
:
|
||||
: "r" (value)
|
||||
: "memory");
|
||||
|
||||
read_p15_c1 ();
|
||||
}
|
||||
|
||||
static void cp_delay (void)
|
||||
{
|
||||
volatile int i;
|
||||
|
||||
/* copro seems to need some delay between reading and writing */
|
||||
for (i = 0; i < 100; i++);
|
||||
}
|
||||
|
||||
/* See also ARM Ref. Man. */
|
||||
#define C1_MMU (1<<0) /* mmu off/on */
|
||||
#define C1_ALIGN (1<<1) /* alignment faults off/on */
|
||||
#define C1_DC (1<<2) /* dcache off/on */
|
||||
#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
|
||||
#define C1_SYS_PROT (1<<8) /* system protection */
|
||||
#define C1_ROM_PROT (1<<9) /* ROM protection */
|
||||
#define C1_IC (1<<12) /* icache off/on */
|
||||
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
|
||||
#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
|
||||
|
||||
int cpu_init (void)
|
||||
{
|
||||
/*
|
||||
* setup up stacks if necessary
|
||||
*/
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
|
||||
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cleanup_before_linux (void)
|
||||
{
|
||||
/*
|
||||
* this function is called just before we call linux
|
||||
* it prepares the processor for linux
|
||||
*
|
||||
* we turn off caches etc ...
|
||||
*/
|
||||
|
||||
unsigned long i;
|
||||
|
||||
disable_interrupts ();
|
||||
|
||||
/* turn off I/D-cache */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
i &= ~(C1_DC | C1_IC);
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
|
||||
/* flush I/D-cache */
|
||||
i = 0;
|
||||
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
|
||||
return (0);
|
||||
}
|
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
extern void reset_cpu (ulong addr);
|
||||
|
||||
disable_interrupts ();
|
||||
reset_cpu (0);
|
||||
/*NOTREACHED*/
|
||||
return (0);
|
||||
}
|
||||
|
||||
void icache_enable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
write_p15_c1 (reg | C1_IC);
|
||||
}
|
||||
|
||||
void icache_disable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
write_p15_c1 (reg & ~C1_IC);
|
||||
}
|
||||
|
||||
int icache_status (void)
|
||||
{
|
||||
return (read_p15_c1 () & C1_IC) != 0;
|
||||
}
|
||||
|
||||
#ifdef USE_920T_MMU
|
||||
/* It makes no sense to use the dcache if the MMU is not enabled */
|
||||
void dcache_enable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
write_p15_c1 (reg | C1_DC);
|
||||
}
|
||||
|
||||
void dcache_disable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
reg &= ~C1_DC;
|
||||
write_p15_c1 (reg);
|
||||
}
|
||||
|
||||
int dcache_status (void)
|
||||
{
|
||||
return (read_p15_c1 () & C1_DC) != 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Alex Zuepke <azu@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <arm920t.h>
|
||||
#include <mc9328.h>
|
||||
|
||||
#include <asm/proc-armv/ptrace.h>
|
||||
|
||||
extern void reset_cpu(ulong addr);
|
||||
int timer_load_val = 0;
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* enable IRQ interrupts */
|
||||
void enable_interrupts (void)
|
||||
{
|
||||
unsigned long temp;
|
||||
__asm__ __volatile__("mrs %0, cpsr\n"
|
||||
"bic %0, %0, #0x80\n"
|
||||
"msr cpsr_c, %0"
|
||||
: "=r" (temp)
|
||||
:
|
||||
: "memory");
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* disable IRQ/FIQ interrupts
|
||||
* returns true if interrupts had been enabled before we disabled them
|
||||
*/
|
||||
int disable_interrupts (void)
|
||||
{
|
||||
unsigned long old,temp;
|
||||
__asm__ __volatile__("mrs %0, cpsr\n"
|
||||
"orr %1, %0, #0xc0\n"
|
||||
"msr cpsr_c, %1"
|
||||
: "=r" (old), "=r" (temp)
|
||||
:
|
||||
: "memory");
|
||||
return (old & 0x80) == 0;
|
||||
}
|
||||
#else
|
||||
void enable_interrupts (void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
int disable_interrupts (void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
void bad_mode (void)
|
||||
{
|
||||
panic ("Resetting CPU ...\n");
|
||||
reset_cpu (0);
|
||||
}
|
||||
|
||||
void show_regs (struct pt_regs *regs)
|
||||
{
|
||||
unsigned long flags;
|
||||
const char *processor_modes[] = {
|
||||
"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
|
||||
"UK4_26", "UK5_26", "UK6_26", "UK7_26",
|
||||
"UK8_26", "UK9_26", "UK10_26", "UK11_26",
|
||||
"UK12_26", "UK13_26", "UK14_26", "UK15_26",
|
||||
"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
|
||||
"UK4_32", "UK5_32", "UK6_32", "ABT_32",
|
||||
"UK8_32", "UK9_32", "UK10_32", "UND_32",
|
||||
"UK12_32", "UK13_32", "UK14_32", "SYS_32",
|
||||
};
|
||||
|
||||
flags = condition_codes (regs);
|
||||
|
||||
printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
|
||||
"sp : %08lx ip : %08lx fp : %08lx\n",
|
||||
instruction_pointer (regs),
|
||||
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
|
||||
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
|
||||
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
|
||||
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
|
||||
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
|
||||
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
|
||||
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
|
||||
printf ("Flags: %c%c%c%c",
|
||||
flags & CC_N_BIT ? 'N' : 'n',
|
||||
flags & CC_Z_BIT ? 'Z' : 'z',
|
||||
flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
|
||||
printf (" IRQs %s FIQs %s Mode %s%s\n",
|
||||
interrupts_enabled (regs) ? "on" : "off",
|
||||
fast_interrupts_enabled (regs) ? "on" : "off",
|
||||
processor_modes[processor_mode (regs)],
|
||||
thumb_mode (regs) ? " (T)" : "");
|
||||
}
|
||||
|
||||
void do_undefined_instruction (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("undefined instruction\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_software_interrupt (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("software interrupt\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_prefetch_abort (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("prefetch abort\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_data_abort (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("data abort\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_not_used (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("not used\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_fiq (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("fast interrupt request\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_irq (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("interrupt request\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
|
||||
int interrupt_init (void)
|
||||
{
|
||||
|
||||
/* we don't use interrupt */
|
||||
return(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
|
||||
void reset_timer (void)
|
||||
{
|
||||
reset_timer_masked ();
|
||||
}
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
{
|
||||
return get_timer_masked ();
|
||||
}
|
||||
|
||||
void set_timer (ulong t)
|
||||
{
|
||||
/* Nop */
|
||||
}
|
||||
|
||||
void udelay (unsigned long usec)
|
||||
{
|
||||
udelay_masked (usec);
|
||||
}
|
||||
|
||||
void reset_timer_masked (void)
|
||||
{
|
||||
u32 tmp;
|
||||
MX1_TCTL1 = 0x09;
|
||||
tmp = 0x1f; /* a little delay for timer to reset */
|
||||
MX1_TPRER1 = 0x1f;
|
||||
MX1_TCTL1 = 0x19;
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
{
|
||||
return MX1_TCN1;
|
||||
}
|
||||
|
||||
void udelay_masked (unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
|
||||
tmo = usec / 1000;
|
||||
tmo *= CFG_HZ;
|
||||
tmo /= 1000;
|
||||
|
||||
reset_timer_masked ();
|
||||
|
||||
while (get_timer_masked () < tmo);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
|
||||
ulong get_tbclk (void) {
|
||||
return CFG_HZ;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* cpu/mc9328/serial.c
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <mc9328.h>
|
||||
|
||||
#if defined(CONFIG_UART1)
|
||||
/* GPIO PORT B */
|
||||
|
||||
#define reg_GIUS MX1_GIUS_C
|
||||
#define reg_GPR MX1_GPR_B
|
||||
#define GPIO_MASK 0xFFFFE1FF
|
||||
#define UART_BASE 0x00206000
|
||||
|
||||
|
||||
#elif defined (CONFIG_UART2)
|
||||
/* GPIO PORT C */
|
||||
|
||||
#define reg_GIUS MX1_GIUS_C
|
||||
#define reg_GPR MX1_GPR_C
|
||||
#define GPIO_MASK 0x0FFFFFFF
|
||||
#define UART_BASE 0x207000
|
||||
|
||||
#endif
|
||||
|
||||
#define reg_URXD (*((volatile u32 *)(UART_BASE+0x00)))
|
||||
#define reg_UTXD (*((volatile u32 *)(UART_BASE+0x40)))
|
||||
#define reg_UCR1 (*((volatile u32 *)(UART_BASE+0x80)))
|
||||
#define reg_UCR2 (*((volatile u32 *)(UART_BASE+0x84)))
|
||||
#define reg_UCR3 (*((volatile u32 *)(UART_BASE+0x88)))
|
||||
#define reg_UCR4 (*((volatile u32 *)(UART_BASE+0x8C)))
|
||||
#define reg_UFCR (*((volatile u32 *)(UART_BASE+0x90)))
|
||||
#define reg_USR1 (*((volatile u32 *)(UART_BASE+0x94)))
|
||||
#define reg_USR2 (*((volatile u32 *)(UART_BASE+0x98)))
|
||||
#define reg_UESC (*((volatile u32 *)(UART_BASE+0x9C)))
|
||||
#define reg_UTIM (*((volatile u32 *)(UART_BASE+0xA0)))
|
||||
#define reg_UBIR (*((volatile u32 *)(UART_BASE+0xA4)))
|
||||
#define reg_UBMR (*((volatile u32 *)(UART_BASE+0xA8)))
|
||||
#define reg_UBRC (*((volatile u32 *)(UART_BASE+0xAC)))
|
||||
|
||||
#define TXFE_MASK 0x4000 /* Tx buffer empty */
|
||||
#define RDR_MASK 0x0001 /* receive data ready */
|
||||
|
||||
|
||||
void serial_setbrg (void) {
|
||||
|
||||
/* config I/O pins for UART */
|
||||
|
||||
reg_GIUS &= GPIO_MASK;
|
||||
reg_GPR &= GPIO_MASK;
|
||||
|
||||
/* config UART */
|
||||
|
||||
reg_UCR1 = 5;
|
||||
reg_UCR2 = 0x4027;
|
||||
reg_UCR4 = 1;
|
||||
reg_UFCR = 0xA81;
|
||||
|
||||
reg_UBIR = 0xF;
|
||||
reg_UBMR = 0x8A;
|
||||
reg_UBRC = 8;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings
|
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits.
|
||||
*
|
||||
*/
|
||||
|
||||
int serial_init (void) {
|
||||
serial_setbrg ();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0
|
||||
* otherwise. When the function is succesfull, the character read is
|
||||
* written into its argument c.
|
||||
*/
|
||||
int serial_getc (void) {
|
||||
|
||||
while (!(reg_USR2 & RDR_MASK)) ; /* wait until RDR bit set */
|
||||
|
||||
return (u8)reg_URXD;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port.
|
||||
*/
|
||||
void serial_putc (const char c) {
|
||||
|
||||
while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
|
||||
|
||||
reg_UTXD = (u16) c;
|
||||
|
||||
if (c == '\n') { /* carriage return ? append line-feed */
|
||||
while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
|
||||
reg_UTXD = '\r';
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test whether a character is in the RX buffer
|
||||
*/
|
||||
int serial_tstc (void) {
|
||||
return reg_USR2 & RDR_MASK;
|
||||
}
|
||||
|
||||
|
||||
void serial_puts (const char *s) {
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,388 @@
|
|||
/*
|
||||
* armboot - Startup Code for ARM920 CPU-core
|
||||
*
|
||||
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
||||
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
||||
* Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Jump vector table as in table 3.1 in [1]
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
.globl _start
|
||||
_start: b reset
|
||||
ldr pc, _undefined_instruction
|
||||
ldr pc, _software_interrupt
|
||||
ldr pc, _prefetch_abort
|
||||
ldr pc, _data_abort
|
||||
ldr pc, _not_used
|
||||
ldr pc, _irq
|
||||
ldr pc, _fiq
|
||||
|
||||
_undefined_instruction: .word undefined_instruction
|
||||
_software_interrupt: .word software_interrupt
|
||||
_prefetch_abort: .word prefetch_abort
|
||||
_data_abort: .word data_abort
|
||||
_not_used: .word not_used
|
||||
_irq: .word irq
|
||||
_fiq: .word fiq
|
||||
|
||||
.balignl 16,0xdeadbeef
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Startup Code (reset vector)
|
||||
*
|
||||
* do important init only if we don't start from memory!
|
||||
* relocate armboot to ram
|
||||
* setup stack
|
||||
* jump to second stage
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
|
||||
.globl _armboot_start
|
||||
_armboot_start:
|
||||
.word _start
|
||||
|
||||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
*/
|
||||
.globl _bss_start
|
||||
_bss_start:
|
||||
.word __bss_start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end:
|
||||
.word _end
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START:
|
||||
.word 0x0badc0de
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START:
|
||||
.word 0x0badc0de
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* the actual reset code
|
||||
*/
|
||||
|
||||
reset:
|
||||
/*
|
||||
* set the cpu to SVC32 mode
|
||||
*/
|
||||
mrs r0,cpsr
|
||||
bic r0,r0,#0x1f
|
||||
orr r0,r0,#0xd3
|
||||
msr cpsr,r0
|
||||
|
||||
/*
|
||||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from ram!
|
||||
*/
|
||||
#ifdef CONFIG_INIT_CRITICAL
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
relocate: /* relocate U-Boot to RAM */
|
||||
adr r0, _start /* r0 <- current position of code */
|
||||
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
||||
cmp r0, r1 /* don't reloc during debug */
|
||||
beq stack_setup
|
||||
|
||||
ldr r2, _armboot_start
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||
add r2, r0, r2 /* r2 <- source end address */
|
||||
|
||||
copy_loop:
|
||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
||||
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
||||
cmp r0, r2 /* until source end addreee [r2] */
|
||||
ble copy_loop
|
||||
|
||||
/* Set up the stack */
|
||||
stack_setup:
|
||||
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
|
||||
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
|
||||
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
|
||||
#endif
|
||||
sub sp, r0, #12 /* leave 3 words for abort-stack */
|
||||
|
||||
clear_bss:
|
||||
ldr r0, _bss_start /* find start of bss segment */
|
||||
ldr r1, _bss_end /* stop here */
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
clbss_l:str r2, [r0] /* clear loop... */
|
||||
add r0, r0, #4
|
||||
cmp r0, r1
|
||||
bne clbss_l
|
||||
|
||||
ldr pc, _start_armboot
|
||||
|
||||
_start_armboot: .word start_armboot
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* CPU_init_critical registers
|
||||
*
|
||||
* setup important registers
|
||||
* setup memory timing
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* flush v4 I/D caches
|
||||
*/
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
||||
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
||||
|
||||
/*
|
||||
* disable MMU stuff and caches
|
||||
*/
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
||||
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
||||
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
|
||||
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
|
||||
/*
|
||||
* before relocating, we have to setup RAM timing
|
||||
* because memory timing is board-dependend, you will
|
||||
* find a memsetup.S in your board directory.
|
||||
*/
|
||||
mov ip, lr
|
||||
bl memsetup
|
||||
mov lr, ip
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Interrupt handling
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
@
|
||||
@ IRQ stack frame.
|
||||
@
|
||||
#define S_FRAME_SIZE 72
|
||||
|
||||
#define S_OLD_R0 68
|
||||
#define S_PSR 64
|
||||
#define S_PC 60
|
||||
#define S_LR 56
|
||||
#define S_SP 52
|
||||
|
||||
#define S_IP 48
|
||||
#define S_FP 44
|
||||
#define S_R10 40
|
||||
#define S_R9 36
|
||||
#define S_R8 32
|
||||
#define S_R7 28
|
||||
#define S_R6 24
|
||||
#define S_R5 20
|
||||
#define S_R4 16
|
||||
#define S_R3 12
|
||||
#define S_R2 8
|
||||
#define S_R1 4
|
||||
#define S_R0 0
|
||||
|
||||
#define MODE_SVC 0x13
|
||||
#define I_BIT 0x80
|
||||
|
||||
/*
|
||||
* use bad_save_user_regs for abort/prefetch/undef/swi ...
|
||||
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
|
||||
*/
|
||||
|
||||
.macro bad_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
ldr r2, _armboot_start
|
||||
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
|
||||
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||
ldmia r2, {r2 - r3} @ get pc, cpsr
|
||||
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
||||
|
||||
add r5, sp, #S_SP
|
||||
mov r1, lr
|
||||
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
|
||||
mov r0, sp
|
||||
.endm
|
||||
|
||||
.macro irq_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
add r8, sp, #S_PC
|
||||
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
||||
str lr, [r8, #0] @ Save calling PC
|
||||
mrs r6, spsr
|
||||
str r6, [r8, #4] @ Save CPSR
|
||||
str r0, [r8, #8] @ Save OLD_R0
|
||||
mov r0, sp
|
||||
.endm
|
||||
|
||||
.macro irq_restore_user_regs
|
||||
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
||||
mov r0, r0
|
||||
ldr lr, [sp, #S_PC] @ Get PC
|
||||
add sp, sp, #S_FRAME_SIZE
|
||||
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
||||
.endm
|
||||
|
||||
.macro get_bad_stack
|
||||
ldr r13, _armboot_start @ setup our mode stack
|
||||
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
|
||||
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||
|
||||
str lr, [r13] @ save caller lr / spsr
|
||||
mrs lr, spsr
|
||||
str lr, [r13, #4]
|
||||
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode
|
||||
@ msr spsr_c, r13
|
||||
msr spsr, r13
|
||||
mov lr, pc
|
||||
movs pc, lr
|
||||
.endm
|
||||
|
||||
.macro get_irq_stack @ setup IRQ stack
|
||||
ldr sp, IRQ_STACK_START
|
||||
.endm
|
||||
|
||||
.macro get_fiq_stack @ setup FIQ stack
|
||||
ldr sp, FIQ_STACK_START
|
||||
.endm
|
||||
|
||||
/*
|
||||
* exception handlers
|
||||
*/
|
||||
.align 5
|
||||
undefined_instruction:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_undefined_instruction
|
||||
|
||||
.align 5
|
||||
software_interrupt:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_software_interrupt
|
||||
|
||||
.align 5
|
||||
prefetch_abort:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_prefetch_abort
|
||||
|
||||
.align 5
|
||||
data_abort:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_data_abort
|
||||
|
||||
.align 5
|
||||
not_used:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_not_used
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
|
||||
.align 5
|
||||
irq:
|
||||
get_irq_stack
|
||||
irq_save_user_regs
|
||||
bl do_irq
|
||||
irq_restore_user_regs
|
||||
|
||||
.align 5
|
||||
fiq:
|
||||
get_fiq_stack
|
||||
/* someone ought to write a more effiction fiq_save_user_regs */
|
||||
irq_save_user_regs
|
||||
bl do_fiq
|
||||
irq_restore_user_regs
|
||||
|
||||
#else
|
||||
|
||||
.align 5
|
||||
irq:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_irq
|
||||
|
||||
.align 5
|
||||
fiq:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_fiq
|
||||
|
||||
#endif
|
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
reset_cpu:
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
|
||||
mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
|
||||
mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
|
||||
bic ip, ip, #0x000f @ ............wcam
|
||||
bic ip, ip, #0x2100 @ ..v....s........
|
||||
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
|
||||
mov pc, r0
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* Support for Analogue&Micro Adder boards family.
|
||||
* Tested on AdderII and Adder87x.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
|
||||
#define CONFIG_MPC875
|
||||
#endif
|
||||
|
||||
#define CONFIG_ADDER /* Analogue&Micro Adder board */
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
#define CONFIG_FEC_ENET /* Ethernet is on FEC */
|
||||
#ifdef CONFIG_FEC_ENET
|
||||
#define CFG_DISCOVER_PHY
|
||||
#define FEC_ENET
|
||||
#endif /* CONFIG_FEC_ENET */
|
||||
|
||||
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
| CFG_CMD_DHCP \
|
||||
| CFG_CMD_IMMAP \
|
||||
| CFG_CMD_MII \
|
||||
| CFG_CMD_PING \
|
||||
)
|
||||
|
||||
/* This must be included AFTER the definition of CONFIG_COMMANDS */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
|
||||
|
||||
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#define CFG_LONGHELP /* #undef to save memory */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* Max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* Default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RAM configuration (note that CFG_SDRAM_BASE must be zero)
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
|
||||
|
||||
#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2)
|
||||
#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V)
|
||||
|
||||
#define CFG_MAMR 0x00802114
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
|
||||
|
||||
#define CFG_RESET_ADDRESS 0x09900000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */
|
||||
#ifdef CONFIG_BZIP2
|
||||
#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
|
||||
#else
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
|
||||
#endif /* CONFIG_BZIP2 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Flash organisation
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xFE000000
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
|
||||
|
||||
/* Environment is in flash */
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
|
||||
#define CFG_OR0_PRELIM 0xFF000774
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Map Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFF000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Configuration registers
|
||||
*/
|
||||
#ifdef CONFIG_WATCHDOG
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
|
||||
SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
|
||||
SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
|
||||
SYPCR_SWF | SYPCR_SWP)
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
|
||||
|
||||
/* TBSCR - Time Base Status and Control Register */
|
||||
#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
|
||||
|
||||
/* PISCR - Periodic Interrupt Status and Control */
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/* PLPRCR - PLL, Low-Power, and Reset Control Register */
|
||||
/* #define CFG_PLPRCR PLPRCR_TEXPS */
|
||||
|
||||
/* SCCR - System Clock and reset Control Register */
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CFG_SCCR SCCR_RTSEL
|
||||
|
||||
#define CFG_DER 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* include/configs/mx1ads.h
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* This is the Configuration setting for Motorola MX1ADS board
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
|
||||
#define CONFIG_MC9328 1 /* It's a Motorola MC9328 SoC */
|
||||
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
|
||||
|
||||
#define BOARD_LATE_INIT 1
|
||||
|
||||
|
||||
#define USE_920T_MMU 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#if 0
|
||||
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
|
||||
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
|
||||
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
* CS8900 Ethernet drivers
|
||||
*/
|
||||
#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
|
||||
#define CS8900_BASE 0x15000300
|
||||
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_UART1 1
|
||||
/* #define CONFIG_UART2 1 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/***********************************************************
|
||||
* Command definition
|
||||
***********************************************************/
|
||||
|
||||
#define CONFIG_COMMANDS \
|
||||
(CONFIG_CMD_DFL | \
|
||||
CFG_CMD_CACHE | \
|
||||
/*CFG_CMD_NAND |*/ \
|
||||
/*CFG_CMD_EEPROM |*/ \
|
||||
/*CFG_CMD_I2C |*/ \
|
||||
/*CFG_CMD_USB |*/ \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_ELF)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M"
|
||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5c
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.0.22
|
||||
#define CONFIG_SERVERIP 192.168.0.11
|
||||
#define CONFIG_BOOTFILE "mx1ads"
|
||||
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
/* what's this ? it's not used anywhere */
|
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
#define CFG_HUSH_PARSER 1
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
|
||||
#else
|
||||
#define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
|
||||
#endif
|
||||
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x09000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x08800000 /* default load address */
|
||||
|
||||
|
||||
#define CFG_HZ 1000
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
|
||||
#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
|
||||
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
|
||||
#define CONFIG_SYNCFLASH 1
|
||||
#define PHYS_FLASH_SIZE 0x01000000
|
||||
#define CFG_MAX_FLASH_SECT (16)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff0000)
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x0f000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x100000
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -372,6 +372,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
|
||||
#define FLASH_FUJLV650 0x00B4 /* Fujitsu MBM 29LV650UE/651UE */
|
||||
|
||||
#define FLASH_MT28S4M16LC 0x00B5 /* Micron MT28S4M16LC */
|
||||
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue