Add SGMII support to the tsec
Adds support for configuring the TBI to talk properly with the SerDes. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Andy Fleming
Ben Warren
parent
75b9d4ae0d
commit
2abe361c03
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@ -216,61 +216,80 @@ int tsec_init(struct eth_device *dev, bd_t * bd)
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return (priv->link ? 0 : -1);
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}
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/* Write value to the device's PHY through the registers
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* specified in priv, modifying the register specified in regnum.
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* It will wait for the write to be done (or for a timeout to
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* expire) before exiting
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*/
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void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value)
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/* Writes the given phy's reg with value, using the specified MDIO regs */
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static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr,
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uint reg, uint value)
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{
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volatile tsec_t *regbase = priv->phyregs;
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int timeout = 1000000;
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regbase->miimadd = (phyid << 8) | regnum;
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regbase->miimcon = value;
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phyregs->miimadd = (addr << 8) | reg;
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phyregs->miimcon = value;
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asm("sync");
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timeout = 1000000;
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while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
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while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
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}
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/* #define to provide old write_phy_reg functionality without duplicating code */
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#define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value)
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/* Provide the default behavior of writing the PHY of this ethernet device */
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#define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
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/* Reads register regnum on the device's PHY through the
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* registers specified in priv. It lowers and raises the read
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* specified registers. It lowers and raises the read
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* command, and waits for the data to become valid (miimind
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* notvalid bit cleared), and the bus to cease activity (miimind
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* busy bit cleared), and then returns the value
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*/
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uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum)
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uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
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{
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uint value;
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volatile tsec_t *regbase = priv->phyregs;
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/* Put the address of the phy, and the register
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* number into MIIMADD */
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regbase->miimadd = (phyid << 8) | regnum;
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phyregs->miimadd = (phyid << 8) | regnum;
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/* Clear the command register, and wait */
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regbase->miimcom = 0;
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phyregs->miimcom = 0;
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asm("sync");
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/* Initiate a read command, and wait */
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regbase->miimcom = MIIM_READ_COMMAND;
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phyregs->miimcom = MIIM_READ_COMMAND;
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asm("sync");
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/* Wait for the the indication that the read is done */
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while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
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while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
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/* Grab the value read from the PHY */
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value = regbase->miimstat;
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value = phyregs->miimstat;
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return value;
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}
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/* #define to provide old read_phy_reg functionality without duplicating code */
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#define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum)
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#define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
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#define TBIANA_SETTINGS ( \
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TBIANA_ASYMMETRIC_PAUSE \
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| TBIANA_SYMMETRIC_PAUSE \
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| TBIANA_FULL_DUPLEX \
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)
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#define TBICR_SETTINGS ( \
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TBICR_PHY_RESET \
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| TBICR_ANEG_ENABLE \
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| TBICR_FULL_DUPLEX \
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| TBICR_SPEED1_SET \
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)
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/* Configure the TBI for SGMII operation */
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static void tsec_configure_serdes(struct tsec_private *priv)
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{
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tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_ANA,
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TBIANA_SETTINGS);
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tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_TBICON,
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TBICON_CLK_SELECT);
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tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_CR,
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TBICR_SETTINGS);
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}
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/* Discover which PHY is attached to the device, and configure it
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* properly. If the PHY is not recognized, then return 0
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@ -280,12 +299,12 @@ static int init_phy(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct phy_info *curphy;
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volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
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volatile tsec_t *phyregs = priv->phyregs;
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volatile tsec_t *regs = priv->regs;
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/* Assign a Physical address to the TBI */
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regs->tbipa = CFG_TBIPA_VALUE;
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regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
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regs->tbipa = CFG_TBIPA_VALUE;
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phyregs->tbipa = CFG_TBIPA_VALUE;
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asm("sync");
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/* Reset MII (due to new addresses) */
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@ -309,6 +328,9 @@ static int init_phy(struct eth_device *dev)
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return 0;
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}
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if (regs->ecntrl & ECNTRL_SGMII_MODE)
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tsec_configure_serdes(priv);
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priv->phyinfo = curphy;
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phy_run_commands(priv, priv->phyinfo->config);
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@ -1700,7 +1722,7 @@ static int tsec_miiphy_read(char *devname, unsigned char addr,
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return -1;
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}
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ret = (unsigned short)read_any_phy_reg(priv, addr, reg);
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ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
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*value = ret;
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return 0;
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@ -1722,7 +1744,7 @@ static int tsec_miiphy_write(char *devname, unsigned char addr,
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return -1;
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}
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write_any_phy_reg(priv, addr, reg, value);
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tsec_local_mdio_write(priv->phyregs, addr, reg, value);
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return 0;
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}
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@ -60,6 +60,27 @@
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#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
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/* TBI register addresses */
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#define TBI_CR 0x00
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#define TBI_SR 0x01
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#define TBI_ANA 0x04
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#define TBI_ANLPBPA 0x05
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#define TBI_ANEX 0x06
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#define TBI_TBICON 0x11
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/* TBI MDIO register bit fields*/
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#define TBICON_CLK_SELECT 0x0020
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_HALF_DUPLEX 0x0040
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#define TBIANA_FULL_DUPLEX 0x0020
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#define TBICR_PHY_RESET 0x8000
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#define TBICR_ANEG_ENABLE 0x1000
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#define TBICR_RESTART_ANEG 0x0200
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#define TBICR_FULL_DUPLEX 0x0100
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#define TBICR_SPEED1_SET 0x0040
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/* MAC register bits */
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#define MACCFG1_SOFT_RESET 0x80000000
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#define MACCFG1_RESET_RX_MC 0x00080000
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@ -540,7 +561,9 @@ typedef struct tsec
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/* This flag currently only has
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* meaning if we're using the eTSEC */
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#define TSEC_REDUCED (1 << 1)
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#define TSEC_REDUCED (1 << 1)
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#define TSEC_SGMII (1 << 2)
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struct tsec_private {
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volatile tsec_t *regs;
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