MPC5121: Add USB EHCI support
Signed-off-by: Francesco Rendine <francesco.rendine@valueteam.com> Signed-off-by: Damien Dusha <d.dusha@gmail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Coding style cleanup; slight file restructuring. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
This commit is contained in:
Damien Dusha
Wolfgang Denk
parent
6f119c558b
commit
29c6fbe047
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@ -1246,4 +1246,8 @@ static inline u32 get_pata_base (void)
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}
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#endif /* __ASSEMBLY__ */
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#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000
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#define CONFIG_SYS_MPC512x_USB_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
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#endif /* __IMMAP_512x__ */
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@ -53,7 +53,9 @@ DECLARE_GLOBAL_DATA_PTR;
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN | \
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CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN)
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_USB1_EN | \
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CLOCK_SCCR2_USB2_EN)
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void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
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@ -35,7 +35,11 @@ COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
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# echi
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COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
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ifdef CONFIG_MPC512X
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COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
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else
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COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
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endif
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COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
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COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
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COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
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@ -40,7 +40,7 @@ int ehci_hcd_init(void)
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{
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struct usb_ehci *ehci;
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ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
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hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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hcor = (struct ehci_hcor *)((uint32_t) hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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@ -0,0 +1,159 @@
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/*
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* (C) Copyright 2010, Damien Dusha, <d.dusha@gmail.com>
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*
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* (C) Copyright 2009, Value Team S.p.A.
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* Francesco Rendine, <francesco.rendine@valueteam.com>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
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*
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* Author: Tor Krill tor@excito.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <usb/ehci-fsl.h>
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#include "ehci.h"
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#include "ehci-core.h"
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static void fsl_setup_phy(volatile struct ehci_hcor *);
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static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
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static int reset_usb_controller(volatile struct usb_ehci *ehci);
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static void usb_platform_dr_init(volatile struct usb_ehci *ehci);
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/*
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* Initialize SOC FSL EHCI Controller
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*
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* This code is derived from EHCI FSL USB Linux driver for MPC5121
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*
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*/
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int ehci_hcd_init(void)
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{
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volatile struct usb_ehci *ehci;
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/* Hook the memory mapped registers for EHCI-Controller */
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
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hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
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hcor = (struct ehci_hcor *)((uint32_t) hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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/* configure interface for UTMI_WIDE */
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usb_platform_dr_init(ehci);
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/* Init Phy USB0 to UTMI+ */
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fsl_setup_phy(hcor);
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/* Set to host mode */
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fsl_platform_set_host_mode(ehci);
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/*
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* Setting the burst size seems to be required to prevent the
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* USB from hanging when communicating with certain USB Mass
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* storage devices. This was determined by analysing the
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* EHCI registers under Linux vs U-Boot and burstsize was the
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* major non-interrupt related difference between the two
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* implementations.
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*
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* Some USB sticks behave better than others. In particular,
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* the following USB stick is especially problematic:
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* 0930:6545 Toshiba Corp
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*
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* The burstsize is set here to match the Linux implementation.
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*/
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out_be32(&ehci->burstsize, FSL_EHCI_TXPBURST(8) |
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FSL_EHCI_RXPBURST(8));
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(void)
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{
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volatile struct usb_ehci *ehci;
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int exit_status = 0;
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if (hcor) {
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/* Unhook struct */
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hccr = NULL;
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hcor = NULL;
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/* Reset the USB controller */
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
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exit_status = reset_usb_controller(ehci);
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}
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return exit_status;
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}
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static int reset_usb_controller(volatile struct usb_ehci *ehci)
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{
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unsigned int i;
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/* Command a reset of the USB Controller */
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out_be32(&(ehci->usbcmd), EHCI_FSL_USBCMD_RST);
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/* Wait for the reset process to finish */
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for (i = 65535 ; i > 0 ; i--) {
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/*
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* The host will set this bit to zero once the
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* reset process is complete
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*/
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if ((in_be32(&(ehci->usbcmd)) & EHCI_FSL_USBCMD_RST) == 0)
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return 0;
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}
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/* Hub did not reset in time */
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return -1;
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}
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static void fsl_setup_phy(volatile struct ehci_hcor *hcor)
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{
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uint32_t portsc;
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portsc = ehci_readl(&hcor->or_portsc[0]);
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portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
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/* Enable the phy mode to UTMI Wide */
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portsc |= PORT_PTS_PTW;
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portsc |= PORT_PTS_UTMI;
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ehci_writel(&hcor->or_portsc[0], portsc);
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}
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static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci)
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{
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uint32_t temp;
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temp = in_le32(&ehci->usbmode);
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temp |= CM_HOST | ES_BE;
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out_le32(&ehci->usbmode, temp);
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}
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static void usb_platform_dr_init(volatile struct usb_ehci *ehci)
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{
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/* Configure interface for UTMI_WIDE */
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out_be32(&ehci->isiphyctrl, PHYCTRL_PHYE | PHYCTRL_PXE);
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out_be32(&ehci->usbgenctrl, GC_PPP | GC_PFP );
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}
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@ -71,6 +71,11 @@ struct ehci_hcor {
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#define STD_ASS (1 << 15)
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#define STS_HALT (1 << 12)
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uint32_t or_usbintr;
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#define INTR_UE (1 << 0) /* USB interrupt enable */
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#define INTR_UEE (1 << 1) /* USB error interrupt enable */
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#define INTR_PCE (1 << 2) /* Port change detect enable */
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#define INTR_SEE (1 << 4) /* system error enable */
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#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
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uint32_t or_frindex;
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uint32_t or_ctrldssegment;
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uint32_t or_periodiclistbase;
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@ -376,6 +376,20 @@
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#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* USB Support
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*/
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#define CONFIG_CMD_USB
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#if defined(CONFIG_CMD_USB)
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#define CONFIG_USB_EHCI /* Enable EHCI Support */
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#define CONFIG_USB_EHCI_FSL /* On a FSL platform */
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#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */
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#define CONFIG_EHCI_DESC_BIG_ENDIAN
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_STORAGE
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#endif
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/*
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* Environment
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*/
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@ -444,10 +458,15 @@
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"mpc5121.nand:-(data)"
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#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
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#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
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#define CONFIG_DOS_PARTITION
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#define CONFIG_MAC_PARTITION
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#define CONFIG_ISO_PARTITION
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#define CONFIG_CMD_FAT
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#define CONFIG_SUPPORT_VFAT
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#endif /* defined(CONFIG_CMD_IDE) */
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/*
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@ -35,12 +35,17 @@
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#define PORT_PTS_ULPI (2 << 30)
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#define PORT_PTS_SERIAL (3 << 30)
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#define PORT_PTS_PTW (1 << 28)
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#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
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#define PORT_PTS_PHCD (1 << 23)
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#define PORT_PP (1 << 12)
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#define PORT_PR (1 << 8)
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/* USBMODE Register bits */
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#define CM_IDLE (0 << 0)
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#define CM_RESERVED (1 << 0)
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#define CM_DEVICE (2 << 0)
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#define CM_HOST (3 << 0)
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#define ES_BE (1 << 2) /* Big Endian Select, default is LE */
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#define USBMODE_RESERVED_2 (0 << 2)
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#define SLOM (1 << 3)
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#define SDIS (1 << 4)
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@ -70,7 +75,78 @@
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#define PHY_CLK_VALID (1 << 17)
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#define FSL_SOC_USB_PORTSC2 0x188
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/* OTG Status Control Register bits */
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#define FSL_SOC_USB_OTGSC 0x1a4
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#define CTRL_VBUS_DISCHARGE (0x1<<0)
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#define CTRL_VBUS_CHARGE (0x1<<1)
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#define CTRL_OTG_TERMINATION (0x1<<3)
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#define CTRL_DATA_PULSING (0x1<<4)
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#define CTRL_ID_PULL_EN (0x1<<5)
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#define HA_DATA_PULSE (0x1<<6)
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#define HA_BA (0x1<<7)
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#define STS_USB_ID (0x1<<8)
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#define STS_A_VBUS_VALID (0x1<<9)
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#define STS_A_SESSION_VALID (0x1<<10)
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#define STS_B_SESSION_VALID (0x1<<11)
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#define STS_B_SESSION_END (0x1<<12)
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#define STS_1MS_TOGGLE (0x1<<13)
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#define STS_DATA_PULSING (0x1<<14)
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#define INTSTS_USB_ID (0x1<<16)
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#define INTSTS_A_VBUS_VALID (0x1<<17)
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#define INTSTS_A_SESSION_VALID (0x1<<18)
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#define INTSTS_B_SESSION_VALID (0x1<<19)
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#define INTSTS_B_SESSION_END (0x1<<20)
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#define INTSTS_1MS (0x1<<21)
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#define INTSTS_DATA_PULSING (0x1<<22)
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#define INTR_USB_ID_EN (0x1<<24)
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#define INTR_A_VBUS_VALID_EN (0x1<<25)
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#define INTR_A_SESSION_VALID_EN (0x1<<26)
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#define INTR_B_SESSION_VALID_EN (0x1<<27)
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#define INTR_B_SESSION_END_EN (0x1<<28)
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#define INTR_1MS_TIMER_EN (0x1<<29)
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#define INTR_DATA_PULSING_EN (0x1<<30)
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#define INTSTS_MASK (0x00ff0000)
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/* USBCMD Bits of interest */
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#define EHCI_FSL_USBCMD_RST (1 << 1)
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#define EHCI_FSL_USBCMD_RS (1 << 0)
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#define INTERRUPT_ENABLE_BITS_MASK \
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(INTR_USB_ID_EN | \
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INTR_1MS_TIMER_EN | \
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INTR_A_VBUS_VALID_EN | \
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INTR_A_SESSION_VALID_EN | \
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INTR_B_SESSION_VALID_EN | \
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INTR_B_SESSION_END_EN | \
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INTR_DATA_PULSING_EN)
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#define INTERRUPT_STATUS_BITS_MASK \
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(INTSTS_USB_ID | \
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INTR_1MS_TIMER_EN | \
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INTSTS_A_VBUS_VALID | \
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INTSTS_A_SESSION_VALID | \
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INTSTS_B_SESSION_VALID | \
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INTSTS_B_SESSION_END | \
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INTSTS_DATA_PULSING)
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#define FSL_SOC_USB_USBMODE 0x1a8
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#define USBGENCTRL 0x200 /* NOTE: big endian */
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#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
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#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
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#define GC_PPP (1 << 3) /* Port Power Polarity */
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#define GC_PFP (1 << 2) /* Power Fault Polarity */
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#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
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#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
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#define ISIPHYCTRL 0x204 /* NOTE: big endian */
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#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
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#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
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#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
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#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
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#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
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#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
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#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
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#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
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@ -85,65 +161,85 @@
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#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
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#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
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#if defined(CONFIG_MPC83xx)
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#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
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#if defined(CONFIG_MPC83XX)
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#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
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#elif defined(CONFIG_MPC85xx)
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#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
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#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
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#elif defined(CONFIG_MPC512X)
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#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
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#endif
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/*
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* USB Registers
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*/
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struct usb_ehci {
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u8 res1[0x100];
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u32 id; /* 0x000 - Identification register */
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u32 hwgeneral; /* 0x004 - General hardware parameters */
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u32 hwhost; /* 0x008 - Host hardware parameters */
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u32 hwdevice; /* 0x00C - Device hardware parameters */
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u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
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u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
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u8 res1[0x68];
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u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
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u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
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u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
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u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
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u32 sbuscfg; /* 0x090 - System Bus Interface Control */
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u8 res2[0x6C];
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u16 caplength; /* 0x100 - Capability Register Length */
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u16 hciversion; /* 0x102 - Host Interface Version */
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u32 hcsparams; /* 0x104 - Host Structural Parameters */
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u32 hccparams; /* 0x108 - Host Capability Parameters */
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u8 res2[0x14];
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u8 res3[0x14];
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u32 dciversion; /* 0x120 - Device Interface Version */
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u32 dciparams; /* 0x124 - Device Controller Params */
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u8 res3[0x18];
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u8 res4[0x18];
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u32 usbcmd; /* 0x140 - USB Command */
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u32 usbsts; /* 0x144 - USB Status */
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u32 usbintr; /* 0x148 - USB Interrupt Enable */
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u32 frindex; /* 0x14C - USB Frame Index */
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u8 res4[0x4];
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u8 res5[0x4];
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u32 perlistbase; /* 0x154 - Periodic List Base
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- USB Device Address */
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u32 ep_list_addr; /* 0x158 - Next Asynchronous List
|
||||
- Endpoint Address */
|
||||
u8 res5[0x4];
|
||||
- End Point Address */
|
||||
u8 res6[0x4];
|
||||
u32 burstsize; /* 0x160 - Programmable Burst Size */
|
||||
#define FSL_EHCI_TXPBURST(X) ((X) << 8)
|
||||
#define FSL_EHCI_RXPBURST(X) (X)
|
||||
u32 txfilltuning; /* 0x164 - Host TT Transmit
|
||||
pre-buffer packet tuning */
|
||||
u8 res6[0x8];
|
||||
u8 res7[0x8];
|
||||
u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
|
||||
u8 res7[0xc];
|
||||
u8 res8[0xc];
|
||||
u32 config_flag; /* 0x180 - Configured Flag Register */
|
||||
u32 portsc; /* 0x184 - Port status/control */
|
||||
u8 res8[0x20];
|
||||
u8 res9[0x1C];
|
||||
u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
|
||||
u32 usbmode; /* 0x1a8 - USB Device Mode */
|
||||
u32 epsetupstat; /* 0x1ac - Endpoint Setup Status */
|
||||
u32 epprime; /* 0x1b0 - Endpoint Init Status */
|
||||
u32 epflush; /* 0x1b4 - Endpoint De-initlialize */
|
||||
u32 epstatus; /* 0x1b8 - Endpoint Status */
|
||||
u32 epcomplete; /* 0x1bc - Endpoint Complete */
|
||||
u32 epctrl0; /* 0x1c0 - Endpoint Control 0 */
|
||||
u32 epctrl1; /* 0x1c4 - Endpoint Control 1 */
|
||||
u32 epctrl2; /* 0x1c8 - Endpoint Control 2 */
|
||||
u32 epctrl3; /* 0x1cc - Endpoint Control 3 */
|
||||
u32 epctrl4; /* 0x1d0 - Endpoint Control 4 */
|
||||
u32 epctrl5; /* 0x1d4 - Endpoint Control 5 */
|
||||
u8 res9[0x228];
|
||||
u32 epsetupstat; /* 0x1ac - End Point Setup Status */
|
||||
u32 epprime; /* 0x1b0 - End Point Init Status */
|
||||
u32 epflush; /* 0x1b4 - End Point De-initlialize */
|
||||
u32 epstatus; /* 0x1b8 - End Point Status */
|
||||
u32 epcomplete; /* 0x1bc - End Point Complete */
|
||||
u32 epctrl0; /* 0x1c0 - End Point Control 0 */
|
||||
u32 epctrl1; /* 0x1c4 - End Point Control 1 */
|
||||
u32 epctrl2; /* 0x1c8 - End Point Control 2 */
|
||||
u32 epctrl3; /* 0x1cc - End Point Control 3 */
|
||||
u32 epctrl4; /* 0x1d0 - End Point Control 4 */
|
||||
u32 epctrl5; /* 0x1d4 - End Point Control 5 */
|
||||
u8 res10[0x28];
|
||||
u32 usbgenctrl; /* 0x200 - USB General Control */
|
||||
u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
|
||||
u8 res11[0x1F8];
|
||||
u32 snoop1; /* 0x400 - Snoop 1 */
|
||||
u32 snoop2; /* 0x404 - Snoop 2 */
|
||||
u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
|
||||
u32 prictrl; /* 0x40c - Priority Control */
|
||||
u32 sictrl; /* 0x410 - System Interface Control */
|
||||
u8 res10[0xEC];
|
||||
u8 res12[0xEC];
|
||||
u32 control; /* 0x500 - Control */
|
||||
u8 res11[0xafc];
|
||||
u8 res13[0xafc];
|
||||
};
|
||||
|
||||
#endif /* _EHCI_FSL_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue