ids8247: Remove legacy NAND defines
because legacy NAND support is deprecated converting to current NAND interface. !This just compile, because I have no more the hardware to test it. Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
Wolfgang Denk
parent
dbd3361440
commit
28afe0160f
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@ -304,21 +304,97 @@ phys_size_t initdram (int board_type)
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int misc_init_r (void)
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{
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gd->bd->bi_flashstart = 0xff800000;
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return 0;
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}
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#if defined(CONFIG_CMD_NAND)
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extern ulong
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nand_probe (ulong physadr);
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#include <nand.h>
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#include <linux/mtd/mtd.h>
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#include <asm/io.h>
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void
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nand_init (void)
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static u8 hwctl;
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static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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ulong totlen = 0;
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struct nand_chip *this = mtd->priv;
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debug ("Probing at 0x%.8x\n", CONFIG_SYS_NAND0_BASE);
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totlen += nand_probe (CONFIG_SYS_NAND0_BASE);
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if (ctrl & NAND_CTRL_CHANGE) {
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if ( ctrl & NAND_CLE ) {
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hwctl |= 0x1;
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writeb(0x00, (this->IO_ADDR_W + 0x0a));
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} else {
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hwctl &= ~0x1;
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writeb(0x00, (this->IO_ADDR_W + 0x08));
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}
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if ( ctrl & NAND_ALE ) {
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hwctl |= 0x2;
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writeb(0x00, (this->IO_ADDR_W + 0x09));
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} else {
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hwctl &= ~0x2;
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writeb(0x00, (this->IO_ADDR_W + 0x08));
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}
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if ( (ctrl & NAND_NCE) != NAND_NCE)
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writeb(0x00, (this->IO_ADDR_W + 0x0c));
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else
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writeb(0x00, (this->IO_ADDR_W + 0x08));
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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printf ("%4lu MB\n", totlen >>20);
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}
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static u_char ids_nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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return readb(this->IO_ADDR_R);
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}
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static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct nand_chip *nand = mtd->priv;
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int i;
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for (i = 0; i < len; i++) {
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if (hwctl & 0x1)
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writeb(buf[i], (nand->IO_ADDR_W + 0x02));
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else if (hwctl & 0x2)
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writeb(buf[i], (nand->IO_ADDR_W + 0x01));
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else
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writeb(buf[i], nand->IO_ADDR_W);
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}
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}
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static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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int i;
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for (i = 0; i < len; i++) {
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buf[i] = readb(this->IO_ADDR_R);
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}
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}
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static int ids_nand_dev_ready(struct mtd_info *mtd)
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{
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/* constant delay (see also tR in the datasheet) */
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udelay(12);
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return 1;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->ecc.mode = NAND_ECC_SOFT;
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/* Reference hardware control function */
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nand->cmd_ctrl = ids_nand_hwctrl;
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nand->read_byte = ids_nand_read_byte;
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nand->write_buf = ids_nand_write_buf;
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nand->read_buf = ids_nand_read_buf;
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nand->dev_ready = ids_nand_dev_ready;
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nand->chip_delay = 12;
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return 0;
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}
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#endif /* CONFIG_CMD_NAND */
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@ -262,63 +262,8 @@
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*/
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_NAND_LEGACY
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#define CONFIG_SYS_NAND0_BASE 0xE1000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define NAND_NO_RB
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_DISABLE_CE(nand) do \
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{ \
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*(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
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} while(0)
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#define NAND_ENABLE_CE(nand) do \
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{ \
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*(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
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} while(0)
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#define NAND_CTL_CLRALE(nandptr) do \
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{ \
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*(((volatile __u8 *)nandptr) + 0x8) = 0; \
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} while(0)
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#define NAND_CTL_SETALE(nandptr) do \
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{ \
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*(((volatile __u8 *)nandptr) + 0x9) = 0; \
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} while(0)
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#define NAND_CTL_CLRCLE(nandptr) do \
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{ \
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*(((volatile __u8 *)nandptr) + 0x8) = 0; \
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} while(0)
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#define NAND_CTL_SETCLE(nandptr) do \
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{ \
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*(((volatile __u8 *)nandptr) + 0xa) = 0; \
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} while(0)
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#ifdef NAND_NO_RB
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/* constant delay (see also tR in the datasheet) */
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#define NAND_WAIT_READY(nand) do { \
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udelay(12); \
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} while (0)
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#else
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/* use the R/B pin */
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#endif
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#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
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#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
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#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
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#endif /* CONFIG_CMD_NAND */
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