Adding fixed sdram setting for cornet_ds board
800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram setting. SPD based parameters and fixed parameters can be toggled by hwconfig. To use fixed parameters, hwconfig=fsl_ddr:sdram=fixed To use SPD parameters, hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
York Sun
Kumar Gala
parent
84bc00300f
commit
28a966715b
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@ -213,4 +213,10 @@ typedef struct memctl_options_s {
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} memctl_options_t;
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extern phys_size_t fsl_ddr_sdram(void);
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typedef struct fixed_ddr_parm{
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int min_freq;
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int max_freq;
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fsl_ddr_cfg_regs_t *ddr_settings;
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} fixed_ddr_parm_t;
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#endif
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@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-$(CONFIG_DDR_SPD) += ddr.o
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COBJS-y += ddr.o
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COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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@ -29,7 +29,6 @@
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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@ -196,20 +195,6 @@ int misc_init_r(void)
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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puts("Initializing....\n");
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dram_size = fsl_ddr_sdram();
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setup_ddr_tlbs(dram_size / 0x100000);
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puts(" DDR: ");
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return dram_size;
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}
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#ifdef CONFIG_MP
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void board_lmb_reserve(struct lmb *lmb)
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{
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@ -8,9 +8,103 @@
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num);
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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extern fixed_ddr_parm_t fixed_ddr_parm_0[];
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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extern fixed_ddr_parm_t fixed_ddr_parm_1[];
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#endif
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phys_size_t fixed_sdram(void)
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{
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int i;
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sys_info_t sysinfo;
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char buf[32];
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fsl_ddr_cfg_regs_t ddr_cfg_regs;
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phys_size_t ddr_size;
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unsigned int lawbar1_target_id;
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get_sys_info(&sysinfo);
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
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if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
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(sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
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memcpy(&ddr_cfg_regs,
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fixed_ddr_parm_0[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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break;
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}
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}
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if (fixed_ddr_parm_0[i].max_freq == 0)
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panic("Unsupported DDR data rate %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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memcpy(&ddr_cfg_regs,
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fixed_ddr_parm_1[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
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#endif
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/*
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* setup laws for DDR. If not interleaving, presuming half memory on
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* DDR1 and the other half on DDR2
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*/
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if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size,
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LAW_TRGT_IF_DDR_INTRLV) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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} else {
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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/* We require both controllers have identical DIMMs */
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lawbar1_target_id = LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size / 2,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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lawbar1_target_id = LAW_TRGT_IF_DDR_2;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
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ddr_size / 2,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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#else
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lawbar1_target_id = LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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#endif
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}
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return ddr_size;
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}
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static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
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{
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@ -190,3 +284,38 @@ void fsl_ddr_board_options(memctl_options_t *popts,
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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int use_spd = 0;
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puts("Initializing....");
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#ifdef CONFIG_DDR_SPD
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/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
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if (hwconfig_sub("fsl_ddr", "sdram")) {
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if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
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use_spd = 1;
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else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
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use_spd = 0;
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else
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use_spd = 1;
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} else
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use_spd = 1;
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#endif
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if (use_spd) {
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puts("using SPD\n");
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dram_size = fsl_ddr_sdram();
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} else {
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puts("using fixed parameters\n");
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dram_size = fixed_sdram();
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}
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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@ -0,0 +1,356 @@
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/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#define DATARATE_800MHZ 800000000
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#define DATARATE_900MHZ 900000000
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#define DATARATE_1000MHZ 1000000000
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#define DATARATE_1200MHZ 1200000000
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#define DATARATE_1300MHZ 1300000000
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#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
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#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
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#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
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#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
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#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
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#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
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#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
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#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
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#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
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#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
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#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
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#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
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#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
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#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
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#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
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#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
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#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
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#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
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#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
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#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
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#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
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#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
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#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
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#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
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#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
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#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
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#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
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#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
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#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
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#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
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#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
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#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
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#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
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#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
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#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
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#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
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#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
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#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
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#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
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#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_TIMING_4 0x00000001
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#define CONFIG_SYS_DDR_TIMING_5 0x02401400
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
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#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
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.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
|
||||
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
|
||||
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
|
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
|
||||
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
|
||||
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
|
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
|
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
|
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
|
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
|
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
|
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
|
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
|
||||
};
|
||||
|
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
|
||||
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
|
||||
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
|
||||
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
|
||||
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
|
||||
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
|
||||
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
|
||||
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
|
||||
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
|
||||
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
|
||||
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
|
||||
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
|
||||
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
|
||||
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
|
||||
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
|
||||
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
|
||||
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
|
||||
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
|
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
|
||||
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
|
||||
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
|
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
|
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
|
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
|
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
|
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
|
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
|
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
|
||||
};
|
||||
|
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
|
||||
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
|
||||
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
|
||||
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
|
||||
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
|
||||
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
|
||||
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
|
||||
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
|
||||
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
|
||||
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
|
||||
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
|
||||
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
|
||||
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
|
||||
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
|
||||
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
|
||||
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
|
||||
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
|
||||
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
|
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
|
||||
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
|
||||
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
|
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
|
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
|
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
|
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
|
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
|
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
|
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
|
||||
};
|
||||
|
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
|
||||
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
|
||||
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
|
||||
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
|
||||
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
|
||||
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
|
||||
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
|
||||
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
|
||||
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
|
||||
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
|
||||
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
|
||||
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
|
||||
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
|
||||
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
|
||||
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
|
||||
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
|
||||
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
|
||||
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
|
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
|
||||
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
|
||||
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
|
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
|
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
|
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
|
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
|
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
|
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
|
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
|
||||
};
|
||||
|
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
|
||||
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
|
||||
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
|
||||
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
|
||||
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
|
||||
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
|
||||
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
|
||||
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
|
||||
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
|
||||
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
|
||||
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
|
||||
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
|
||||
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
|
||||
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
|
||||
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
|
||||
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
|
||||
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
|
||||
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
|
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
|
||||
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
|
||||
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
|
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
|
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
|
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
|
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
|
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
|
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
|
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
|
||||
};
|
||||
|
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
|
||||
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
|
||||
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
|
||||
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
|
||||
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
|
||||
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
|
||||
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
|
||||
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
|
||||
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
|
||||
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
|
||||
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
|
||||
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
|
||||
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
|
||||
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
|
||||
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
|
||||
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
|
||||
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
|
||||
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
|
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
|
||||
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
|
||||
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
|
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
|
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
|
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
|
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
|
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
|
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
|
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
|
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
|
||||
};
|
||||
|
||||
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
|
||||
{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
|
||||
{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
|
||||
{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
|
||||
{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
|
||||
{0, 0, NULL}
|
||||
};
|
||||
|
||||
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
|
||||
{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
|
||||
{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
|
||||
{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
|
||||
{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},
|
||||
{0, 0, NULL}
|
||||
};
|
||||
|
|
@ -130,68 +130,10 @@
|
|||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_FSL_DDR3
|
||||
|
||||
#ifdef CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1
|
||||
#define SPD_EEPROM_ADDRESS1 0x51
|
||||
#define SPD_EEPROM_ADDRESS2 0x52
|
||||
#else
|
||||
#define CONFIG_SYS_SDRAM_SIZE 4096
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
|
||||
#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
|
||||
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x01031000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x55440804
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x74713a66
|
||||
#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b
|
||||
#define CONFIG_SYS_DDR_MODE_1 0x00421850
|
||||
#define CONFIG_SYS_DDR_MODE_2 0x00100000
|
||||
#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
|
||||
#define CONFIG_SYS_DDR_INTERVAL 0x10400100
|
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
|
||||
#define CONFIG_SYS_DDR_TIMING_4 0x00220001
|
||||
#define CONFIG_SYS_DDR_TIMING_5 0x03401500
|
||||
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
|
||||
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xc7048000
|
||||
#define CONFIG_SYS_DDR_CONTROL2 0x24400011
|
||||
#define CONFIG_SYS_DDR_CDR1 0x00000000
|
||||
#define CONFIG_SYS_DDR_CDR2 0x00000000
|
||||
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
|
||||
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
|
||||
#define CONFIG_SYS_DDR_SBE 0x00010000
|
||||
#define CONFIG_SYS_DDR_DEBUG_18 0x40100400
|
||||
|
||||
#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf
|
||||
#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff
|
||||
#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
|
||||
#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG
|
||||
#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3
|
||||
#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0
|
||||
#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1
|
||||
#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2
|
||||
#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1
|
||||
#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2
|
||||
#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL
|
||||
#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL
|
||||
#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT
|
||||
#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL
|
||||
#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4
|
||||
#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5
|
||||
#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL
|
||||
#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL
|
||||
#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL
|
||||
#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2
|
||||
#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1
|
||||
#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2
|
||||
#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN
|
||||
#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS
|
||||
#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE
|
||||
#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18
|
||||
|
||||
#endif
|
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
|
|
|
|||
Loading…
Reference in New Issue