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Merge branch 'wd'

This commit is contained in:
Jon Loeliger 2006-08-09 13:36:54 -05:00
parent 870cbeaa45 6587f7e1e9
commit 281f69ede2
248 changed files with 24221 additions and 6667 deletions
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308
CHANGELOG
View File

@ -2,6 +2,314 @@
Changes since U-Boot 1.1.4:
======================================================================
* Prevent USB commands from working when USB is stopped.
* Add rudimentary handling of alternate settings of USB interfaces.
This is in order to fix issues with some USB sticks timing out
during initialization. Some code readability improvements.
* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
Please see doc/README.bamboo for details.
Patch by Stefan Roese, 27 Jul 2006
* Fix CONFIG_CMDLINE_EDITING implementation
Patch by Stefan Roese, 27 Jul 2006
* Fix preboot message on TQM5200 after switching to hush parser.
* MCC200: set default configuration to low_boot DDR,
and support for configurable options high_boot and/or SDRAM.
* Add support for 256 MB SDRAM on CPU87
Patch by Josef Wagner, 25 Nov 2005
* Add configuration for cam5200 board (based on TQM5200S).
* More code cleanup
* Disabled kvme080 board in MAKEALL because of build problems.
* Code cleanup
* Update NetStar board
Patch by Ladislav Michl, 03 Nov 2005
* Make code better readable.
Patch by Ladislav Michl, 14 Sep 2005
* Enable initrd ATAG for xm250 board.
Patch by Josef Wagner, 05 Sep 2005
* Add readline cmdline-editing extension
Patch by JinHua Luo, 01 Sep 2005
* Add support for friendly-arm SBC-2410X board
Patch by JinHua Luo, 01 Sep 2005
* Fix multi-part image support on i386 platform.
Patch by David Updegraff, 19 Aug 2005
* Add support for KVME080 board
Patch by Sangmoon Kim, 18 Aug 2005
* Fix MIPS LE build problem
Patch by Matej Kupljen, 10 Aug 2005
* Check argument count in "mii" command.
Problem pointed out by Andrew Dyer, 13 Jun 2005
* Cleanup TQM5200 board configurations:
- make highboot configurations use environment at high end, too,
to avoid flash fragmentation
- always use redundand environment
- don't enable video code for modules without graphics controller
- provide useful (though different) mtdparts settings
- get rid of CONFIG_CS_AUTOCONF which was always set anyway
* Extend mkconfig tool to print more useful target name
* Add support for high-boot on TQM5200 and TQM5200S boards.
Hint: the CPLD on the TQM5200 must be programmed with a software
version supporting the high boot option! The new TQM5200S is
already supporting this option. On the TQM5200 this option will be
supported in configurations with MPC5200 rev B processors.
To actually "high boot", set jumper X30 on the STK52xx.
Patch by Martin Krause, 12 Jul 2006
* Add support for new TQM5200 revisions
- Support for TQM5200S (short version without graphic controller)
- Support for modules with 'N' type S29GL128N Spansion flashes
(requires changes to flash layout)
- Support for MPC5200B cpu (mostly support for second SDRAM bank)
Patch by Martin Krause, 07 Jul 2006
* Fix support for PS/2 keyboard on TQM85xx boards
The PS/2 keyobard driver for the TQM85xx modules only supports the
internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
include a DUART, the TQM8560 modules can't be used with the PS/2
keyboard controller on the STK85xx board.
The PS/2 keyboard driver should work with the modules TQM8540,
TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
Make sure the PS/2 controller on the STK85xx is programmed. Jumper
settings: X66 1-2, 9-10; X61 2-3
Patch by Martin Krause, 21 Jun 2006
* Adjust RTC century handling on STK52xx board to match Linux driver.
Patch by Martin Krause, 12 Jun 2006
* Adjust filenames for USB update images on TRAB board.
During an automatic update via USB stick, U-Boot searches for
images with the name "firmware.img" and "kernel.img". This names
are now changed to "firmw_01.img" and "kernl_01.img". This is done,
to prevent updates of new boards (with the new macronics "c" step
flashes) with old, incompatible firmware or kernel versions.
Patch by Martin Krause, 21 Jun 2006
* Bugfix in VFD routine on TRAB board.
Make sure upper lext pixel can be set to blue, too
(so far only red was possible).
Patch by Martin Krause, 15 Feb 2006
* Enable buffered flash writes for TB5200 board.
* Fix some bugs in TRAB board flash driver.
- increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
- use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
- remove "Unlock Bypass" mode, because macronix flashes do not support
this mode officially
- fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
for Intel compatible flashes, not for AMD compatible.
Patch by Martin Krause, 15 Feb 2006
* Add additional error messages to flash driver on TRAB board
(for erase errors and timeout errors)
Patch by Martin Krause, 14 Feb 2006
* Add support for TB5200 board
The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006
* Enable buffered flash writes for TQM5200 board.
* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick.
* Add support for TQM885D board.
Patch by Martin Krause, 20 Mar 2006
* Fix FEC initialisation: All MII configuration is done via FEC1
registers, but MII_SPEED was configured according to FEC used. So
if only FEC2 was used, this caused the real MII_SPEED register in
FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages.
Fix: always configure MII_SPEED on FEC1 only.
Patch by Markus Klotzbuecher, 12 Jul 2006
* Add support for SPC1920 board.
Patch by Markus Klotzbuecher, 12 Jul 2006
* MCC200 board: support console on any one of the Quad UART ports.
* Fix error in flash protection calculation on MCC200 board.
* Major PCMCIA Cleanup to make code better readable and maintainable.
Notes:
- Board-dependend code for RPXLITE and RPXCLASSIC-based boards
placed to the drivers/rpx_pmcia.c file to avoid duplication.
Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
- drivers/i82365.c has been split into two parts located at
board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
the only boards using CONFIG_82365).
- Changes were tested for clean build and *very* *few* boards.
* Fix timer problems on AMCC yucca board.
Set Timer Clock Select to use CPU clock as a timer input source.
* Bring yucca config more in line with other AMCC boards.
* Add AMCC bamboo board to MAKEALL build script.
* Fix AMCC bamboo eval board compilation errors.
* Add system memory to the PCI region list for AMCC PPC44x CPUs.
Enabled it for Yucca board.
* Cleanup config file and bootup output for Yucca board.
* Fix CONFIG_440_GX define usage.
* Remove autogenerated bmp_logo.h file.
* Add support for AMCC 440SPe CPU based eval board (Yucca).
* Call serial_initialize() before first debug() is used.
* Cleanup trab board for GCC-4.x
* VoiceBlue update: use new MTD flash partitioning methods, use more
reasonable TEXT_BASE, update default environment and enable keyed
autoboot.
Patch by Ladislav Michl, 16. Aug 2005
* Add forgotten changes for the PLEB 2 Board.
Patch by David Snowdon, 13. Aug 2005
* Add support for wrPPMC7xx/74xx boards
Patch by Richard Danter, 12 Aug 2005
* Add support for gth2 board
Patch by Thomas Lange, Aug 11 2005
* Add support for CONFIG_SERIAL_MULTI on MPC5xxx
Patch by Martin Krause, 8 Jun 2006
This patch supports two serial consoles on boards with
a MPC5xxx CPU. The console can be switched at runtime
by setting stdin, stdout and stderr to the desired serial
interface (serial0 or serial1). The PSCs to be used as
console port are definded by CONFIG_PSC_CONSOLE
and CONFIG_PSC_CONSOLE2.
See README.serial_multi for details.
* Bugfix in I2C initialisation on S3C2400.
If the bus is blocked because of a previously interrupted
transfer, up to eleven clocks are generated on the I2CSCL
line to complete the transfer and to free the bus.
With this fix pin I2CSCL (PG6) is really configured as GPIO
so the clock pulses are really generated.
Patch by Martin Krause, 04 Apr 2006
* Fix DDR6 errata on TQM834x boards
Patch by Thomas Waehner, 07 Mar 2006
* Remove obsolete flash driver board/tqm5200/flash.c
Patch by Martin Krause, 11 Jan 2006
* Update configuration for CMC-PU2 board
Patch by Martin Krause, 17 Nov 2005
* Add support for PS/2 keyboard on TQM85xx board
Patch by Martin Krause, 07 Nov 2005
Tested on a STK85XX baseboard. Make sure the PS/2 controller
has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
In tsc2000_read_channel() the delay after setting the multiplexer
to a temperature channel is increased from 1,5 ms to 10 ms. This
is to allow the multiplexer inputs to stabilize after huge steps
of the input signal level.
Patch by Martin Krause, 08 Nov 2005
* Adjust TQM5200 make targets
Make the automatic CS configuration the default.
The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
and CONFIG_TQM5200_AC are removed.
"TQM5200_config" is now the default for STK52XX.200 base boards.
On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
Patch by Martin Krause, 07 Nov 2005
* Fix setting of environment variable "ver" on trab board
The environment variable "ver" is now set before
do_auto_update() is called, so that "ver" can be used
in USB update scripts.
Patch by Martin Krause, 27 Oct 2005
* Fix wrong usage of udelay() in led_blink() on trab board
Patch by Martin Krause, 27 Oct 2005
* Fix udelay bug in vfd.c for trab board
Patch by Martin Krause, 27 Oct 2005
* Disable JFFS2 support for trab board
Patch by Martin Krause, 27 Oct 2005
* Change mtdparts definition on trab board to match current flash map
Patch by Martin Krause, 27 Oct 2005
* Fix memory init problems on MCC200 board
* Fix IxEthDB.h to compile again
Patch by Stefan Roese, 14 Jun 2006
* Minor cleanup for PCS440EP board
Patch by Stefan Roese, 13 Jun 2006
* Add MCF5282 support (without preloader)
relocate ichache_State to ram
u-boot can run from internal flash
Add EB+MCF-EV123 board support.
Add m68k Boards to MAKEALL
Patch from Jens Scharsig, 08 Aug 2005
* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards
Patch by Scott McNutt, 08 Jun 2006
* Nios II - Add EPCS Controller bootrom work-around
-When booting from an epcs controller, the epcs bootrom may leave the
slave select in an asserted state causing soft reset hang. This
patch ensures slave select is negated at reset.
Patch by Scott McNutt, 08 Jun 2006
* Update PK1C20 board
-Update base addresses for standard configuration
-Eliminate use of CACHE_BYPASS in board code
Patch by Scott McNutt, 08 Jun 2006
* Nios II - Fix I/O Macros and mini-app stubs
-Fix asm/io.h macros
-Eliminate use of CACHE_BYPASS in cpu code
-Eliminate assembler warnings
-Fix mini-app stubs and force no small data
Patch by Scott McNutt, 08 Jun 2006
* Fix U-Boot environment sector protection on MCC200 board
* Minor cleanup for PCS440EP board
* Update PCS440EP port to fit into one flash device (incl. environment)

7
CREDITS
View File

@ -105,6 +105,10 @@ N: Magnus Damm
E: damm@opensource.se
D: 8xxrom
N: Richard Danter
E: richard.danter@windriver.com
D: Support for Wind River PPMC 7xx/74xx boards
N: George G. Davis
E: gdavis@mvista.com
D: Board ports for ADS GraphicsClient+ and Intel Assabet
@ -229,6 +233,7 @@ D: Port to Windriver ppmc8260 board
N: Sangmoon Kim
E: dogoil@etinsys.com
D: Support for debris board
D: Support for KVME080 board
N: Frederick W. Klatt
E: fred.klatt@windriver.com
@ -253,7 +258,7 @@ D Support for Intrinsyc CERF PXA250 board.
N: Thomas Lange
E: thomas@corelatus.se
D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
N: Marc Leeman
E: marc.leeman@barco.com

5
MAINTAINERS
View File

@ -197,6 +197,7 @@ Brad Kemp <Brad.Kemp@seranoa.com>
Sangmoon Kim <dogoil@etinsys.com>
debris MPC8245
KVME080 MPC8245
Thomas Lange <thomas@corelatus.se>
@ -489,6 +490,7 @@ Wolfgang Denk <wd@denx.de>
Thomas Lange <thomas@corelatus.se>
dbau1x00 MIPS32 Au1000
gth2 MIPS32 Au1000
#########################################################################
# Nios-32 Systems: #
@ -517,6 +519,9 @@ Scott McNutt <smcnutt@psyent.com>
PCI5441 Nios-II
PK1C20 Nios-II
EP1C20 Nios-II
EP1S10 Nios-II
EP1S40 Nios-II
#########################################################################
# MicroBlaze Systems: #

78
MAKEALL
View File

@ -27,14 +27,14 @@ LIST_5xx=" \
LIST_5xxx=" \
BC3450 cpci5200 EVAL5200 icecube_5100 \
icecube_5200 lite5200b mcc200 o2dnt \
pf5200 PM520 Total5100 Total5200 \
Total5200_Rev2 TQM5200_auto \
pf5200 PM520 TB5200 Total5100 \
Total5200 Total5200_Rev2 TQM5200 TQM5200_B \
TQM5200S \
"
#########################################################################
## MPC8xx Systems
#########################################################################
LIST_8xx=" \
Adder87x GENIETV MBX860T R360MPI \
AdderII GTH MHPC RBC823 \
@ -44,16 +44,18 @@ LIST_8xx=" \
CCM IP860 NETPHONE RPXlite_DW \
cogent_mpc8xx IVML24 NETTA RRvision \
ELPT860 IVML24_128 NETTA2 SM850 \
EP88x IVML24_256 NETTA_ISDN SPD823TS \
ESTEEM192E IVMS8 NETVIA svm_sc8xx \
ETX094 IVMS8_128 NETVIA_V2 SXNI855T \
FADS823 IVMS8_256 NX823 TOP860 \
FADS850SAR KUP4K pcu_e TQM823L \
FADS860T KUP4X QS823 TQM823L_LCD \
FLAGADM LANTEC QS850 TQM850L \
FPS850L lwmon QS860T TQM855L \
GEN860T MBX quantum TQM860L \
GEN860T_SC uc100 \
EP88x IVML24_256 NETTA_ISDN spc1920 \
ESTEEM192E IVMS8 NETVIA SPD823TS \
ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \
FADS823 IVMS8_256 NX823 SXNI855T \
FADS850SAR KUP4K pcu_e TOP860 \
FADS860T KUP4X QS823 TQM823L \
FLAGADM LANTEC QS850 TQM823L_LCD \
FPS850L lwmon QS860T TQM850L \
GEN860T MBX quantum TQM855L \
GEN860T_SC TQM860L \
TQM885D \
uc100 \
v37 \
"
@ -72,10 +74,10 @@ LIST_4xx=" \
luan METROBOX MIP405 MIP405T \
ML2 ml300 ocotea OCRTC \
ORSG p3p440 PCI405 pcs440ep \
PIP405 PLU405 PMC405 PPChameleonEVB \
sbc405 VOH405 VOM405 W7OLMC \
PIP405 PLU405 PMC405 PPChameleonEVB \
sbc405 VOH405 VOM405 W7OLMC \
W7OLMG walnut WUH405 XPEDITE1K \
yellowstone yosemite \
yellowstone yosemite yucca bamboo \
"
#########################################################################
@ -93,9 +95,9 @@ LIST_8220=" \
LIST_824x=" \
A3000 barco BMW CPC45 \
CU824 debris eXalion HIDDEN_DRAGON \
MOUSSE MUSENKI MVBLUE OXC \
PN62 Sandpoint8240 Sandpoint8245 sbc8240 \
SL8245 utx8245 \
MOUSSE MUSENKI MVBLUE \
OXC PN62 Sandpoint8240 Sandpoint8245 \
sbc8240 SL8245 utx8245 \
"
#########################################################################
@ -142,7 +144,7 @@ LIST_74xx=" \
"
LIST_7xx=" \
BAB7xx CPCI750 ELPPC \
BAB7xx CPCI750 ELPPC ppmc7xx \
"
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
@ -179,9 +181,10 @@ LIST_ARM9=" \
ap966 cp920t cp922_XA10 cp926ejs \
cp946es cp966 lpd7a400 mp2usb \
mx1ads mx1fs2 netstar omap1510inn \
omap1610h2 omap1610inn omap730p2 scb9328 \
smdk2400 smdk2410 trab VCMA9 \
versatile versatileab versatilepb voiceblue
omap1610h2 omap1610inn omap730p2 sbc2410x \
scb9328 smdk2400 smdk2410 trab \
VCMA9 versatile versatileab versatilepb \
voiceblue \
"
#########################################################################
@ -204,9 +207,9 @@ LIST_ARM11=" \
LIST_pxa=" \
adsvix cerf250 cradle csb226 \
delta innokom lubbock pxa255_idp \
wepep250 xaeniax xm250 xsengine \
zylonite \
delta innokom lubbock pleb2 \
pxa255_idp wepep250 xaeniax xm250 \
xsengine zylonite \
"
LIST_ixp="ixdp425 ixdpg425 pdnb3"
@ -226,7 +229,7 @@ LIST_mips4kc="incaip"
LIST_mips5kc="purple"
LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2"
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
@ -255,29 +258,38 @@ LIST_x86="${LIST_I486}"
#########################################################################
LIST_nios=" \
ADNPESC1 ADNPESC1_base_32 \
ADNPESC1 ADNPESC1_base_32 \
ADNPESC1_DNPEVA2_base_32 \
DK1C20 DK1C20_standard_32 \
DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
DK1C20 DK1C20_standard_32 \
DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
"
#########################################################################
## Nios-II Systems
#########################################################################
LIST_nios2="PCI5441 PK1C20"
LIST_nios2=" \
EP1C20 EP1S10 EP1S40 \
PCI5441 PK1C20 \
"
#########################################################################
## MicroBlaze Systems
#########################################################################
LIST_microblaze="suzaku"
LIST_microblaze=" \
suzaku
"
#########################################################################
## ColdFire Systems
#########################################################################
LIST_coldfire="cobra5272 M5272C3 M5282EVB TASREG r5200 M5271EVB"
LIST_coldfire=" \
cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \
M5271EVB M5272C3 M5282EVB TASREG \
r5200 M5271EVB \
"
#-----------------------------------------------------------------------

133
Makefile
View File

@ -7,7 +7,7 @@
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
@ -326,13 +326,25 @@ lite5200b_LOWBOOT_config: unconfig
@./mkconfig -a IceCube ppc mpc5xxx icecube
mcc200_config \
mcc200_lowboot_config: unconfig
mcc200_SDRAM \
mcc200_highboot \
mcc200_highboot_SDRAM: unconfig
@ >include/config.h
@[ -z "$(findstring lowboot_,$@)" ] || \
{ echo "TEXT_BASE = 0xFC000000" >board/mcc200/config.tmp ; \
echo "... with lowboot configuration" ; \
@[ -n "$(findstring highboot,$@)" ] || \
{ echo "... with lowboot configuration" ; \
}
@./mkconfig mcc200 ppc mpc5xxx mcc200
@[ -z "$(findstring highboot,$@)" ] || \
{ echo "TEXT_BASE = 0xFFF00000" >board/mcc200/config.tmp ; \
echo "... with highboot configuration" ; \
}
@[ -n "$(findstring _SDRAM,$@)" ] || \
{ echo "... with DDR" ; \
}
@[ -z "$(findstring _SDRAM,$@)" ] || \
{ echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \
echo "... with SDRAM" ; \
}
@./mkconfig -a mcc200 ppc mpc5xxx mcc200
o2dnt_config:
@./mkconfig o2dnt ppc mpc5xxx o2dnt
@ -359,15 +371,21 @@ smmaco4_config: unconfig
@./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
spieval_config: unconfig
echo "#define CONFIG_CS_AUTOCONF">>include/config.h
echo "... with automatic CS configuration"
@./mkconfig -a spieval ppc mpc5xxx tqm5200
TB5200_B_config \
TB5200_config: unconfig
@[ -z "$(findstring _B,$@)" ] || \
{ echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
echo "... with MPC5200B processor" ; \
}
@./mkconfig -n $@ -a TB5200 ppc mpc5xxx tqm5200
MINI5200_config \
EVAL5200_config \
TOP5200_config: unconfig
@ echo "#define CONFIG_$(@:_config=) 1" >include/config.h
@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
@./mkconfig -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
Total5100_config \
Total5200_config \
@ -397,36 +415,40 @@ Total5200_Rev2_lowboot_config: unconfig
}
@./mkconfig -a Total5200 ppc mpc5xxx total5200
TQM5200_auto_config \
TQM5200_AA_config \
TQM5200_AB_config \
TQM5200_AC_config \
TQM5200_config \
TQM5200_B_config \
TQM5200_B_HIGHBOOT_config \
TQM5200S_config \
TQM5200S_HIGHBOOT_config \
TQM5200_STK100_config \
cam5200_config \
MiniFAP_config: unconfig
@ >include/config.h
@[ -z "$(findstring MiniFAP,$@)" ] || \
{ echo "#define CONFIG_MINIFAP" >>include/config.h ; \
echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \
echo "... TQM5200_AC on MiniFAP" ; \
}
@[ -z "$(findstring AA,$@)" ] || \
{ echo "#define CONFIG_TQM5200_AA" >>include/config.h ; \
echo "... with 4 MB Flash, 16 MB SDRAM, 32 kB EEPROM" ; \
@[ -z "$(findstring cam5200,$@)" ] || \
{ echo "#define CONFIG_CAM5200" >>include/config.h ; \
echo "#define CONFIG_TQM5200S" >>include/config.h ; \
echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
echo "... TQM5200S on Cam5200" ; \
}
@[ -z "$(findstring AB,$@)" ] || \
{ echo "#define CONFIG_TQM5200_AB" >>include/config.h ; \
echo "... with 64 MB Flash, 64 MB SDRAM, 32 kB EEPROM, 512 kB SRAM" ; \
echo "... with Graphics Controller"; \
@[ -z "$(findstring STK100,$@)" ] || \
{ echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \
echo "... on a STK52XX.100 base board" ; \
}
@[ -z "$(findstring AC,$@)" ] || \
{ echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \
echo "... with 4 MB Flash, 128 MB SDRAM" ; \
echo "... with Graphics Controller"; \
@[ -z "$(findstring TQM5200_B,$@)" ] || \
{ echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
}
@[ -z "$(findstring auto,$@)" ] || \
{ echo "#define CONFIG_CS_AUTOCONF" >>include/config.h ; \
echo "... with automatic CS configuration" ; \
@[ -z "$(findstring TQM5200S,$@)" ] || \
{ echo "#define CONFIG_TQM5200S" >>include/config.h ; \
echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
}
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
@[ -z "$(findstring HIGHBOOT,$@)" ] || \
{ echo "TEXT_BASE = 0xFFF00000" >board/tqm5200/config.tmp ; \
}
@./mkconfig -n $@ -a TQM5200 ppc mpc5xxx tqm5200
#########################################################################
## MPC8xx Systems
@ -723,6 +745,9 @@ RRvision_LCD_config: unconfig
SM850_config : unconfig
@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
spc1920_config:
@./mkconfig $(@:_config=) ppc mpc8xx spc1920
SPD823TS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx spd8xx
@ -760,6 +785,7 @@ TQM855M_config \
TQM860M_config \
TQM862M_config \
TQM866M_config \
TQM885D_config \
virtlab2_config: unconfig
@ >include/config.h
@[ -z "$(findstring _LCD,$@)" ] || \
@ -999,6 +1025,9 @@ yosemite_config: unconfig
yellowstone_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
yucca_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yucca amcc
#########################################################################
## MPC8220 Systems
#########################################################################
@ -1049,6 +1078,9 @@ eXalion_config: unconfig
HIDDEN_DRAGON_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
kvme080_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x kvme080 etin
MOUSSE_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x mousse
@ -1303,9 +1335,6 @@ VoVPN-GW_100MHz_config: unconfig
ZPC1900_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
#========================================================================
# M68K
#========================================================================
#########################################################################
## Coldfire
#########################################################################
@ -1313,6 +1342,19 @@ ZPC1900_config: unconfig
cobra5272_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
EB+MCF-EV123_config : unconfig
@ >include/config.h
@echo "TEXT_BASE = 0xFFE00000"|tee board/BuS/EB+MCF-EV123/textbase.mk
@./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
EB+MCF-EV123_internal_config : unconfig
@ >include/config.h
@echo "TEXT_BASE = 0xF0000000"|tee board/BuS/EB+MCF-EV123/textbase.mk
@./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
M5271EVB_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 m5271evb
M5272C3_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
@ -1325,9 +1367,6 @@ TASREG_config : unconfig
r5200_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 r5200
M5271EVB_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 m5271evb
#########################################################################
## MPC83xx Systems
#########################################################################
@ -1471,6 +1510,9 @@ PCIPPC6_config: unconfig
ZUMA_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
ppmc7xx_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
#========================================================================
# ARM
#========================================================================
@ -1604,6 +1646,9 @@ omap730p2_cs3boot_config : unconfig
fi;
@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
sbc2410x_config: unconfig
@./mkconfig $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
scb9328_config : unconfig
@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
@ -1671,6 +1716,11 @@ cm4008_config : unconfig
cm41xx_config : unconfig
@./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695
gth2_config : unconfig
@ >include/config.h
@echo "#define CONFIG_GTH2 1" >>include/config.h
@./mkconfig -a gth2 mips mips gth2
#########################################################################
## S3C44B0 Systems
#########################################################################
@ -1728,6 +1778,9 @@ ixdpg425_config : unconfig
lubbock_config : unconfig
@./mkconfig $(@:_config=) arm pxa lubbock
pleb2_config : unconfig
@./mkconfig $(@:_config=) arm pxa pleb2
logodl_config : unconfig
@./mkconfig $(@:_config=) arm pxa logodl
@ -1914,6 +1967,15 @@ ADNPESC1_config: unconfig
## Nios-II
#########################################################################
EP1C20_config : unconfig
@./mkconfig EP1C20 nios2 nios2 ep1c20 altera
EP1S10_config : unconfig
@./mkconfig EP1S10 nios2 nios2 ep1s10 altera
EP1S40_config : unconfig
@./mkconfig EP1S40 nios2 nios2 ep1s40 altera
PK1C20_config : unconfig
@./mkconfig PK1C20 nios2 nios2 pk1c20 psyent
@ -1967,6 +2029,7 @@ clean:
rm -f board/netstar/*.srec board/netstar/*.bin
rm -f board/trab/trab_fkt board/voiceblue/eeprom
rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
rm -f include/bmp_logo.h
clobber: clean
find . -type f \( -name .depend \

14
README
View File

@ -306,12 +306,13 @@ The following options need to be configured:
CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250,
CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110,
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400,
CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
CONFIG_SHANNON, CONFIG_P2_OMAP730, CONFIG_SMDK2400,
CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9
CONFIG_PLEB2, CONFIG_SHANNON, CONFIG_P2_OMAP730,
CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB,
CONFIG_VCMA9
MicroBlaze based boards:
------------------------
@ -322,6 +323,7 @@ The following options need to be configured:
------------------------
CONFIG_PCI5441 CONFIG_PK1C20
CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40
- CPU Module Type: (if CONFIG_COGENT is defined)
@ -1488,6 +1490,12 @@ The following options need to be configured:
of the backslashes before semicolons and special
symbols.
- Commandline Editing and History:
CONFIG_CMDLINE_EDITING
Enable editiong and History functions for interactive
commandline input operations
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS

162
board/BuS/EB+MCF-EV123/EB+MCF-EV123.c Normal file
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@ -0,0 +1,162 @@
/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include "asm/m5282.h"
#include "VCxK.h"
int checkboard (void)
{
puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
puts (" Boot from Internal FLASH\n");
#endif
return 0;
}
long int initdram (int board_type)
{
int size,i;
size = 0;
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
| MCFSDRAMC_DCR_RC((15 * CFG_CLK)>>4);
#ifdef CFG_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_16);
MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M
| MCFSDRAMC_DMR_V;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
*(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
for (i=0; i < 2000; i++)
asm(" nop");
mbar_writeLong(MCFSDRAMC_DACR0, mbar_readLong(MCFSDRAMC_DACR0)
| MCFSDRAMC_DACR_IMRS);
*(unsigned int *)(CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE * 1024 * 1024;
#endif
#ifdef CFG_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_16;
MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M
| MCFSDRAMC_DMR_V;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
*(unsigned short *)(CFG_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i=0; i < 2000; i++)
asm(" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
*(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE1 * 1024 * 1024;
#endif
return size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
int misc_init_r(void)
{
init_vcxk();
return 1;
}
/*---------------------------------------------------------------------------*/
int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int rcode = 0;
ulong source;
switch (argc) {
case 2:
source = simple_strtoul(argv[1],NULL,16);
vcxk_loadimage(source);
rcode = 0;
break;
default:
printf ("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
break;
}
return rcode;
}
/***************************************************/
U_BOOT_CMD(
vcimage, 2, 0, do_vcimage,
"vcimage - loads an image to Display\n",
"vcimage addr\n"
);
/* EOF EB+MCF-EV123c */

40
board/BuS/EB+MCF-EV123/Makefile Normal file
View File

@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

136
board/BuS/EB+MCF-EV123/VCxK.c Normal file
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@ -0,0 +1,136 @@
/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/m5282.h>
#include "VCxK.h"
vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
#define VCXK_BWS vcxk_bws
static ulong vcxk_driver;
ulong search_vcxk_driver(void);
void vcxk_cls(void);
void vcxk_setbrightness(short brightness);
int vcxk_request(void);
int vcxk_acknowledge_wait(void);
void vcxk_clear(void);
int init_vcxk(void)
{
VIDEO_Invert_CFG &= ~VIDEO_Invert_IO;
VIDEO_INVERT_PORT |= VIDEO_INVERT_PIN;
VIDEO_INVERT_DDR |= VIDEO_INVERT_PIN;
VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
VIDEO_REQUEST_DDR |= VIDEO_REQUEST_PIN;
VIDEO_ACKNOWLEDGE_DDR &= ~VIDEO_ACKNOWLEDGE_PIN;
vcxk_driver = search_vcxk_driver();
if (vcxk_driver)
{
/* use flash resist driver */
}
else
{
vcxk_cls();
vcxk_cls();
vcxk_setbrightness(1000);
}
VIDEO_ENABLE_DDR |= VIDEO_ENABLE_PIN;
VIDEO_ENABLE_PORT |= VIDEO_ENABLE_PIN;
VIDEO_ENABLE_PORT &= ~VIDEO_ENABLE_PIN;
return 1;
}
void vcxk_loadimage(ulong source)
{
int cnt;
vcxk_acknowledge_wait();
for (cnt=0; cnt<16384; cnt++)
{
VCXK_BWS[cnt*2] = (*(vu_char*) source);
source++;
}
vcxk_request();
}
void vcxk_cls(void)
{
vcxk_acknowledge_wait();
vcxk_clear();
vcxk_request();
}
void vcxk_clear(void)
{
int cnt;
for (cnt=0; cnt<16384; cnt++)
{
VCXK_BWS[cnt*2] = 0x00;
}
}
void vcxk_setbrightness(short brightness)
{
VCXK_BWS[0x8000]=(brightness >> 4) +2;
VCXK_BWS[0xC000]= (brightness + 23) >> 8;
VCXK_BWS[0xC001]= (brightness + 23) & 0xFF;
}
int vcxk_request(void)
{
if (vcxk_driver)
{
/* use flash resist driver */
}
else
{
VIDEO_REQUEST_PORT &= ~VIDEO_REQUEST_PIN;
VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
}
return 1;
}
int vcxk_acknowledge_wait(void)
{
if (vcxk_driver)
{
/* use flash resist driver */
}
else
{
while (!(VIDEO_ACKNOWLEDGE_PORT & VIDEO_ACKNOWLEDGE_PIN));
}
return 1;
}
ulong search_vcxk_driver(void)
{
return 0;
}
/* eof */

48
board/BuS/EB+MCF-EV123/VCxK.h Normal file
View File

@ -0,0 +1,48 @@
/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __VCXK_H_
#define __VCXK_H_
extern int init_vcxk(void);
void vcxk_loadimage(ulong source);
#define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
#define VIDEO_ACKNOWLEDGE_PIN 0x0001
#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT
#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR
#define VIDEO_ENABLE_PIN 0x0002
#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT
#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR
#define VIDEO_REQUEST_PIN 0x0004
#define VIDEO_Invert_CFG MCFGPIO_PEPAR
#define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2
#define VIDEO_INVERT_PORT MCFGPIO_PORTE
#define VIDEO_INVERT_DDR MCFGPIO_DDRE
#define VIDEO_INVERT_PIN MCFGPIO_PORT2
#endif

212
board/BuS/EB+MCF-EV123/cfm_flash.c Normal file
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@ -0,0 +1,212 @@
/*
* Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH
*
* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/m5282.h>
#include "cfm_flash.h"
#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
#if (CFG_CLK>20000000)
#define CFM_CLK (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
#else
#define CFM_CLK ((long) CFG_CLK / 400000 + 1)
#endif
#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \
(CFG_MBAR & 0xC0000000))
void cfm_flash_print_info (flash_info_t * info)
{
printf ("Freescale: ");
switch (info->flash_id & FLASH_TYPEMASK) {
case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK:
printf ("MCF5281 internal FLASH\n");
break;
case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK:
printf ("MCF5282 internal FLASH\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
}
void cfm_flash_init (flash_info_t * info)
{
int sector;
ulong protection;
MCFCFM_MCR = 0;
MCFCFM_CLKD = CFM_CLK;
debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CFG_CLK);
MCFCFM_SACC = 0;
MCFCFM_DACC = 0;
if (MCFCFM_SEC & MCFCFM_SEC_KEYEN)
puts("CFM backdoor access is enabled\n");
if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT)
puts("CFM securety is enabled\n");
#ifdef CONFIG_M5281
info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
(FREESCALE_ID_MCF5281 & FLASH_TYPEMASK);
info->size = 256*1024;
info->sector_count = 16;
#else
info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
(FREESCALE_ID_MCF5282 & FLASH_TYPEMASK);
info->size = 512*1024;
info->sector_count = 32;
#endif
protection = MCFCFM_PROT;
for (sector = 0; sector < info->sector_count; sector++)
{
if (sector == 0)
{
info->start[sector] = CFG_INT_FLASH_BASE;
}
else
{
info->start[sector] = info->start[sector-1] + 0x04000;
}
info->protect[sector] = protection & 1;
protection >>= 1;
}
}
int cfm_flash_readycheck(int checkblank)
{
int rc;
unsigned char state;
rc = ERR_OK;
while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF));
state = MCFCFM_USTAT;
if (state & MCFCFM_USTAT_ACCERR)
{
debug ("%s(): CFM access error",__FUNCTION__);
rc = ERR_PROG_ERROR;
}
if (state & MCFCFM_USTAT_PVIOL)
{
debug ("%s(): CFM protection violation",__FUNCTION__);
rc = ERR_PROTECTED;
}
if (checkblank)
{
if (!(state & MCFCFM_USTAT_BLANK))
{
debug ("%s(): CFM erras error",__FUNCTION__);
rc = ERR_NOT_ERASED;
}
}
MCFCFM_USTAT = state & 0x34; /* reset state */
return rc;
}
/* Erase 16KiB = 8 2KiB pages */
int cfm_flash_erase_sector (flash_info_t * info, int sector)
{
ulong address;
int page;
int rc;
rc= ERR_OK;
address = cmf_backdoor_address(info->start[sector]);
for (page=0; (page<8) && (rc==ERR_OK); page++)
{
*(volatile __u32*) address = 0;
MCFCFM_CMD = MCFCFM_CMD_PGERS;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(0);
if (rc==ERR_OK)
{
*(volatile __u32*) address = 0;
MCFCFM_CMD = MCFCFM_CMD_PGERSVER;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(1);
}
address += 0x800;
}
return rc;
}
int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
ulong dest, data;
rc = ERR_OK;
if (addr & 3)
{
debug ("Byte and Word alignment not supported\n");
rc = ERR_ALIGN;
}
if (cnt & 3)
{
debug ("Byte and Word transfer not supported\n");
rc = ERR_ALIGN;
}
dest = cmf_backdoor_address(addr);
while ((cnt>=4) && (rc == ERR_OK))
{
data =*((volatile u32 *) src);
*(volatile u32*) dest = data;
MCFCFM_CMD = MCFCFM_CMD_PGM;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(0);
if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR;
src +=4;
dest +=4;
addr +=4;
cnt -=4;
}
return rc;
}
#ifdef CFG_FLASH_PROTECTION
int cfm_flash_protect(flash_info_t * info,long sector,int prot)
{
int rc;
rc= ERR_OK;
if (prot)
{
MCFCFM_PROT |= (1<<sector);
info->protect[sector]=1;
}
else
{
MCFCFM_PROT &= ~(1<<sector);
info->protect[sector]=0;
}
return rc;
}
#endif
#endif

40
board/BuS/EB+MCF-EV123/cfm_flash.h Normal file
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@ -0,0 +1,40 @@
/*
* Basic Flash Driver for Freescale MCF 5282 internal FLASH
*
* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CFM_FLASH_H_
#define __CFM_FLASH_H_
#define FREESCALE_MANUFACT 0xFACFFACF
#define FREESCALE_ID_MCF5281 0x5281
#define FREESCALE_ID_MCF5282 0x5282
extern void cfm_flash_print_info (flash_info_t * info);
extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
extern void cfm_flash_init (flash_info_t * info);
extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
#ifdef CFG_FLASH_PROTECTION
extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
#endif
#endif

28
board/BuS/EB+MCF-EV123/config.mk Normal file
View File

@ -0,0 +1,28 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/textbase.mk
ifndef TEXT_BASE
TEXT_BASE = 0xFE000000
endif

413
board/BuS/EB+MCF-EV123/flash.c Normal file
View File

@ -0,0 +1,413 @@
/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* Based On
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "cfm_flash.h"
#define PHYS_FLASH_1 CFG_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (AMD_MANUFACT & FLASH_VENDMASK):
printf ("AMD: ");
switch (info->flash_id & FLASH_TYPEMASK) {
case (AMD_ID_LV160B & FLASH_TYPEMASK):
printf ("AM29LV160B (16Bit)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
break;
case FREESCALE_MANUFACT & FLASH_VENDMASK:
cfm_flash_print_info (info);
break;
default:
printf ("Unknown Vendor ");
break;
}
puts (" Size: ");
if ((info->size >> 20) > 0)
{
printf ("%ld MiB",info->size >> 20);
}
else
{
printf ("%ld KiB",info->size >> 10);
}
printf (" in %d Sectors\n", info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 4) == 0) {
printf ("\n ");
}
printf ("%02d: %08lX%s ", i,info->start[i],
info->protect[i] ? " P" : " ");
}
printf ("\n\n");
}
unsigned long flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
switch (i)
{
case 1:
flash_info[i].flash_id =
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV160B & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
flashbase = PHYS_FLASH_1;
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j == 0) {
/* 1st is 16 KiB */
flash_info[i].start[j] = flashbase;
}
if ((j >= 1) && (j <= 2)) {
/* 2nd and 3rd are 8 KiB */
flash_info[i].start[j] =
flashbase + 0x4000 + 0x2000 * (j - 1);
}
if (j == 3) {
/* 4th is 32 KiB */
flash_info[i].start[j] = flashbase + 0x8000;
}
if ((j >= 4) && (j <= 34)) {
/* rest is 256 KiB */
flash_info[i].start[j] =
flashbase + 0x10000 + 0x10000 * (j - 4);
}
}
break;
case 0:
cfm_flash_init (&flash_info[i]);
break;
default:
panic ("configured to many flash banks!\n");
}
size += flash_info[i].size;
}
flash_protect (FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + 0xffff, &flash_info[0]);
return size;
}
#define CMD_READ_ARRAY 0x00F0
#define CMD_UNLOCK1 0x00AA
#define CMD_UNLOCK2 0x0055
#define CMD_ERASE_SETUP 0x0080
#define CMD_ERASE_CONFIRM 0x0030
#define CMD_PROGRAM 0x00A0
#define CMD_UNLOCK_BYPASS 0x0020
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(info->start[0] + (0x00000555<<1)))
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(info->start[0] + (0x000002AA<<1)))
#define BIT_ERASE_DONE 0x0080
#define BIT_RDY_MASK 0x0080
#define BIT_PROGRAM_ERROR 0x0020
#define BIT_TIMEOUT 0x80000000 /* our flag */
#define ERR_READY -1
int amd_flash_erase_sector(flash_info_t * info, int sector)
{
int state;
ulong result;
volatile u16 *addr =
(volatile u16 *) (info->start[sector]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
*addr = CMD_ERASE_CONFIRM;
/* wait until flash is ready */
state = 0;
set_timer (0);
do {
result = *addr;
/* check timeout */
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
state = ERR_TIMOUT;
}
if (!state && (result & 0xFFFF) & BIT_ERASE_DONE)
state = ERR_READY;
}
while (!state);
if (state == ERR_READY)
state = ERR_OK;
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
return state;
}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int iflag, cflag;
int sector;
int rc;
rc = ERR_OK;
if (info->flash_id == FLASH_UNKNOWN)
{
rc = ERR_UNKNOWN_FLASH_TYPE;
} /* (info->flash_id == FLASH_UNKNOWN) */
if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count)
{
rc = ERR_INVAL;
}
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) {
if (info->protect[sector])
{
putc('P'); /* protected sector will not erase */
}
else
{
/* erase on unprotected sector */
puts("E\b");
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_erase_sector(info,sector);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_erase_sector(info,sector);
break;
default:
return ERR_UNKNOWN_FLASH_VENDOR;
}
putc('.');
}
}
if (rc!=ERR_OK)
{
printf ("\n ");
flash_perror (rc);
}
else
{
printf (" done\n");
}
udelay (10000); /* allow flash to settle - wait 10 ms */
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
{
volatile u16 *addr;
ulong result;
int cflag, iflag;
int state;
/*
* Check if Flash is (sufficiently) erased
*/
addr = (volatile u16 *) dest;
result = *addr;
if ((result & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
set_timer (0);
/* wait until flash is ready */
state = 0;
do {
result = *addr;
/* check timeout */
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
state = ERR_TIMOUT;
}
if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
state = ERR_READY;
} while (!state);
*addr = CMD_READ_ARRAY;
if (state == ERR_READY)
state = ERR_OK;
if ((*addr != data) && (state != ERR_TIMOUT))
state = ERR_PROG_ERROR;
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return state;
}
int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
ulong dest;
u16 data;
rc = ERR_OK;
if (addr & 1)
{
debug ("Byte alignment not supported\n");
rc = ERR_ALIGN;
}
if (cnt & 1)
{
debug ("Byte transfer not supported\n");
rc = ERR_ALIGN;
}
dest = addr;
while ((cnt>=2) && (rc == ERR_OK))
{
data =*((volatile u16 *) src);
rc=amd_write_word (info,dest,data);
src +=2;
dest +=2;
cnt -=2;
}
return rc;
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_write_buff(info,src,addr,cnt);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_write_buff(info,src,addr,cnt);
break;
default:
rc = ERR_UNKNOWN_FLASH_VENDOR;
}
return rc;
}
int amd_flash_protect(flash_info_t * info,long sector,int prot)
{
int rc;
rc= ERR_OK;
if (prot)
{
info->protect[sector]=1;
}
else
{
info->protect[sector]=0;
}
return rc;
}
#ifdef CFG_FLASH_PROTECTION
int flash_real_protect(flash_info_t * info,long sector,int prot)
{
int rc;
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_protect(info,sector,prot);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_protect(info,sector,prot);
break;
default:
rc = ERR_UNKNOWN_FLASH_VENDOR;
}
return rc;
}
#endif

1
board/BuS/EB+MCF-EV123/textbase.mk Normal file
View File

@ -0,0 +1 @@
TEXT_BASE = 0xF0000000

141
board/BuS/EB+MCF-EV123/u-boot.lds Normal file
View File

@ -0,0 +1,141 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf52x2/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/string.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset; */
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

8
board/MAI/bios_emulator/scitech/src/pm/win32/event.c
View File

@ -147,14 +147,14 @@ void _EVT_pumpMessages(void)
if (EVT.oldMove != -1) {
EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */
EVT.evtq[EVT.oldMove].where_y = evt.where_y;
/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; // TODO! */
/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; // TODO! */
/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; / / TODO! */
/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; / / TODO! */
evt.what = 0;
}
else {
EVT.oldMove = EVT.freeHead; /* Save id of this move event */
/* evt.relative_x = mickeyX; // TODO! */
/* evt.relative_y = mickeyY; // TODO! */
/* evt.relative_x = mickeyX; / / TODO! */
/* evt.relative_y = mickeyY; / / TODO! */
}
}
else

3
board/Marvell/include/core.h
View File

@ -91,7 +91,10 @@ extern unsigned int INTERNAL_REG_BASE_ADDR;
#define _1G 0x40000000
#define _2G 0x80000000
#ifndef BOOL_WAS_DEFINED
#define BOOL_WAS_DEFINED
typedef enum _bool{false,true} bool;
#endif
/* Little to Big endian conversion macros */

190
board/altera/common/AMDLV065D.c Normal file
View File

@ -0,0 +1,190 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_NIOS)
#include <nios.h>
#else
#include <asm/io.h>
#endif
#define SECTSZ (64 * 1024)
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
/*----------------------------------------------------------------------*/
unsigned long flash_init (void)
{
int i;
unsigned long addr;
flash_info_t *fli = &flash_info[0];
fli->size = CFG_FLASH_SIZE;
fli->sector_count = CFG_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
addr = CFG_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
fli->protect[i] = 1;
}
return (CFG_FLASH_SIZE);
}
/*--------------------------------------------------------------------*/
void flash_print_info (flash_info_t * info)
{
int i, k;
int erased;
unsigned long *addr;
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
/* Check if whole sector is erased */
erased = 1;
addr = (unsigned long *) info->start[i];
for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
if ( readl(addr++) != (unsigned long)-1) {
erased = 0;
break;
}
}
/* Print the info */
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " ");
}
printf ("\n");
}
/*-------------------------------------------------------------------*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
unsigned char *addr = (unsigned char *) info->start[0];
unsigned char *addr2;
int prot, sect;
ulong start;
/* Some sanity checking */
if ((s_first < 0) || (s_first > s_last)) {
printf ("- no sectors to erase\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
/* It's ok to erase multiple sectors provided we don't delay more
* than 50 usec between cmds ... at which point the erase time-out
* occurs. So don't go and put printf() calls in the loop ... it
* won't be very helpful ;-)
*/
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (unsigned char *) info->start[sect];
writeb (addr, 0xaa);
writeb (addr, 0x55);
writeb (addr, 0x80);
writeb (addr, 0xaa);
writeb (addr, 0x55);
writeb (addr2, 0x30);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
start = get_timer (0);
while ( readb (addr2) != 0xff) {
udelay (1000 * 1000);
putc ('.');
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
printf ("timeout\n");
return 1;
}
}
}
}
printf ("\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
vu_char *cmd = (vu_char *) info->start[0];
vu_char *dst = (vu_char *) addr;
unsigned char b;
ulong start;
while (cnt) {
/* Check for sufficient erase */
b = *src;
if ((readb (dst) & b) != b) {
printf ("%02x : %02x\n", readb (dst), b);
return (2);
}
writeb (cmd, 0xaa);
writeb (cmd, 0x55);
writeb (cmd, 0xa0);
writeb (dst, b);
/* Verify write */
start = get_timer (0);
while (readb (dst) != b) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return 1;
}
}
dst++;
src++;
cnt--;
}
return (0);
}

62
board/altera/common/epled.c Normal file
View File

@ -0,0 +1,62 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <nios2-io.h>
#include <status_led.h>
/* The LED port is configured as output only, so we
* must track the state manually.
*/
static led_id_t val = 0;
void __led_init (led_id_t mask, int state)
{
nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
if (state == STATUS_LED_ON)
val &= ~mask;
else
val |= mask;
writel (&pio->data, val);
}
void __led_set (led_id_t mask, int state)
{
nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
if (state == STATUS_LED_ON)
val &= ~mask;
else
val |= mask;
writel (&pio->data, val);
}
void __led_toggle (led_id_t mask)
{
nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
val ^= mask;
writel (&pio->data, val);
}

50
board/altera/ep1c20/Makefile Normal file
View File

@ -0,0 +1,50 @@
#
# (C) Copyright 2001-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
COMOBJS := ../common/AMDLV065D.o ../common/epled.o
OBJS := $(BOARD).o $(COMOBJS)
SOBJS =
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

31
board/altera/ep1c20/config.mk Normal file
View File

@ -0,0 +1,31 @@
#
# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

40
board/altera/ep1c20/ep1c20.c Normal file
View File

@ -0,0 +1,40 @@
/*
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
puts ("BOARD : Altera EP-1C20\n");
return 0;
}
long int initdram (int board_type)
{
return (0);
}

136
board/altera/ep1c20/u-boot.lds Normal file
View File

@ -0,0 +1,136 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlenios2")
OUTPUT_ARCH(nios2)
ENTRY(_start)
SECTIONS
{
.text :
{
cpu/nios2/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
}
. = ALIGN (4);
_etext = .;
PROVIDE (etext = .);
/* CMD TABLE - sandwich this in between text and data so
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
__u_boot_cmd_start = .;
.u_boot_cmd :
{
*(.u_boot_cmd)
}
. = ALIGN(4);
__u_boot_cmd_end = .;
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
* adjacent to simplify the startup code -- and provide
* the global pointer for gp-relative access.
*/
_data = .;
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
}
. = ALIGN(16);
_gp = .; /* Global pointer addr */
PROVIDE (gp = .);
.sdata :
{
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
}
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
/* UNINIT DATA - Small uninitialized data is first so it's
* adjacent to sdata and can be referenced via gp. The normal
* bss follows. We keep it adjacent to simplify init code.
*/
__bss_start = .;
.sbss :
{
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
}
. = ALIGN(4);
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
*(.scommon)
}
. = ALIGN(4);
_end = .;
PROVIDE (end = .);
/* DEBUG -- symbol table, string table, etc. etc.
*/
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

50
board/altera/ep1s10/Makefile Normal file
View File

@ -0,0 +1,50 @@
#
# (C) Copyright 2001-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
COMOBJS := ../common/AMDLV065D.o ../common/epled.o
OBJS := $(BOARD).o $(COMOBJS)
SOBJS =
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

31
board/altera/ep1s10/config.mk Normal file
View File

@ -0,0 +1,31 @@
#
# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

40
board/altera/ep1s10/ep1s10.c Normal file
View File

@ -0,0 +1,40 @@
/*
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
puts ("BOARD : Altera EP-1S10\n");
return 0;
}
long int initdram (int board_type)
{
return (0);
}

136
board/altera/ep1s10/u-boot.lds Normal file
View File

@ -0,0 +1,136 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlenios2")
OUTPUT_ARCH(nios2)
ENTRY(_start)
SECTIONS
{
.text :
{
cpu/nios2/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
}
. = ALIGN (4);
_etext = .;
PROVIDE (etext = .);
/* CMD TABLE - sandwich this in between text and data so
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
__u_boot_cmd_start = .;
.u_boot_cmd :
{
*(.u_boot_cmd)
}
. = ALIGN(4);
__u_boot_cmd_end = .;
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
* adjacent to simplify the startup code -- and provide
* the global pointer for gp-relative access.
*/
_data = .;
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
}
. = ALIGN(16);
_gp = .; /* Global pointer addr */
PROVIDE (gp = .);
.sdata :
{
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
}
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
/* UNINIT DATA - Small uninitialized data is first so it's
* adjacent to sdata and can be referenced via gp. The normal
* bss follows. We keep it adjacent to simplify init code.
*/
__bss_start = .;
.sbss :
{
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
}
. = ALIGN(4);
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
*(.scommon)
}
. = ALIGN(4);
_end = .;
PROVIDE (end = .);
/* DEBUG -- symbol table, string table, etc. etc.
*/
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

50
board/altera/ep1s40/Makefile Normal file
View File

@ -0,0 +1,50 @@
#
# (C) Copyright 2001-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
COMOBJS := ../common/AMDLV065D.o ../common/epled.o
OBJS := $(BOARD).o $(COMOBJS)
SOBJS =
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

31
board/altera/ep1s40/config.mk Normal file
View File

@ -0,0 +1,31 @@
#
# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

35
board/altera/ep1s40/ep1s40.c Normal file
View File

@ -0,0 +1,35 @@
/*
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
int checkboard (void)
{
puts ("BOARD : Altera EP-1S40\n");
return 0;
}
long int initdram (int board_type)
{
return (0);
}

136
board/altera/ep1s40/u-boot.lds Normal file
View File

@ -0,0 +1,136 @@
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlenios2")
OUTPUT_ARCH(nios2)
ENTRY(_start)
SECTIONS
{
.text :
{
cpu/nios2/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
}
. = ALIGN (4);
_etext = .;
PROVIDE (etext = .);
/* CMD TABLE - sandwich this in between text and data so
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
__u_boot_cmd_start = .;
.u_boot_cmd :
{
*(.u_boot_cmd)
}
. = ALIGN(4);
__u_boot_cmd_end = .;
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
* adjacent to simplify the startup code -- and provide
* the global pointer for gp-relative access.
*/
_data = .;
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
}
. = ALIGN(16);
_gp = .; /* Global pointer addr */
PROVIDE (gp = .);
.sdata :
{
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
}
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
/* UNINIT DATA - Small uninitialized data is first so it's
* adjacent to sdata and can be referenced via gp. The normal
* bss follows. We keep it adjacent to simplify init code.
*/
__bss_start = .;
.sbss :
{
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
}
. = ALIGN(4);
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
*(.scommon)
}
. = ALIGN(4);
_end = .;
PROVIDE (end = .);
/* DEBUG -- symbol table, string table, etc. etc.
*/
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

2
board/amcc/bamboo/bamboo.c
View File

@ -435,7 +435,7 @@ long int initdram (int board_type)
*/
init_spd_array();
dram_size = spd_sdram (0);
dram_size = spd_sdram();
return dram_size;
}

13
board/amcc/bamboo/bamboo.h
View File

@ -283,10 +283,8 @@
/*----------------------------------------------------------------------------+
| PPC440EP GPIOs addresses.
+----------------------------------------------------------------------------*/
#define GPIO0_BASE 0xEF600B00
#define GPIO0_REAL 0xEF600B00
#define GPIO1_BASE 0xEF600C00
#define GPIO1_REAL 0xEF600C00
/* Offsets */
@ -331,17 +329,6 @@
#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
/*----------------------------------------------------------------------------+
| Declare Configuration values
+----------------------------------------------------------------------------*/
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef struct { unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
} gpio_param_s;
/*----------------------------------------------------------------------------+
| XX XX
|

4
board/amcc/bamboo/config.mk
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2002
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -21,7 +21,7 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFF80000
TEXT_BASE = 0xFFFA0000
PLATFORM_CPPFLAGS += -DCONFIG_440=1

4
board/amcc/yellowstone/yellowstone.c
View File

@ -313,13 +313,13 @@ void sdram_init(void)
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x84000000); /* Enable */
mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);

4
board/amcc/yosemite/yosemite.c
View File

@ -309,13 +309,13 @@ void sdram_init(void)
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x84000000); /* Enable */
mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);

47
board/amcc/yucca/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o cmd_yucca.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

288
board/amcc/yucca/cmd_yucca.c Normal file
View File

@ -0,0 +1,288 @@
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* hacked for evb440spe
*/
#include <common.h>
#include <command.h>
#include "yucca.h"
#include <i2c.h>
#include <asm/byteorder.h>
extern void print_evb440spe_info(void);
static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
int flag, int argc, char *argv[]);
extern int cmd_get_data_size(char* arg, int default_size);
/* ------------------------------------------------------------------------- */
int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
return setBootStrapClock (cmdtp, 1, flag, argc, argv);
}
/* ------------------------------------------------------------------------- */
/* Modify memory.
*
* Syntax:
* evb440spe wrclk prom0,prom1
*/
static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
int argc, char *argv[])
{
uchar chip;
ulong data;
int nbytes;
extern char console_buffer[];
char sysClock[4];
char cpuClock[4];
char plbClock[4];
char pcixClock[4];
if (argc < 3) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (strcmp(argv[2], "prom0") == 0)
chip = IIC0_BOOTPROM_ADDR;
else
chip = IIC0_ALT_BOOTPROM_ADDR;
do {
printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0))
nbytes=0;
strcpy(sysClock, console_buffer);
} while (nbytes == 0);
do {
if (strcmp(sysClock, "66") == 0) {
printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
} else {
#ifdef CONFIG_STRESS
printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
#else
printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
#endif
}
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
} else {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "500") != 0) &
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
}
strcpy(cpuClock, console_buffer);
} while (nbytes == 0);
if (strcmp(cpuClock, "500") == 0){
strcpy(plbClock, "166");
} else if (strcmp(cpuClock, "533") == 0){
strcpy(plbClock, "133");
} else {
do {
if (strcmp(cpuClock, "400") == 0)
printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n");
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0)
printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n");
#endif
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(cpuClock, "400") == 0) {
if ((strcmp(console_buffer, "100") != 0) &
(strcmp(console_buffer, "133") != 0))
nbytes = 0;
}
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0) {
if ((strcmp(console_buffer, "133") != 0) &
(strcmp(console_buffer, "166") != 0))
nbytes = 0;
}
#endif
strcpy(plbClock, console_buffer);
} while (nbytes == 0);
}
do {
printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0) &
(strcmp(console_buffer, "100") != 0) &
(strcmp(console_buffer, "133") != 0)) {
nbytes = 0;
}
strcpy(pcixClock, console_buffer);
} while (nbytes == 0);
printf("\nsys clk = %sMhz\n", sysClock);
printf("cpu clk = %sMhz\n", cpuClock);
printf("plb clk = %sMhz\n", plbClock);
printf("Pci-X clk = %sMhz\n", pcixClock);
do {
printf("\npress [y] to write I2C bootstrap \n");
printf("or [n] to abort. \n");
printf("Don't forget to set board switches \n");
printf("according to your choice before re-starting \n");
printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "n") == 0)
return 0;
} while (nbytes == 0);
if (strcmp(sysClock, "33") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "100") == 0))
data = 0x8678c206;
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x8678c2c6;
if ((strcmp(cpuClock, "500") == 0))
data = 0x8778f2c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x87790252;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x87794256;
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "166") == 0))
data = 0x87794206;
#endif
}
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "100") == 0))
data = 0x84706206;
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x847062c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x85708206;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x8570a256;
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "166") == 0))
data = 0x8570a206;
#endif
}
#ifdef DEBUG
printf(" pin strap0 to write in i2c = %x\n", data);
#endif /* DEBUG */
if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
printf("Error writing strap0 in %s\n", argv[2]);
if (strcmp(pcixClock, "33") == 0)
data = 0x00000701;
if (strcmp(pcixClock, "66") == 0)
data = 0x00000601;
if (strcmp(pcixClock, "100") == 0)
data = 0x00000501;
if (strcmp(pcixClock, "133") == 0)
data = 0x00000401;
if (strcmp(plbClock, "166") == 0)
data = data | 0x05950000;
else
data = data | 0x05A50000;
#ifdef DEBUG
printf(" pin strap1 to write in i2c = %x\n", data);
#endif /* DEBUG */
udelay(1000);
if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
printf("Error writing strap1 in %s\n", argv[2]);
return 0;
}
U_BOOT_CMD(
evb440spe, 3, 1, do_evb440spe,
"evb440spe - program the serial device strap\n",
"wrclk [prom0|prom1] - program the serial device strap\n"
);

42
board/amcc/yucca/config.mk Normal file
View File

@ -0,0 +1,42 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 440SPe Reference Platform (yucca) board
#
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else
TEXT_BASE = 0xfffb0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

1054
board/amcc/yucca/flash.c Normal file
View File

File diff suppressed because it is too large Load Diff

104
board/amcc/yucca/init.S Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
#define TLB2(a) ((a) & 0x00000fbf)
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ;\
0: mflr r0 ;\
mtlr r1 ;\
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbtab_end

157
board/amcc/yucca/u-boot.lds Normal file
View File

@ -0,0 +1,157 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yucca/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

146
board/amcc/yucca/u-boot.lds.debug Normal file
View File

@ -0,0 +1,146 @@
/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yucca/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

1096
board/amcc/yucca/yucca.c Normal file
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363
board/amcc/yucca/yucca.h Normal file
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@ -0,0 +1,363 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __YUCCA_H_
#define __YUCCA_H_
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
#define TMR_FREQ_EXT 25000000
#define BOARD_UART_CLOCK 11059200
#define BOARD_OPTION_SELECTED 1
#define BOARD_OPTION_NOT_SELECTED 0
#define ENGINEERING_CLOCK_CHECKING "clk_chk"
#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
#define ENGINEERING_CLOCK_CHECKING_DATA 1
#define ENGINEERING_EXTERNAL_CLOCK_DATA 2
/* ethernet definition */
#define MAX_ENETMODE_PARM 3
#define ENETMODE_NEG 0
#define ENETMODE_SPEED 1
#define ENETMODE_DUPLEX 2
#define ENETMODE_AUTONEG 0
#define ENETMODE_NO_AUTONEG 1
#define ENETMODE_10 2
#define ENETMODE_100 3
#define ENETMODE_1000 4
#define ENETMODE_HALF 5
#define ENETMODE_FULL 6
#define NUM_TLB_ENTRIES 64
/*----------------------------------------------------------------------------+
| TLB specific defines.
+----------------------------------------------------------------------------*/
#define TLB_256MB_ALIGN_MASK 0xF0000000
#define TLB_16MB_ALIGN_MASK 0xFF000000
#define TLB_1MB_ALIGN_MASK 0xFFF00000
#define TLB_256KB_ALIGN_MASK 0xFFFC0000
#define TLB_64KB_ALIGN_MASK 0xFFFF0000
#define TLB_16KB_ALIGN_MASK 0xFFFFC000
#define TLB_4KB_ALIGN_MASK 0xFFFFF000
#define TLB_1KB_ALIGN_MASK 0xFFFFFC00
#define TLB_256MB_SIZE 0x10000000
#define TLB_16MB_SIZE 0x01000000
#define TLB_1MB_SIZE 0x00100000
#define TLB_256KB_SIZE 0x00040000
#define TLB_64KB_SIZE 0x00010000
#define TLB_16KB_SIZE 0x00004000
#define TLB_4KB_SIZE 0x00001000
#define TLB_1KB_SIZE 0x00000400
#define TLB_WORD0_EPN_MASK 0xFFFFFC00
#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_V_MASK 0x00000200
#define TLB_WORD0_V_ENABLE 0x00000200
#define TLB_WORD0_V_DISABLE 0x00000000
#define TLB_WORD0_TS_MASK 0x00000100
#define TLB_WORD0_TS_1 0x00000100
#define TLB_WORD0_TS_0 0x00000000
#define TLB_WORD0_SIZE_MASK 0x000000F0
#define TLB_WORD0_SIZE_1KB 0x00000000
#define TLB_WORD0_SIZE_4KB 0x00000010
#define TLB_WORD0_SIZE_16KB 0x00000020
#define TLB_WORD0_SIZE_64KB 0x00000030
#define TLB_WORD0_SIZE_256KB 0x00000040
#define TLB_WORD0_SIZE_1MB 0x00000050
#define TLB_WORD0_SIZE_16MB 0x00000070
#define TLB_WORD0_SIZE_256MB 0x00000090
#define TLB_WORD0_TPAR_MASK 0x0000000F
#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
#define TLB_WORD1_RPN_MASK 0xFFFFFC00
#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_PAR1_MASK 0x00000300
#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
#define TLB_WORD1_PAR1_0 0x00000000
#define TLB_WORD1_PAR1_1 0x00000100
#define TLB_WORD1_PAR1_2 0x00000200
#define TLB_WORD1_PAR1_3 0x00000300
#define TLB_WORD1_ERPN_MASK 0x0000000F
#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
#define TLB_WORD2_PAR2_MASK 0xC0000000
#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
#define TLB_WORD2_PAR2_0 0x00000000
#define TLB_WORD2_PAR2_1 0x40000000
#define TLB_WORD2_PAR2_2 0x80000000
#define TLB_WORD2_PAR2_3 0xC0000000
#define TLB_WORD2_U0_MASK 0x00008000
#define TLB_WORD2_U0_ENABLE 0x00008000
#define TLB_WORD2_U0_DISABLE 0x00000000
#define TLB_WORD2_U1_MASK 0x00004000
#define TLB_WORD2_U1_ENABLE 0x00004000
#define TLB_WORD2_U1_DISABLE 0x00000000
#define TLB_WORD2_U2_MASK 0x00002000
#define TLB_WORD2_U2_ENABLE 0x00002000
#define TLB_WORD2_U2_DISABLE 0x00000000
#define TLB_WORD2_U3_MASK 0x00001000
#define TLB_WORD2_U3_ENABLE 0x00001000
#define TLB_WORD2_U3_DISABLE 0x00000000
#define TLB_WORD2_W_MASK 0x00000800
#define TLB_WORD2_W_ENABLE 0x00000800
#define TLB_WORD2_W_DISABLE 0x00000000
#define TLB_WORD2_I_MASK 0x00000400
#define TLB_WORD2_I_ENABLE 0x00000400
#define TLB_WORD2_I_DISABLE 0x00000000
#define TLB_WORD2_M_MASK 0x00000200
#define TLB_WORD2_M_ENABLE 0x00000200
#define TLB_WORD2_M_DISABLE 0x00000000
#define TLB_WORD2_G_MASK 0x00000100
#define TLB_WORD2_G_ENABLE 0x00000100
#define TLB_WORD2_G_DISABLE 0x00000000
#define TLB_WORD2_E_MASK 0x00000080
#define TLB_WORD2_E_ENABLE 0x00000080
#define TLB_WORD2_E_DISABLE 0x00000000
#define TLB_WORD2_UX_MASK 0x00000020
#define TLB_WORD2_UX_ENABLE 0x00000020
#define TLB_WORD2_UX_DISABLE 0x00000000
#define TLB_WORD2_UW_MASK 0x00000010
#define TLB_WORD2_UW_ENABLE 0x00000010
#define TLB_WORD2_UW_DISABLE 0x00000000
#define TLB_WORD2_UR_MASK 0x00000008
#define TLB_WORD2_UR_ENABLE 0x00000008
#define TLB_WORD2_UR_DISABLE 0x00000000
#define TLB_WORD2_SX_MASK 0x00000004
#define TLB_WORD2_SX_ENABLE 0x00000004
#define TLB_WORD2_SX_DISABLE 0x00000000
#define TLB_WORD2_SW_MASK 0x00000002
#define TLB_WORD2_SW_ENABLE 0x00000002
#define TLB_WORD2_SW_DISABLE 0x00000000
#define TLB_WORD2_SR_MASK 0x00000001
#define TLB_WORD2_SR_ENABLE 0x00000001
#define TLB_WORD2_SR_DISABLE 0x00000000
/*----------------------------------------------------------------------------+
| Board specific defines.
+----------------------------------------------------------------------------*/
#define NONCACHE_MEMORY_SIZE (64*1024)
#define NONCACHE_AREA0_ENDOFFSET (64*1024)
#define NONCACHE_AREA1_ENDOFFSET (32*1024)
#define FLASH_SECTORSIZE 0x00010000
/* SDRAM MICRON */
#define SDRAM_MICRON 0x2C
#define SDRAM_TRUE 1
#define SDRAM_FALSE 0
#define SDRAM_DDR1 1
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */
#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */
#define MAXBANKSPERDIMM 2
#define MAXRANKSPERDIMM 2
#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */
#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */
#define ERROR_STR_LENGTH 256
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
/*----------------------------------------------------------------------------+
| SDR Configuration registers
+----------------------------------------------------------------------------*/
/* Serial Device Strap Reg 0 */
#define sdr_pstrp0 0x0040
#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */
#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */
#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */
#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */
#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */
#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */
#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */
#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */
#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */
/* Serial Device Enabled - Addr = 0xA8 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
/* Serial Device Enabled - Addr = 0xA4 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
/* Pin Straps Reg */
#define SDR0_PSTRP0 0x0040
#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
/* fpgareg - defines are in include/config/YUCCA.h */
#define SDR0_CUST0_ENET3_MASK 0x00000080
#define SDR0_CUST0_ENET3_COPPER 0x00000000
#define SDR0_CUST0_ENET3_FIBER 0x00000080
#define SDR0_CUST0_RGMII3_MASK 0x00000070
#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
#define SDR0_CUST0_RGMII3_DISAB 0x00000000
#define SDR0_CUST0_RGMII3_RTBI 0x00000040
#define SDR0_CUST0_RGMII3_RGMII 0x00000050
#define SDR0_CUST0_RGMII3_TBI 0x00000060
#define SDR0_CUST0_RGMII3_GMII 0x00000070
#define SDR0_CUST0_ENET2_MASK 0x00000008
#define SDR0_CUST0_ENET2_COPPER 0x00000000
#define SDR0_CUST0_ENET2_FIBER 0x00000008
#define SDR0_CUST0_RGMII2_MASK 0x00000007
#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
#define SDR0_CUST0_RGMII2_DISAB 0x00000000
#define SDR0_CUST0_RGMII2_RTBI 0x00000004
#define SDR0_CUST0_RGMII2_RGMII 0x00000005
#define SDR0_CUST0_RGMII2_TBI 0x00000006
#define SDR0_CUST0_RGMII2_GMII 0x00000007
#define ONE_MILLION 1000000
#define ONE_BILLION 1000000000
/*----------------------------------------------------------------------------+
| X
| XX
| XX XXX XXXXX XX XXX XXXXX
| XX XX X XXX XX XX
| XX XX XXXXXX XX XX
| XX XX X XX XX XX XX
| XXX XX XXXXX X XXXX XXX
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Declare Configuration values
+----------------------------------------------------------------------------*/
typedef enum config_selection {
CONFIG_NOT_SELECTED,
CONFIG_SELECTED
} config_selection_t;
typedef enum config_list {
UART2_IN_SERVICE_MODE,
CPU_TRACE_MODE,
UART1_CTS_RTS,
CONFIG_NB
} config_list_t;
#define MAX_CONFIG_SELECT_NB 3
#define BOARD_INFO_UART2_IN_SERVICE_MODE 1
#define BOARD_INFO_CPU_TRACE_MODE 2
#define BOARD_INFO_UART1_CTS_RTS_MODE 4
void force_bup_config_selection(config_selection_t *confgi_select_P);
void update_config_selection_table(config_selection_t *config_select_P);
void display_config_selection(config_selection_t *config_select_P);
/*----------------------------------------------------------------------------+
| XX
|
| XXXX XX XXX XXX XXXX
| XX XX XX XX XX XX
| XX XXX XX XX XX XX XX
| XX XX XXXXX XX XX XX
| XXXX XX XXXX XXXX
| XXXX
|
|
|
| +------------------------------------------------------------------+
| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
| +----------------------+------------------+-----+------------+-----+
| | | | | | |
| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | |
| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | |
| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | |
| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | |
| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | |
| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | |
| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA |
| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA |
| | GPIO0_8 | PERREADY | I | TRCES4 | NA |
| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA |
| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA |
| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA |
| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA |
| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA |
| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA |
| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA |
| | GPIO0_16 | IRQ5 | I | UART2RX | I |
| | GPIO0_17 | PERBE0_N | O | UART2TX | O |
| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA |
| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA |
| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA |
| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA |
| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA |
| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA |
| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA |
| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA |
| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA |
| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA |
| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA |
| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA |
| | GPIO0_30 | UART1RX | I | NA | NA |
| | GPIO0_31 | UART1TX | O | NA | NA |
| | | | | | |
| +----------------------+------------------+-----+------------+-----+
|
+----------------------------------------------------------------------------*/
unsigned long auto_calc_speed(void);
/*----------------------------------------------------------------------------+
| Prototypes
+----------------------------------------------------------------------------*/
void print_evb440spe_info(void);
int onboard_pci_arbiter_selected(int core_pci);
#ifdef __cplusplus
}
#endif
#endif /* __YUCCA_H_ */

2
board/atc/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o ti113x.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

637
board/atc/ti113x.c Normal file
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@ -0,0 +1,637 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************
*
* Lots of code copied from:
*
* i82365.c 1.352 - Linux driver for Intel 82365 and compatible
* PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
* (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
*/
#include <common.h>
#ifdef CONFIG_I82365
#include <command.h>
#include <pci.h>
#include <pcmcia.h>
#include <asm/io.h>
#include <pcmcia/ss.h>
#include <pcmcia/i82365.h>
#include <pcmcia/yenta.h>
#include <pcmcia/ti113x.h>
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
{0, 0}
};
#define CYCLE_TIME 120
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev);
#endif
typedef struct socket_info_t {
pci_dev_t dev;
u_short bcr;
u_char pci_lat, cb_lat, sub_bus, cache;
u_int cb_phys;
socket_cap_t cap;
u_short type;
u_int flags;
ti113x_state_t state;
} socket_info_t;
static socket_info_t socket;
static socket_state_t state;
static struct pccard_mem_map mem;
static struct pccard_io_map io;
/*====================================================================*/
/* Some PCI shortcuts */
static int pci_readb (socket_info_t * s, int r, u_char * v)
{
return pci_read_config_byte (s->dev, r, v);
}
static int pci_writeb (socket_info_t * s, int r, u_char v)
{
return pci_write_config_byte (s->dev, r, v);
}
static int pci_readw (socket_info_t * s, int r, u_short * v)
{
return pci_read_config_word (s->dev, r, v);
}
static int pci_writew (socket_info_t * s, int r, u_short v)
{
return pci_write_config_word (s->dev, r, v);
}
static int pci_readl (socket_info_t * s, int r, u_int * v)
{
return pci_read_config_dword (s->dev, r, v);
}
static int pci_writel (socket_info_t * s, int r, u_int v)
{
return pci_write_config_dword (s->dev, r, v);
}
/*====================================================================*/
#define cb_readb(s, r) readb((s)->cb_phys + (r))
#define cb_readl(s, r) readl((s)->cb_phys + (r))
#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
static u_char i365_get (socket_info_t * s, u_short reg)
{
return cb_readb (s, 0x0800 + reg);
}
static void i365_set (socket_info_t * s, u_short reg, u_char data)
{
cb_writeb (s, 0x0800 + reg, data);
}
static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) | mask);
}
static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) & ~mask);
}
#if 0 /* not used */
static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
{
u_char d = i365_get (s, reg);
i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
}
static u_short i365_get_pair (socket_info_t * s, u_short reg)
{
return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
}
#endif /* not used */
static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
{
i365_set (s, reg, data & 0xff);
i365_set (s, reg + 1, data >> 8);
}
/*======================================================================
Code to save and restore global state information for TI 1130 and
TI 1131 controllers, and to set and report global configuration
options.
======================================================================*/
static void ti113x_get_state (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
}
static void ti113x_set_state (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
pci_writel (s, TI12XX_IRQMUX, p->irqmux);
i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
}
static u_int ti113x_set_opts (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
u_int mask = 0xffff;
p->cardctl &= ~TI113X_CCR_ZVENABLE;
p->cardctl |= TI113X_CCR_SPKROUTEN;
return mask;
}
/*======================================================================
Routines to handle common CardBus options
======================================================================*/
/* Default settings for PCI command configuration register */
#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
static void cb_get_state (socket_info_t * s)
{
pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
}
static void cb_set_state (socket_info_t * s)
{
pci_writel (s, CB_LEGACY_MODE_BASE, 0);
pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
pci_writew (s, PCI_COMMAND, CMD_DFLT);
pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
}
static void cb_set_opts (socket_info_t * s)
{
if (s->cache == 0)
s->cache = 8;
if (s->pci_lat == 0)
s->pci_lat = 0xa8;
if (s->cb_lat == 0)
s->cb_lat = 0xb0;
}
/*======================================================================
Power control for Cardbus controllers: used both for 16-bit and
Cardbus cards.
======================================================================*/
static int cb_set_power (socket_info_t * s, socket_state_t * state)
{
u_int reg = 0;
/* restart card voltage detection if it seems appropriate */
if ((state->Vcc == 0) && (state->Vpp == 0) &&
!(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
switch (state->Vcc) {
case 0:
reg = 0;
break;
case 33:
reg = CB_SC_VCC_3V;
break;
case 50:
reg = CB_SC_VCC_5V;
break;
default:
return -1;
}
switch (state->Vpp) {
case 0:
break;
case 33:
reg |= CB_SC_VPP_3V;
break;
case 50:
reg |= CB_SC_VPP_5V;
break;
case 120:
reg |= CB_SC_VPP_12V;
break;
default:
return -1;
}
if (reg != cb_readl (s, CB_SOCKET_CONTROL))
cb_writel (s, CB_SOCKET_CONTROL, reg);
return 0;
}
/*======================================================================
Generic routines to get and set controller options
======================================================================*/
static void get_bridge_state (socket_info_t * s)
{
ti113x_get_state (s);
cb_get_state (s);
}
static void set_bridge_state (socket_info_t * s)
{
cb_set_state (s);
i365_set (s, I365_GBLCTL, 0x00);
i365_set (s, I365_GENCTL, 0x00);
ti113x_set_state (s);
}
static void set_bridge_opts (socket_info_t * s)
{
ti113x_set_opts (s);
cb_set_opts (s);
}
/*====================================================================*/
#define PD67_EXT_INDEX 0x2e /* Extension index */
#define PD67_EXT_DATA 0x2f /* Extension data */
#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
#define pd67_ext_get(s, r) \
(i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
static int i365_get_status (socket_info_t * s, u_int * value)
{
u_int status;
status = i365_get (s, I365_IDENT);
status = i365_get (s, I365_STATUS);
*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
} else {
*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
}
*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
*value |= (status & I365_CS_READY) ? SS_READY : 0;
*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
status = cb_readl (s, CB_SOCKET_STATE);
*value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
*value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
*value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
*value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
/* For now, ignore cards with unsupported voltage keys */
if (*value & SS_XVCARD)
*value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
return 0;
} /* i365_get_status */
static int i365_set_socket (socket_info_t * s, socket_state_t * state)
{
u_char reg;
set_bridge_state (s);
/* IO card, RESET flag */
reg = 0;
reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
i365_set (s, I365_INTCTL, reg);
reg = I365_PWR_NORESET;
if (state->flags & SS_PWR_AUTO)
reg |= I365_PWR_AUTO;
if (state->flags & SS_OUTPUT_ENA)
reg |= I365_PWR_OUT;
cb_set_power (s, state);
reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
if (reg != i365_get (s, I365_POWER))
i365_set (s, I365_POWER, reg);
return 0;
} /* i365_set_socket */
/*====================================================================*/
static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
{
u_short base, i;
u_char map;
debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
mem->map, mem->flags, mem->speed,
mem->sys_start, mem->sys_stop, mem->card_start);
map = mem->map;
if ((map > 4) ||
(mem->card_start > 0x3ffffff) ||
(mem->sys_start > mem->sys_stop) ||
(mem->speed > 1000)) {
return -1;
}
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
/* Take care of high byte, for PCI controllers */
i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
base = I365_MEM (map);
i = (mem->sys_start >> 12) & 0x0fff;
if (mem->flags & MAP_16BIT)
i |= I365_MEM_16BIT;
if (mem->flags & MAP_0WS)
i |= I365_MEM_0WS;
i365_set_pair (s, base + I365_W_START, i);
i = (mem->sys_stop >> 12) & 0x0fff;
switch (mem->speed / CYCLE_TIME) {
case 0:
break;
case 1:
i |= I365_MEM_WS0;
break;
case 2:
i |= I365_MEM_WS1;
break;
default:
i |= I365_MEM_WS1 | I365_MEM_WS0;
break;
}
i365_set_pair (s, base + I365_W_STOP, i);
i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
if (mem->flags & MAP_WRPROT)
i |= I365_MEM_WRPROT;
if (mem->flags & MAP_ATTRIB)
i |= I365_MEM_REG;
i365_set_pair (s, base + I365_W_OFF, i);
/* Turn on the window if necessary */
if (mem->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
return 0;
} /* i365_set_mem_map */
static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
{
u_char map, ioctl;
map = io->map;
/* comment out: comparison is always false due to limited range of data type */
if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
(io->stop < io->start))
return -1;
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
if (io->speed)
ioctl |= I365_IOCTL_WAIT (map);
if (io->flags & MAP_0WS)
ioctl |= I365_IOCTL_0WS (map);
if (io->flags & MAP_16BIT)
ioctl |= I365_IOCTL_16BIT (map);
if (io->flags & MAP_AUTOSZ)
ioctl |= I365_IOCTL_IOCS16 (map);
i365_set (s, I365_IOCTL, ioctl);
/* Turn on the window if necessary */
if (io->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
return 0;
} /* i365_set_io_map */
/*====================================================================*/
int i82365_init (void)
{
u_int val;
int i;
if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
/* Controller not found */
return 1;
}
debug ("i82365 Device Found!\n");
pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
socket.cb_phys &= ~0xf;
get_bridge_state (&socket);
set_bridge_opts (&socket);
i = i365_get_status (&socket, &val);
if (val & SS_DETECT) {
if (val & SS_3VCARD) {
state.Vcc = state.Vpp = 33;
puts (" 3.3V card found: ");
} else if (!(val & SS_XVCARD)) {
state.Vcc = state.Vpp = 50;
puts (" 5.0V card found: ");
} else {
puts ("i82365: unsupported voltage key\n");
state.Vcc = state.Vpp = 0;
}
} else {
/* No card inserted */
puts ("No card\n");
return 1;
}
state.flags = SS_IOCARD | SS_OUTPUT_ENA;
state.csc_mask = 0;
state.io_irq = 0;
i365_set_socket (&socket, &state);
for (i = 500; i; i--) {
if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
break;
udelay (1000);
}
if (i == 0) {
/* PC Card not ready for data transfer */
puts ("i82365 PC Card not ready for data transfer\n");
return 1;
}
debug (" PC Card ready for data transfer: ");
mem.map = 0;
mem.flags = MAP_ATTRIB | MAP_ACTIVE;
mem.speed = 300;
mem.sys_start = CFG_PCMCIA_MEM_ADDR;
mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
io.map = 0;
io.flags = MAP_AUTOSZ | MAP_ACTIVE;
io.speed = 0;
io.start = 0x0100;
io.stop = 0x010F;
i365_set_io_map (&socket, &io);
#ifdef DEBUG
i82365_dump_regions (socket.dev);
#endif
return 0;
}
void i82365_exit (void)
{
io.map = 0;
io.flags = 0;
io.speed = 0;
io.start = 0;
io.stop = 0x1;
i365_set_io_map (&socket, &io);
mem.map = 0;
mem.flags = 0;
mem.speed = 0;
mem.sys_start = 0;
mem.sys_stop = 0x1000;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
socket.state.sysctl &= 0xFFFF00FF;
state.Vcc = state.Vpp = 0;
i365_set_socket (&socket, &state);
}
int pcmcia_on (void)
{
u_int rc;
debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
rc = i82365_init();
if (rc)
goto exit;
rc = check_ide_device(0);
if (rc == 0)
goto exit;
i82365_exit();
exit:
return rc;
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_off (void)
{
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
i82365_exit();
return 0;
}
#endif
/*======================================================================
Debug stuff
======================================================================*/
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev)
{
u_int tmp[2];
u_int *mem = (void *) socket.cb_phys;
u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
pci_read_config_dword (dev, 0x00, tmp + 0);
pci_read_config_dword (dev, 0x80, tmp + 1);
printf ("PCI CONF: %08X ... %08X\n",
tmp[0], tmp[1]);
printf ("PCI MEM: ... %08X ... %08X\n",
mem[0x8 / 4], mem[0x800 / 4]);
printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
printf ("CIS CONF: %02X %02X %02X ...\n",
cis[0x200], cis[0x202], cis[0x204]);
printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
ide[0], ide[1], ide[2], ide[3],
ide[4], ide[5], ide[6], ide[7]);
}
#endif /* DEBUG */
#endif /* CONFIG_I82365 */

2
board/c2mon/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

284
board/c2mon/pcmcia.c Normal file
View File

@ -0,0 +1,284 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "C2MON"
static void cfg_ports (void)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
ushort sreg;
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure Port C for TPS2211 PC-Card Power-Interface Switch
*
* Switch off all voltages, assert shutdown
*/
sreg = immap->im_ioport.iop_pcdat;
sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */
sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */
immap->im_ioport.iop_pcdat = sreg;
immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS);
immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS;
debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n",
immap->im_ioport.iop_pcpar,
immap->im_ioport.iop_pcdir,
immap->im_ioport.iop_pcdat);
/*
* Configure Port B for TPS2211 PC-Card Power-Interface Switch
*
* Over-Current Input only
*/
cp->cp_pbpar &= ~(TPS2211_INPUTS);
cp->cp_pbdir &= ~(TPS2211_INPUTS);
debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
}
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, pipr, mask;
ushort sreg;
int i;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
cfg_ports ();
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
pipr = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
pipr,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
sreg = immap->im_ioport.iop_pcdat;
if ((pipr & mask) == mask) {
sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
TPS2211_VCCD1); /* 5V on */
sreg &= ~(TPS2211_VCCD0); /* 3V off */
puts (" 5.0V card found: ");
} else {
sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
TPS2211_VCCD0); /* 3V on */
sreg &= ~(TPS2211_VCCD1); /* 5V off */
puts (" 3.3V card found: ");
}
debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n",
sreg,
( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off",
(!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off"
);
immap->im_ioport.iop_pcdat = sreg;
/* Wait 500 ms; use this to check for over-current */
for (i=0; i<5000; ++i) {
if ((cp->cp_pbdat & TPS2211_OC) == 0) {
printf (" *** Overcurrent - Safety shutdown ***\n");
immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1);
return (1);
}
udelay (100);
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
/* ALl voltages off / Hi-Z */
immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 |
TPS2211_VCCD0 | TPS2211_VCCD1 );
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
ushort sreg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable,
* Turn all power pins to Hi-Z
*/
debug ("PCMCIA power OFF\n");
cfg_ports (); /* Enables switch, but all in Hi-Z */
sreg = immap->im_ioport.iop_pcdat;
sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */
switch(vcc) {
case 0: break; /* Switch off */
case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */
sreg &= ~TPS2211_VCCD1;
break;
case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */
sreg |= TPS2211_VCCD1;
break;
default: goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
immap->im_ioport.iop_pcdat = sreg;
#ifdef DEBUG
{
char *s;
if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) {
s = "at 3.3V";
} else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) {
s = "at 5.0V";
} else {
s = "down";
}
printf ("PCMCIA powered %s\n", s);
}
#endif
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

802
board/cpc45/pd67290.c
View File

@ -1,4 +1,6 @@
/* pd67290.c - system configuration module for SPD67290
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -18,51 +20,799 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* (C) 2004 DENX Software Engineering, Heiko Schocher <hs@denx.de>
********************************************************************
*
* Lots of code copied from:
*
* i82365.c 1.352 - Linux driver for Intel 82365 and compatible
* PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
* (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <pci.h>
/* imports */
#include <mpc824x.h>
#ifdef CONFIG_I82365
#include <command.h>
#include <pci.h>
#include <pcmcia.h>
#include <asm/io.h>
#include <pcmcia/ss.h>
#include <pcmcia/i82365.h>
#include <pcmcia/yenta.h>
#include <pcmcia/cirrus.h>
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
{}
{0, 0}
};
/***************************************************************************
*
* SPD67290Init -
*
* RETURNS: -1 on error, 0 if OK
*/
#define CYCLE_TIME 120
int SPD67290Init (void)
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev);
#endif
typedef struct socket_info_t {
pci_dev_t dev;
u_short bcr;
u_char pci_lat, cb_lat, sub_bus, cache;
u_int cb_phys;
socket_cap_t cap;
u_short type;
u_int flags;
cirrus_state_t c_state;
} socket_info_t;
/* These definitions must match the pcic table! */
typedef enum pcic_id {
IS_PD6710, IS_PD672X, IS_VT83C469
} pcic_id;
typedef struct pcic_t {
char *name;
} pcic_t;
static pcic_t pcic[] = {
{" Cirrus PD6710: "},
{" Cirrus PD672x: "},
{" VIA VT83C469: "},
};
static socket_info_t socket;
static socket_state_t state;
static struct pccard_mem_map mem;
static struct pccard_io_map io;
/*====================================================================*/
/* Some PCI shortcuts */
static int pci_readb (socket_info_t * s, int r, u_char * v)
{
pci_dev_t devno;
int idx = 0; /* general index */
ulong membaseCsr; /* base address of device memory space */
return pci_read_config_byte (s->dev, r, v);
}
static int pci_writeb (socket_info_t * s, int r, u_char v)
{
return pci_write_config_byte (s->dev, r, v);
}
static int pci_readw (socket_info_t * s, int r, u_short * v)
{
return pci_read_config_word (s->dev, r, v);
}
static int pci_writew (socket_info_t * s, int r, u_short v)
{
return pci_write_config_word (s->dev, r, v);
}
/* find PD67290 device */
if ((devno = pci_find_devices (supported, idx++)) < 0) {
printf ("No PD67290 device found !!\n");
/*====================================================================*/
#define cb_readb(s) readb((s)->cb_phys + 1)
#define cb_writeb(s, v) writeb(v, (s)->cb_phys)
#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
#define cb_readl(s, r) readl((s)->cb_phys + (r))
#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
static u_char i365_get (socket_info_t * s, u_short reg)
{
u_char val;
#ifdef CONFIG_PCMCIA_SLOT_A
int slot = 0;
#else
int slot = 1;
#endif
val = I365_REG (slot, reg);
cb_writeb (s, val);
val = cb_readb (s);
debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
return val;
}
static void i365_set (socket_info_t * s, u_short reg, u_char data)
{
#ifdef CONFIG_PCMCIA_SLOT_A
int slot = 0;
#else
int slot = 1;
#endif
u_char val;
val = I365_REG (slot, reg);
cb_writeb (s, val);
cb_writeb2 (s, data);
debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
}
static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) | mask);
}
static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) & ~mask);
}
#if 0 /* not used */
static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
{
u_char d = i365_get (s, reg);
i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
}
static u_short i365_get_pair (socket_info_t * s, u_short reg)
{
return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
}
#endif /* not used */
static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
{
i365_set (s, reg, data & 0xff);
i365_set (s, reg + 1, data >> 8);
}
/*======================================================================
Code to save and restore global state information for Cirrus
PD67xx controllers, and to set and report global configuration
options.
======================================================================*/
#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
static void cirrus_get_state (socket_info_t * s)
{
int i;
cirrus_state_t *p = &s->c_state;
p->misc1 = i365_get (s, PD67_MISC_CTL_1);
p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
p->misc2 = i365_get (s, PD67_MISC_CTL_2);
for (i = 0; i < 6; i++)
p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
}
static void cirrus_set_state (socket_info_t * s)
{
int i;
u_char misc;
cirrus_state_t *p = &s->c_state;
misc = i365_get (s, PD67_MISC_CTL_2);
i365_set (s, PD67_MISC_CTL_2, p->misc2);
if (misc & PD67_MC2_SUSPEND)
udelay (50000);
misc = i365_get (s, PD67_MISC_CTL_1);
misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
for (i = 0; i < 6; i++)
i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
}
static u_int cirrus_set_opts (socket_info_t * s)
{
cirrus_state_t *p = &s->c_state;
u_int mask = 0xffff;
#if DEBUG
char buf[200];
memset (buf, 0, 200);
#endif
if (has_ring == -1)
has_ring = 1;
flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
#if DEBUG
if (p->misc2 & PD67_MC2_IRQ15_RI)
strcat (buf, " [ring]");
if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
strcat (buf, " [dyn mode]");
if (p->misc1 & PD67_MC1_INPACK_ENA)
strcat (buf, " [inpack]");
#endif
if (p->misc2 & PD67_MC2_IRQ15_RI)
mask &= ~0x8000;
if (has_led > 0) {
#if DEBUG
strcat (buf, " [led]");
#endif
mask &= ~0x1000;
}
if (has_dma > 0) {
#if DEBUG
strcat (buf, " [dma]");
#endif
mask &= ~0x0600;
flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
#if DEBUG
if (p->misc2 & PD67_MC2_FREQ_BYPASS)
strcat (buf, " [freq bypass]");
#endif
}
if (setup_time >= 0)
p->timer[0] = p->timer[3] = setup_time;
if (cmd_time > 0) {
p->timer[1] = cmd_time;
p->timer[4] = cmd_time * 2 + 4;
}
if (p->timer[1] == 0) {
p->timer[1] = 6;
p->timer[4] = 16;
if (p->timer[0] == 0)
p->timer[0] = p->timer[3] = 1;
}
if (recov_time >= 0)
p->timer[2] = p->timer[5] = recov_time;
debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
buf,
p->timer[0], p->timer[1], p->timer[2],
p->timer[3], p->timer[4], p->timer[5]);
return mask;
}
/*======================================================================
Routines to handle common CardBus options
======================================================================*/
/* Default settings for PCI command configuration register */
#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
static void cb_get_state (socket_info_t * s)
{
pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
}
static void cb_set_state (socket_info_t * s)
{
pci_writew (s, PCI_COMMAND, CMD_DFLT);
pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
}
static void cb_set_opts (socket_info_t * s)
{
}
/*======================================================================
Power control for Cardbus controllers: used both for 16-bit and
Cardbus cards.
======================================================================*/
static int cb_set_power (socket_info_t * s, socket_state_t * state)
{
u_int reg = 0;
reg = I365_PWR_NORESET;
if (state->flags & SS_PWR_AUTO)
reg |= I365_PWR_AUTO;
if (state->flags & SS_OUTPUT_ENA)
reg |= I365_PWR_OUT;
if (state->Vpp != 0) {
if (state->Vpp == 120) {
reg |= I365_VPP1_12V;
puts (" 12V card found: ");
} else if (state->Vpp == state->Vcc) {
reg |= I365_VPP1_5V;
} else {
puts (" power not found: ");
return -1;
}
}
if (state->Vcc != 0) {
reg |= I365_VCC_5V;
if (state->Vcc == 33) {
puts (" 3.3V card found: ");
i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else if (state->Vcc == 50) {
puts (" 5V card found: ");
i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else {
puts (" power not found: ");
return -1;
}
}
if (reg != i365_get (s, I365_POWER)) {
reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
i365_set (s, I365_POWER, reg);
}
return 0;
}
/*======================================================================
Generic routines to get and set controller options
======================================================================*/
static void get_bridge_state (socket_info_t * s)
{
cirrus_get_state (s);
cb_get_state (s);
}
static void set_bridge_state (socket_info_t * s)
{
cb_set_state (s);
i365_set (s, I365_GBLCTL, 0x00);
i365_set (s, I365_GENCTL, 0x00);
cirrus_set_state (s);
}
static void set_bridge_opts (socket_info_t * s)
{
cirrus_set_opts (s);
cb_set_opts (s);
}
/*====================================================================*/
#define PD67_EXT_INDEX 0x2e /* Extension index */
#define PD67_EXT_DATA 0x2f /* Extension data */
#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
#define pd67_ext_get(s, r) \
(i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
static int i365_get_status (socket_info_t * s, u_int * value)
{
u_int status;
u_char val;
u_char power, vcc, vpp;
u_int powerstate;
status = i365_get (s, I365_IDENT);
status = i365_get (s, I365_STATUS);
*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
} else {
*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
}
*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
*value |= (status & I365_CS_READY) ? SS_READY : 0;
*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
/* Check for Cirrus CL-PD67xx chips */
i365_set (s, PD67_CHIP_INFO, 0);
val = i365_get (s, PD67_CHIP_INFO);
s->type = -1;
if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
val = i365_get (s, PD67_CHIP_INFO);
if ((val & PD67_INFO_CHIP_ID) == 0) {
s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
i365_set (s, PD67_EXT_INDEX, 0xe5);
if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
s->type = IS_VT83C469;
}
} else {
printf ("no Cirrus Chip found\n");
*value = 0;
return -1;
}
/* - 0xfe000000 see MPC 8245 Users Manual Adress Map B */
membaseCsr = PCMCIA_IO_BASE - 0xfe000000;
power = i365_get (s, I365_POWER);
state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
vcc = power & I365_VCC_MASK;
vpp = power & I365_VPP1_MASK;
state.Vcc = state.Vpp = 0;
if((vcc== 0) || (vpp == 0)) {
/*
* On the Cirrus we get the info which card voltage
* we have in EXTERN DATA and write it to MISC_CTL1
*/
powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
if (powerstate & PD67_EXD_VS1(0)) {
/* 5V Card */
i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else {
/* 3.3V Card */
i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
}
i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
power = i365_get (s, I365_POWER);
}
if (power & I365_VCC_5V) {
state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
}
if (power == I365_VPP1_12V)
state.Vpp = 120;
/* IO card, RESET flags, IO interrupt */
power = i365_get (s, I365_INTCTL);
state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
if (power & I365_PC_IOCARD)
state.flags |= SS_IOCARD;
state.io_irq = power & I365_IRQ_MASK;
/* Card status change mask */
power = i365_get (s, I365_CSCINT);
state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
if (state.flags & SS_IOCARD)
state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
else {
state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
}
debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
"io_irq %d, csc_mask %#2.2x\n", state.flags,
state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
return 0;
} /* i365_get_status */
static int i365_set_socket (socket_info_t * s, socket_state_t * state)
{
u_char reg;
set_bridge_state (s);
/* IO card, RESET flag */
reg = 0;
reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
i365_set (s, I365_INTCTL, reg);
cb_set_power (s, state);
#if 0
/* Card status change interrupt mask */
reg = s->cs_irq << 4;
if (state->csc_mask & SS_DETECT)
reg |= I365_CSC_DETECT;
if (state->flags & SS_IOCARD) {
if (state->csc_mask & SS_STSCHG)
reg |= I365_CSC_STSCHG;
} else {
if (state->csc_mask & SS_BATDEAD)
reg |= I365_CSC_BVD1;
if (state->csc_mask & SS_BATWARN)
reg |= I365_CSC_BVD2;
if (state->csc_mask & SS_READY)
reg |= I365_CSC_READY;
}
i365_set (s, I365_CSCINT, reg);
i365_get (s, I365_CSC);
#endif /* 0 */
return 0;
} /* i365_set_socket */
/*====================================================================*/
static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
{
u_short base, i;
u_char map;
debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
mem->map, mem->flags, mem->speed,
mem->sys_start, mem->sys_stop, mem->card_start);
map = mem->map;
if ((map > 4) ||
(mem->card_start > 0x3ffffff) ||
(mem->sys_start > mem->sys_stop) ||
(mem->speed > 1000)) {
return -1;
}
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
/* Take care of high byte, for PCI controllers */
i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
base = I365_MEM (map);
i = (mem->sys_start >> 12) & 0x0fff;
if (mem->flags & MAP_16BIT)
i |= I365_MEM_16BIT;
if (mem->flags & MAP_0WS)
i |= I365_MEM_0WS;
i365_set_pair (s, base + I365_W_START, i);
i = (mem->sys_stop >> 12) & 0x0fff;
switch (mem->speed / CYCLE_TIME) {
case 0:
break;
case 1:
i |= I365_MEM_WS0;
break;
case 2:
i |= I365_MEM_WS1;
break;
default:
i |= I365_MEM_WS1 | I365_MEM_WS0;
break;
}
i365_set_pair (s, base + I365_W_STOP, i);
i = 0;
if (mem->flags & MAP_WRPROT)
i |= I365_MEM_WRPROT;
if (mem->flags & MAP_ATTRIB)
i |= I365_MEM_REG;
i365_set_pair (s, base + I365_W_OFF, i);
/* set System Memory map Upper Adress */
i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
/* Turn on the window if necessary */
if (mem->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
return 0;
} /* i365_set_mem_map */
static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
{
u_char map, ioctl;
map = io->map;
/* comment out: comparison is always false due to limited range of data type */
if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
(io->stop < io->start))
return -1;
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
if (io->speed)
ioctl |= I365_IOCTL_WAIT (map);
if (io->flags & MAP_0WS)
ioctl |= I365_IOCTL_0WS (map);
if (io->flags & MAP_16BIT)
ioctl |= I365_IOCTL_16BIT (map);
if (io->flags & MAP_AUTOSZ)
ioctl |= I365_IOCTL_IOCS16 (map);
i365_set (s, I365_IOCTL, ioctl);
/* Turn on the window if necessary */
if (io->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
return 0;
} /* i365_set_io_map */
/*====================================================================*/
/*
* PCI_ADDR = (HOST_ADDR - 0xfe000000)
* see MPC 8245 Users Manual Adress Map B
*/
#define HOST_TO_PCI(addr) ((addr) - 0xfe000000)
#define PCI_TO_HOST(addr) ((addr) + 0xfe000000)
int i82365_init (void)
{
u_int val;
int i;
if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
/* Controller not found */
printf ("No PD67290 device found !!\n");
return 1;
}
debug ("i82365 Device Found!\n");
socket.cb_phys = PCMCIA_IO_BASE;
/* set base address */
pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, membaseCsr);
pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0,
HOST_TO_PCI(socket.cb_phys));
/* enable mapped memory and IO addresses */
pci_write_config_dword (devno,
pci_write_config_dword (socket.dev,
PCI_COMMAND,
PCI_COMMAND_MEMORY |
PCI_COMMAND_IO | PCI_COMMAND_WAIT);
get_bridge_state (&socket);
set_bridge_opts (&socket);
i = i365_get_status (&socket, &val);
if (i > -1) {
puts (pcic[socket.type].name);
} else {
printf ("i82365: Controller not found.\n");
return 1;
}
if((val & SS_DETECT) != SS_DETECT){
puts ("No card\n");
return 1;
}
state.flags |= SS_OUTPUT_ENA;
i365_set_socket (&socket, &state);
for (i = 500; i; i--) {
if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
break;
udelay (1000);
}
if (i == 0) {
/* PC Card not ready for data transfer */
puts ("i82365 PC Card not ready for data transfer\n");
return 1;
}
debug (" PC Card ready for data transfer: ");
mem.map = 0;
mem.flags = MAP_ATTRIB | MAP_ACTIVE;
mem.speed = 300;
mem.sys_start = CFG_PCMCIA_MEM_ADDR;
mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
mem.map = 1;
mem.flags = MAP_ACTIVE;
mem.speed = 300;
mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE;
mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
#ifdef DEBUG
i82365_dump_regions (socket.dev);
#endif
return 0;
}
void i82365_exit (void)
{
io.map = 0;
io.flags = 0;
io.speed = 0;
io.start = 0;
io.stop = 0x1;
i365_set_io_map (&socket, &io);
mem.map = 0;
mem.flags = 0;
mem.speed = 0;
mem.sys_start = 0;
mem.sys_stop = 0x1000;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
mem.map = 1;
mem.flags = 0;
mem.speed = 0;
mem.sys_start = 0;
mem.sys_stop = 0x1000;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
state.Vcc = state.Vpp = 0;
i365_set_socket (&socket, &state);
}
int pcmcia_on (void)
{
u_int rc;
debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
rc = i82365_init();
if (rc)
goto exit;
rc = check_ide_device(0);
if (rc == 0)
goto exit;
i82365_exit();
exit:
return rc;
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_off (void)
{
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
i82365_exit();
return 0;
}
#endif
/*======================================================================
Debug stuff
======================================================================*/
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev)
{
u_int tmp[2];
u_int *mem = (void *) socket.cb_phys;
u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
pci_read_config_dword (dev, 0x00, tmp + 0);
pci_read_config_dword (dev, 0x80, tmp + 1);
printf ("PCI CONF: %08X ... %08X\n",
tmp[0], tmp[1]);
printf ("PCI MEM: ... %08X ... %08X\n",
mem[0x8 / 4], mem[0x800 / 4]);
printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
printf ("CIS CONF: %02X %02X %02X ...\n",
cis[0x200], cis[0x202], cis[0x204]);
printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
ide[0], ide[1], ide[2], ide[3],
ide[4], ide[5], ide[6], ide[7]);
}
#endif /* DEBUG */
#endif /* CONFIG_I82365 */

24
board/cpu87/cpu87.c
View File

@ -197,7 +197,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
*/
int checkboard (void)
{
printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV);
printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
return 0;
}
@ -280,7 +280,7 @@ long int initdram (int board_type)
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifndef CFG_RAMBOOT
ulong size8, size9;
ulong size8, size9, size10;
#endif
long psize;
@ -294,17 +294,25 @@ long int initdram (int board_type)
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL) ");
} else {
size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
(uchar *) CFG_SDRAM_BASE);
psize = max(size8,max(size9,size10));
if (psize == size8) {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:8COL) ");
}
} else if (psize == size9){
psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:9COL) ");
} else
printf ("(60x:10COL) ");
#endif /* CFG_RAMBOOT */

40
board/etin/kvme080/Makefile Normal file
View File

@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o multiverse.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

30
board/etin/kvme080/config.mk Normal file
View File

@ -0,0 +1,30 @@
#
# (C) Copyright 2005
# Sangmoon, Etin Systems, dogoil@etinsys.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# KVME080 board
#
TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

193
board/etin/kvme080/kvme080.c Normal file
View File

@ -0,0 +1,193 @@
/*
* (C) Copyright 2005
* Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
#include <asm/processor.h>
int checkboard(void)
{
puts ("Board: KVME080\n");
return 0;
}
unsigned long setdram(int m, int row, int col, int bank)
{
int i;
unsigned long start, end;
uint32_t mccr1;
uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
uint8_t mber = 0;
CONFIG_READ_WORD(MCCR1, mccr1);
mccr1 &= 0xffff0000;
start = CFG_SDRAM_BASE;
end = start + (1 << (col + row + 3) ) * bank - 1;
for (i = 0; i < m; i++) {
mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
if (i < 4) {
msar1 |= ((start >> 20) & 0xff) << i * 8;
emsar1 |= ((start >> 28) & 0xff) << i * 8;
mear1 |= ((end >> 20) & 0xff) << i * 8;
emear1 |= ((end >> 28) & 0xff) << i * 8;
} else {
msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
}
mber |= 1 << i;
start += (1 << (col + row + 3) ) * bank;
end += (1 << (col + row + 3) ) * bank;
}
for (; i < 8; i++) {
if (i < 4) {
msar1 |= 0xff << i * 8;
emsar1 |= 0x30 << i * 8;
mear1 |= 0xff << i * 8;
emear1 |= 0x30 << i * 8;
} else {
msar2 |= 0xff << (i-4) * 8;
emsar2 |= 0x30 << (i-4) * 8;
mear2 |= 0xff << (i-4) * 8;
emear2 |= 0x30 << (i-4) * 8;
}
}
CONFIG_WRITE_WORD(MCCR1, mccr1);
CONFIG_WRITE_WORD(MSAR1, msar1);
CONFIG_WRITE_WORD(EMSAR1, emsar1);
CONFIG_WRITE_WORD(MEAR1, mear1);
CONFIG_WRITE_WORD(EMEAR1, emear1);
CONFIG_WRITE_WORD(MSAR2, msar2);
CONFIG_WRITE_WORD(EMSAR2, emsar2);
CONFIG_WRITE_WORD(MEAR2, mear2);
CONFIG_WRITE_WORD(EMEAR2, emear2);
CONFIG_WRITE_BYTE(MBER, mber);
return (1 << (col + row + 3) ) * bank * m;
}
long int initdram(int board_type)
{
unsigned int msr;
long int size = 0;
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
mtmsr(msr);
if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
size = 0x20000000; /* 512MB */
else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
size = 0x10000000; /* 256MB */
else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
size = 0x10000000; /* 256MB */
else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
size = 0x08000000; /* 128MB */
else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
size = 0x08000000; /* 128MB */
else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
size = 0x04000000; /* 64MB */
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
mtspr(IBAT2L, CFG_IBAT2L);
mtspr(IBAT2U, CFG_IBAT2U);
mtspr(DBAT2L, CFG_DBAT2L);
mtspr(DBAT2U, CFG_DBAT2U);
mtmsr(msr);
return size;
}
struct pci_controller hose;
void pci_init_board(void)
{
pci_mpc824x_init(&hose);
}
int board_early_init_f(void)
{
*(volatile unsigned char *)(0xff080120) = 0xfb;
return 0;
}
int board_early_init_r(void)
{
unsigned int msr;
CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
mtmsr(msr);
return 0;
}
extern int multiverse_init(void);
int misc_init_r(void)
{
multiverse_init();
return 0;
}
void *nvram_read(void *dest, const long src, size_t count)
{
volatile uchar *d = (volatile uchar*) dest;
volatile uchar *s = (volatile uchar*) src;
while(count--) {
*d++ = *s++;
asm volatile("sync");
}
return dest;
}
void nvram_write(long dest, const void *src, size_t count)
{
volatile uchar *d = (volatile uchar*)dest;
volatile uchar *s = (volatile uchar*)src;
while(count--) {
*d++ = *s++;
asm volatile("sync");
}
}

186
board/etin/kvme080/multiverse.c Normal file
View File

@ -0,0 +1,186 @@
/*
* multiverse.c
*
* VME driver for Multiverse
*
* Author : Sangmoon Kim
* dogoil@etinsys.com
*
* Copyright 2005 ETIN SYSTEMS Co.,Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <common.h>
#include <asm/io.h>
#include <pci.h>
#include "multiverse.h"
static unsigned long vme_asi_addr;
static unsigned long vme_iack_addr;
static unsigned long pci_reg_addr;
static unsigned long vme_reg_addr;
int multiv_reset(unsigned long base)
{
writeb(0x09, base + VME_SLAVE32_AM);
writeb(0x39, base + VME_SLAVE24_AM);
writeb(0x29, base + VME_SLAVE16_AM);
writeb(0x2f, base + VME_SLAVE_REG_AM);
writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
#ifdef A32_SLV_WINDOW
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
base + VME_SLAVE32_MASK);
writeb(0x01, base + VME_SLAVE32_EN);
} else {
writeb(0xff, base + VME_SLAVE32_MASK);
writeb(0x00, base + VME_SLAVE32_EN);
}
#else
writeb(0xff, base + VME_SLAVE32_MASK);
writeb(0x00, base + VME_SLAVE32_EN);
#endif
#ifdef A24_SLV_WINDOW
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
base + VME_SLAVE24_MASK);
writeb(0x01, base + VME_SLAVE24_EN);
} else {
writeb(0xff, base + VME_SLAVE24_MASK);
writeb(0x00, base + VME_SLAVE24_EN);
}
#else
writeb(0xff, base + VME_SLAVE24_MASK);
writeb(0x00, base + VME_SLAVE24_EN);
#endif
#ifdef A16_SLV_WINDOW
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
base + VME_SLAVE16_MASK);
writeb(0x01, base + VME_SLAVE16_EN);
} else {
writeb(0xff, base + VME_SLAVE16_MASK);
writeb(0x00, base + VME_SLAVE16_EN);
}
#else
writeb(0xff, base + VME_SLAVE16_MASK);
writeb(0x00, base + VME_SLAVE16_EN);
#endif
#ifdef REG_SLV_WINDOW
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
base + VME_SLAVE_REG_MASK);
writeb(0x01, base + VME_SLAVE_REG_EN);
} else {
writeb(0xf8, base + VME_SLAVE_REG_MASK);
}
#else
writeb(0xf8, base + VME_SLAVE_REG_MASK);
#endif
writeb(0x09, base + VME_MASTER32_AM);
writeb(0x39, base + VME_MASTER24_AM);
writeb(0x29, base + VME_MASTER16_AM);
writeb(0x2f, base + VME_MASTER_REG_AM);
writel(0x00000000, base + VME_RMW_ADRS);
writeb(0x00, base + VME_IRQ);
writeb(0x00, base + VME_INT_EN);
writel(0x00000000, base + VME_IRQ1_REG);
writel(0x00000000, base + VME_IRQ2_REG);
writel(0x00000000, base + VME_IRQ3_REG);
writel(0x00000000, base + VME_IRQ4_REG);
writel(0x00000000, base + VME_IRQ5_REG);
writel(0x00000000, base + VME_IRQ6_REG);
writel(0x00000000, base + VME_IRQ7_REG);
return 0;
}
void multiv_auto_slot_id(unsigned long base)
{
unsigned int vector;
int slot_id = 1;
if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
base + VME_CTRL);
while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
while (readb(base + VME_INT) & 0x04) {
vector = *(volatile unsigned int*)
(vme_iack_addr + VME_IACK2);
*(unsigned char*)(vme_asi_addr + 0x7ffff)
= (slot_id << 3) & 0xff;
slot_id ++;
if (slot_id > 31)
break;
}
}
}
}
int multiverse_init(void)
{
int i;
pci_dev_t pdev;
unsigned int bar[6];
pdev = pci_find_device(0x1895, 0x0001, 0);
if (pdev == 0)
return -1;
for (i = 0; i < 6; i++)
pci_read_config_dword (pdev,
PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
pci_reg_addr = bar[0];
vme_reg_addr = bar[1] + 0x00F00000;
vme_iack_addr = bar[1] + 0x00200000;
vme_asi_addr = bar[3];
pci_write_config_dword (pdev, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
writel(0xFF000000, pci_reg_addr + P_TA1);
writel(0x04, pci_reg_addr + P_IMG_CTRL1);
writel(0xf0000000, pci_reg_addr + P_TA2);
writel(0x04, pci_reg_addr + P_IMG_CTRL2);
writel(0xF1000000, pci_reg_addr + P_TA3);
writel(0x04, pci_reg_addr + P_IMG_CTRL3);
writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
writel(0x04, pci_reg_addr + P_IMG_CTRL5);
writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
writel(0x04, pci_reg_addr + W_IMG_CTRL1);
writel(0xF0000000, pci_reg_addr + W_BA2);
writel(0xFF000000, pci_reg_addr + W_AM2);
writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
writel(0x04, pci_reg_addr + W_IMG_CTRL2);
writel(0xFF000000, pci_reg_addr + W_BA3);
writel(0xFF000000, pci_reg_addr + W_AM3);
writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
writel(0x04, pci_reg_addr + W_IMG_CTRL3);
writel(0x00000001, pci_reg_addr + W_ERR_CS);
writel(0x00000001, pci_reg_addr + P_ERR_CS);
multiv_reset(vme_reg_addr);
writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
vme_reg_addr + VME_CTRL);
multiv_auto_slot_id(vme_reg_addr);
return 0;
}

176
board/etin/kvme080/multiverse.h Normal file
View File

@ -0,0 +1,176 @@
/*
* multiverse.h
*
* VME driver for Multiverse
*
* Author : Sangmoon Kim
* dogoil@etinsys.com
*
* Copyright 2005 ETIN SYSTEMS Co.,Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __MULTIVERSE_H__
#define __MULTIVERSE_H__
#define VME_A32_MSTR_BUS 0x90000000
#define VME_A32_MSTR_SIZE 0x01000000
#define VME_A32_SLV_SIZE 0x01000000
#define VME_A32_SLV_BUS 0x90000000
#define VME_A24_SLV_BUS 0x00000000
#define VME_A16_SLV_BUS 0x00000000
#define VME_A32_SLV_LOCAL 0x00000000
#define VME_A24_SLV_LOCAL 0x00000000
#define VME_A16_SLV_LOCAL 0x00000000
#define A32_SLV_WINDOW
#undef A24_SLV_WINDOW
#undef A16_SLV_WINDOW
#undef REG_SLV_WINDOW
/* PCI Registers */
#define P_IMG_CTRL0 0x100
#define P_BA0 0x104
#define P_AM0 0x108
#define P_TA0 0x10C
#define P_IMG_CTRL1 0x110
#define P_BA1 0x114
#define P_AM1 0x118
#define P_TA1 0x11C
#define P_IMG_CTRL2 0x120
#define P_BA2 0x124
#define P_AM2 0x128
#define P_TA2 0x12C
#define P_IMG_CTRL3 0x130
#define P_BA3 0x134
#define P_AM3 0x138
#define P_TA3 0x13C
#define P_IMG_CTRL4 0x140
#define P_BA4 0x144
#define P_AM4 0x148
#define P_TA4 0x14C
#define P_IMG_CTRL5 0x150
#define P_BA5 0x154
#define P_AM5 0x158
#define P_TA5 0x15C
#define P_ERR_CS 0x160
#define P_ERR_ADDR 0x164
#define P_ERR_DATA 0x168
#define WB_CONF_SPC_BAR 0x180
#define W_IMG_CTRL1 0x184
#define W_BA1 0x188
#define W_AM1 0x18C
#define W_TA1 0x190
#define W_IMG_CTRL2 0x194
#define W_BA2 0x198
#define W_AM2 0x19C
#define W_TA2 0x1A0
#define W_IMG_CTRL3 0x1A4
#define W_BA3 0x1A8
#define W_AM3 0x1AC
#define W_TA3 0x1B0
#define W_IMG_CTRL4 0x1B4
#define W_BA4 0x1B8
#define W_AM4 0x1BC
#define W_TA4 0x1C0
#define W_IMG_CTRL5 0x1C4
#define W_BA5 0x1C8
#define W_AM5 0x1CC
#define W_TA5 0x1D0
#define W_ERR_CS 0x1D4
#define W_ERR_ADDR 0x1D8
#define W_ERR_DATA 0x1DC
#define CNF_ADDR 0x1E0
#define CNF_DATA 0x1E4
#define INT_ACK 0x1E8
#define ICR 0x1EC
#define ISR 0x1F0
/* VME registers */
#define VME_SLAVE32_AM 0x03
#define VME_SLAVE24_AM 0x02
#define VME_SLAVE16_AM 0x01
#define VME_SLAVE_REG_AM 0x00
#define VME_SLAVE32_A 0x07
#define VME_SLAVE24_A 0x06
#define VME_SLAVE16_A 0x05
#define VME_SLAVE_REG_A 0x04
#define VME_SLAVE32_MASK 0x0B
#define VME_SLAVE24_MASK 0x0A
#define VME_SLAVE16_MASK 0x09
#define VME_SLAVE_REG_MASK 0x08
#define VME_SLAVE32_EN 0x0F
#define VME_SLAVE24_EN 0x0E
#define VME_SLAVE16_EN 0x0D
#define VME_SLAVE_REG_EN 0x0C
#define VME_MASTER32_AM 0x13
#define VME_MASTER24_AM 0x12
#define VME_MASTER16_AM 0x11
#define VME_MASTER_REG_AM 0x10
#define VME_RMW_ADRS 0x14
#define VME_MBOX 0x18
#define VME_STATUS 0x1E
#define VME_CTRL 0x1C
#define VME_IRQ 0x20
#define VME_INT_EN 0x21
#define VME_INT 0x22
#define VME_IRQ1_REG 0x24
#define VME_IRQ2_REG 0x28
#define VME_IRQ3_REG 0x2C
#define VME_IRQ4_REG 0x30
#define VME_IRQ5_REG 0x34
#define VME_IRQ6_REG 0x38
#define VME_IRQ7_REG 0x3C
/* VME control register */
#define VME_CTRL_BRDRST 0x01
#define VME_CTRL_SYSRST 0x02
#define VME_CTRL_RMW 0x04
#define VME_CTRL_SHORT_D 0x08
#define VME_CTRL_SYSFAIL 0x10
#define VME_CTRL_VOWN 0x20
#define VME_CTRL_A16_REG_MODE 0x40
/* VME status register */
#define VME_STATUS_SYSCON 0x01
#define VME_STATUS_SYSFAIL 0x02
#define VME_STATUS_ACFAIL 0x04
#define VME_STATUS_SYSRST 0x08
#define VME_STATUS_VOWN 0x10
/* Interrupt types */
#define LVL1 0x0002
#define LVL2 0x0004
#define LVL3 0x0008
#define LVL4 0x0010
#define LVL5 0x0020
#define LVL6 0x0040
#define LVL7 0x0080
#define MULTIVERSE_INTI_INT 0x0100
#define MULTIVERSE_WB_INT 0x0200
#define MULTIVERSE_PCI_INT 0x0400
/* interrupt acknowledge */
#define VME_IACK1 0x04
#define VME_IACK2 0x08
#define VME_IACK3 0x0c
#define VME_IACK4 0x10
#define VME_IACK5 0x14
#define VME_IACK6 0x18
#define VME_IACK7 0x1c
#endif /* __MULTIVERSE_H__ */

128
board/etin/kvme080/u-boot.lds Normal file
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@ -0,0 +1,128 @@
/*
* (C) Copyright 2001-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc824x/start.o (.text)
lib_ppc/board.o (.text)
lib_ppc/ppcstring.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
board/fads/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o lamp.o
OBJS = $(BOARD).o flash.o lamp.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

2
board/fads/fads.h
View File

@ -467,7 +467,9 @@
#define CONFIG_ISO_PARTITION 1
#undef CONFIG_ATAPI
#if 0 /* does not make sense when CFG_CMD_IDE is not enabled, too */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#endif
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */

84
board/fads/pcmcia.c Normal file
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@ -0,0 +1,84 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#ifdef CONFIG_ADS
#define PCMCIA_BOARD_MSG "ADS"
#else
#define PCMCIA_BOARD_MSG "FADS"
#endif
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
u_long reg = 0;
switch(vpp) {
case 0: reg = 0; break;
case 50: reg = 1; break;
case 120: reg = 2; break;
default: return 1;
}
switch(vcc) {
case 0: reg = 0; break;
#ifdef CONFIG_ADS
case 50: reg = BCSR1_PCCVCCON; break;
#endif
#ifdef CONFIG_FADS
case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break;
case 50: reg = BCSR1_PCCVCC1; break;
#endif
default: return 1;
}
/* first, turn off all power */
#ifdef CONFIG_ADS
*((uint *)BCSR1) |= BCSR1_PCCVCCON;
#endif
#ifdef CONFIG_FADS
*((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1);
#endif
*((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK;
/* enable new powersettings */
#ifdef CONFIG_ADS
*((uint *)BCSR1) &= ~reg;
#endif
#ifdef CONFIG_FADS
*((uint *)BCSR1) |= reg;
#endif
*((uint *)BCSR1) |= reg << 20;
return 0;
}
int pcmcia_hardware_enable(int slot)
{
*((uint *)BCSR1) &= ~BCSR1_PCCEN;
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
*((uint *)BCSR1) &= ~BCSR1_PCCEN;
return 0;
}
#endif /* CFG_CMD_PCMCIA */
#endif /* CONFIG_PCMCIA */

2
board/gth/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o ee_access.o
OBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

93
board/gth/pcmcia.c Normal file
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@ -0,0 +1,93 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH"
int pcmcia_voltage_set (int slot, int vcc, int vpp)
{ /* Do nothing */
return 0;
}
int pcmcia_hardware_enable (int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: GTH Slot %c\n", 'A' + slot);
immap = (immap_t *) CFG_IMMR;
sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (500);
/*
* Make sure there is a card in the slot,
* then configure the interface.
*/
udelay (10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__, __FUNCTION__,
&(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & 0x98000000) {
printf (" No Card found\n");
return (1);
}
mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
(reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX (_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
return 0; /* No hardware to disable */
}
#endif
#endif /* CONFIG_PCMCIA */

41
board/gth2/Makefile Normal file
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@ -0,0 +1,41 @@
#
# (C) Copyright 2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o ee_access.o
SOBJS = lowlevel_init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

41
board/gth2/config.mk Normal file
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@ -0,0 +1,41 @@
#
# (C) Copyright 2004-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMD Alchemy AU1000, MIPS32 core
#
ifeq ($(TBASE),0)
TEXT_BASE = 0
else
ifeq ($(TBASE),1)
TEXT_BASE = 0xbfc10070
else
ifeq ($(TBASE),2)
TEXT_BASE = 0xbfc30070
else
## Only to make ordinary make work
TEXT_BASE = 0x90000000
endif
endif
endif

347
board/gth2/ee_access.c Normal file
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@ -0,0 +1,347 @@
/* Module for handling DALLAS DS2438, smart battery monitor
Chip can store up to 40 bytes of user data in EEPROM,
perform temp, voltage and current measurements.
Chip also contains a unique serial number.
Always read/write LSb first
For documentaion, see data sheet for DS2438, 2438.pdf
By Thomas.Lange@corelatus.com 001025
Copyright (C) 2000-2005 Corelatus AB */
/* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/au1x00.h>
#include <asm/io.h>
#include "ee_dev.h"
#include "ee_access.h"
/* static int Debug = 1; */
#undef E_DEBUG
#define E_DEBUG(fmt,args...) /* */
/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */
/* We dont have kernel functions */
#define printk printf
#define KERN_DEBUG
#define KERN_ERR
#define EIO 1
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */
static u8 crc_lookup[256] = {
0, 94, 188, 226, 97, 63, 221, 131,
194, 156, 126, 32, 163, 253, 31, 65,
157, 195, 33, 127, 252, 162, 64, 30,
95, 1, 227, 189, 62, 96, 130, 220,
35, 125, 159, 193, 66, 28, 254, 160,
225, 191, 93, 3, 128, 222, 60, 98,
190, 224, 2, 92, 223, 129, 99, 61,
124, 34, 192, 158, 29, 67, 161, 255,
70, 24, 250, 164, 39, 121, 155, 197,
132, 218, 56, 102, 229, 187, 89, 7,
219, 133, 103, 57, 186, 228, 6, 88,
25, 71, 165, 251, 120, 38, 196, 154,
101, 59, 217, 135, 4, 90, 184, 230,
167, 249, 27, 69, 198, 152, 122, 36,
248, 166, 68, 26, 153, 199, 37, 123,
58, 100, 134, 216, 91, 5, 231, 185,
140, 210, 48, 110, 237, 179, 81, 15,
78, 16, 242, 172, 47, 113, 147, 205,
17, 79, 173, 243, 112, 46, 204, 146,
211, 141, 111, 49, 178, 236, 14, 80,
175, 241, 19, 77, 206, 144, 114, 44,
109, 51, 209, 143, 12, 82, 176, 238,
50, 108, 142, 208, 83, 13, 239, 177,
240, 174, 76, 18, 145, 207, 45, 115,
202, 148, 118, 40, 171, 245, 23, 73,
8, 86, 180, 234, 105, 55, 213, 139,
87, 9, 235, 181, 54, 104, 138, 212,
149, 203, 41, 119, 244, 170, 72, 22,
233, 183, 85, 11, 136, 214, 52, 106,
43, 117, 151, 201, 74, 20, 246, 168,
116, 42, 200, 150, 21, 75, 169, 247,
182, 232, 10, 84, 215, 137, 107, 53
};
static void
write_gpio_data(int value ){
if(value){
/* Tristate */
gpio_tristate(GPIO_EEDQ);
}
else{
/* Drive 0 */
gpio_clear(GPIO_EEDQ);
}
}
static u8 make_new_crc( u8 Old_crc, u8 New_value ){
/* Compute a new checksum with new byte, using previous checksum as input
See DS app note 17, understanding and using cyclic redundancy checks...
Also see DS2438, page 11 */
return( crc_lookup[Old_crc ^ New_value ]);
}
int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
/* Check if the checksum for this buffer is correct */
u8 Curr_crc=0;
int i;
u8 *Curr_byte = Buffer;
for(i=0;i<Len;i++){
Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
Curr_byte++;
}
E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
if(Curr_crc == Crc){
/* Good */
return(TRUE);
}
printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
return(FALSE);
}
static void
set_idle(void){
/* Send idle and keep start time
Continous 1 is idle */
WRITE_PORT(1);
}
static int
do_cpu_reset(void){
/* Release reset and verify that chip responds with presence pulse */
int Retries=0;
while(Retries<15){
udelay(RESET_LOW_TIME);
/* Send reset */
WRITE_PORT(0);
udelay(RESET_LOW_TIME);
/* Release reset */
WRITE_PORT(1);
/* Wait for EEPROM to drive output */
udelay(PRESENCE_TIMEOUT);
if(!READ_PORT){
/* Ok, EEPROM is driving a 0 */
E_DEBUG("Presence detected\n");
if(Retries){
E_DEBUG("Retries %d\n",Retries);
}
/* Make sure chip releases pin */
udelay(PRESENCE_LOW_TIME);
return 0;
}
Retries++;
}
printk(KERN_ERR"eeprom did not respond when releasing reset\n");
/* Make sure chip releases pin */
udelay(PRESENCE_LOW_TIME);
/* Set to idle again */
set_idle();
return(-EIO);
}
static u8
read_cpu_byte(void){
/* Read a single byte from EEPROM
Read LSb first */
int i;
int Value;
u8 Result=0;
u32 Flags;
E_DEBUG("Reading byte\n");
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
#ifdef __KERNEL__
/* Disable irq */
save_flags(Flags);
cli();
#endif
/* Pull down pin short time to start read
See page 26 in data sheet */
WRITE_PORT(0);
udelay(READ_LOW);
WRITE_PORT(1);
/* Wait for chip to drive pin */
udelay(READ_TIMEOUT);
Value = READ_PORT;
if(Value)
Value=1;
#ifdef __KERNEL__
/* Enable irq */
restore_flags(Flags);
#endif
/* Wait for chip to release pin */
udelay(TOTAL_READ_LOW-READ_TIMEOUT);
/* LSb first */
Result|=Value<<i;
/* E_DEBUG("Read %d\n",Value); */
}
E_DEBUG("Read byte 0x%x\n",Result);
return(Result);
}
static void
write_cpu_byte(u8 Byte){
/* Write a single byte to EEPROM
Write LSb first */
int i;
int Value;
u32 Flags;
E_DEBUG("Writing byte 0x%x\n",Byte);
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
Value = Byte&1;
#ifdef __KERNEL__
/* Disable irq */
save_flags(Flags);
cli();
#endif
/* Pull down pin short time for a 1, long time for a 0
See page 26 in data sheet */
WRITE_PORT(0);
if(Value){
/* Write a 1 */
udelay(WRITE_1_LOW);
}
else{
/* Write a 0 */
udelay(WRITE_0_LOW);
}
WRITE_PORT(1);
#ifdef __KERNEL__
/* Enable irq */
restore_flags(Flags);
#endif
if(Value)
/* Wait for chip to read the 1 */
udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
/* E_DEBUG("Wrote %d\n",Value); */
Byte>>=1;
}
}
int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
/* Execute this command string, including
giving reset and setting to idle after command
if Rx_len is set, we read out data from EEPROM */
int i;
E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
if(do_cpu_reset()){
/* Failed! */
return(-EIO);
}
if(Send_skip)
/* Always send SKIP_ROM first to tell chip we are sending a command,
except when we read out rom data for chip */
write_cpu_byte(SKIP_ROM);
/* Always have Tx data */
for(i=0;i<Tx_len;i++){
write_cpu_byte(Tx[i]);
}
if(Rx_len){
for(i=0;i<Rx_len;i++){
Rx[i]=read_cpu_byte();
}
}
set_idle();
E_DEBUG("Command done\n");
return(0);
}
int ee_init_cpu_data(void){
int i;
u8 Tx[10];
/* Leave it floting since altera is driving the same pin */
set_idle();
/* Copy all User EEPROM data to scratchpad */
for(i=0;i<USER_PAGES;i++){
Tx[0]=RECALL_MEMORY;
Tx[1]=EE_USER_PAGE_0+i;
if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
}
/* Make sure chip doesnt store measurements in NVRAM */
Tx[0]=WRITE_SCRATCHPAD;
Tx[1]=0; /* Page */
Tx[2]=9;
if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
Tx[0]=COPY_SCRATCHPAD;
if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
for(i=0;i<10;i++){
udelay(1000);
}
return(0);
}

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/* By Thomas.Lange@Corelatus.com 001025 */
/* Definitions for EEPROM/VOLT METER DS2438 */
/* Copyright (C) 2000-2005 Corelatus AB */
#ifndef INCeeaccessh
#define INCeeaccessh
#include <asm/types.h>
#include "ee_dev.h"
int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
int ee_init_cpu_data(void);
int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
/* Defs for altera reg */
#define EE_WRITE_SHIFT 8 /* bits to shift left */
#define EE_READ_SHIFT 16 /* bits to shift left */
#define EE_DONE 0x80000000
#define EE_BUSY 0x40000000
#define EE_ERROR 0x20000000
/* Commands */
#define EE_CMD_NOP 0
#define EE_CMD_INIT_RES 1
#define EE_CMD_WR_BYTE 2
#define EE_CMD_RD_BYTE 3
#endif /* INCeeaccessh */

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/* By Thomas.Lange@Corelatus.com 001025 */
/* Definitions for EEPROM/VOLT METER DS2438 */
/* Copyright (C) 2000-2005 Corelatus AB */
/* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef INCeedevh
#define INCeedevh
#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
/* MIPS */
#define WRITE_PORT(Value) write_gpio_data(Value)
#define READ_PORT (gpio_read()&GPIO_EEDQ)
/* 64 bytes chip */
#define EE_CHIP_SIZE 64
/* Board with new current resistor */
#define EE_GTH_0304 1
/* new dsp and 64 MB SDRAM */
#define EE_DSP_64 0x10
/* microsecs */
/* Pull line down at least this long for reset pulse */
#define RESET_LOW_TIME 490
/* Read presence pulse after we release reset pulse */
#define PRESENCE_TIMEOUT 100
#define PRESENCE_LOW_TIME 200
#define WRITE_0_LOW 60
#define WRITE_1_LOW 1
#define TOTAL_WRITE_LOW 60
#define READ_LOW 1
#define READ_TIMEOUT 10
#define TOTAL_READ_LOW 70
/* Rom function commands */
#define READ_ROM 0x33
#define MATCH_ROM 0x55
#define SKIP_ROM 0xCC
#define SEARCH_ROM 0xF0
/* Memory_command_function */
#define WRITE_SCRATCHPAD 0x4E
#define READ_SCRATCHPAD 0xBE
#define COPY_SCRATCHPAD 0x48
#define RECALL_MEMORY 0xB8
#define CONVERT_TEMP 0x44
#define CONVERT_VOLTAGE 0xB4
/* Chip is divided in 8 pages, 8 bytes each */
#define EE_PAGE_SIZE 8
/* All chip data we want are in page 0 */
/* Bytes in page 0 */
#define EE_P0_STATUS 0
#define EE_P0_TEMP_LSB 1
#define EE_P0_TEMP_MSB 2
#define EE_P0_VOLT_LSB 3
#define EE_P0_VOLT_MSB 4
#define EE_P0_CURRENT_LSB 5
#define EE_P0_CURRENT_MSB 6
/* 40 byte user data is located at page 3-7 */
#define EE_USER_PAGE_0 3
#define USER_PAGES 5
/* Layout of gth user pages usage */
/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */
#define EE_ETHERNET_OFFSET 0
#endif /* INCeedevh */

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/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
printf ("Skipping flash_init\n");
return (0);
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
printf ("write_buff not implemented\n");
return (-1);
}

435
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/*
* (C) Copyright 2005
* Thomas.Lange@corelatus.se
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/au1x00.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
#include <watchdog.h>
#include "ee_access.h"
static int wdi_status = 0;
unsigned long mips_io_port_base = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
void inline log_serial_char(char c){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
int serial_log_offset;
u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
serial_log_offset = *serial_log_offsetp;
*(serial_log_buffer + serial_log_offset) = c;
serial_log_offset++;
if(serial_log_offset >= 4096){
serial_log_offset = 4;
}
*serial_log_offsetp = serial_log_offset;
}
void init_log_serial(void){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
/* Copy buffer from last run */
memcpy(serial_log_buffer + 4096,
serial_log_buffer,
4096);
memset(serial_log_buffer, 0, 4096);
*serial_log_offsetp = 4;
}
void hw_watchdog_reset(void){
volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR;
if(wdi_status){
*sys_outputset = GPIO_CPU_LED|GPIO_WDI;
wdi_status = 0;
}
else{
*sys_outputclear = GPIO_CPU_LED|GPIO_WDI;
wdi_status = 1;
}
}
long int initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
WATCHDOG_RESET();
return (SDRAM_SIZE);
}
/* In cpu/mips/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
void set_ledcard(u32 value){
/* Clock 24 bits to led card */
int i;
volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
/* Start with known values */
*sys_outputclr = GPIO_LEDCLK|GPIO_LEDD;
for(i=0;i<24;i++){
if(value&0x00800000){
*sys_outputset = GPIO_LEDD;
}
else{
*sys_outputclr = GPIO_LEDD;
}
udelay(1);
*sys_outputset = GPIO_LEDCLK;
udelay(1);
*sys_outputclr = GPIO_LEDCLK;
udelay(1);
value<<=1;
}
/* Data is enable output */
*sys_outputset = GPIO_LEDD;
}
int checkboard (void)
{
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
u32 proc_id;
WATCHDOG_RESET();
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
switch (proc_id >> 24) {
case 0:
puts ("Board: GTH2\n");
printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n",
(proc_id >> 8) & 0xFF, proc_id & 0xFF);
break;
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
#ifdef CONFIG_IDE_PCMCIA
/* PCMCIA is on a 36 bit physical address.
We need to map it into a 32 bit addresses */
write_one_tlb(20, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_IO_BASE, /* Hi */
0x3C000017, /* Lo0 */
0x3C200017); /* Lo1 */
write_one_tlb(21, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_ATTR_BASE, /* Hi */
0x3D000017, /* Lo0 */
0x3D200017); /* Lo1 */
write_one_tlb(22, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_MEM_ADDR, /* Hi */
0x3E000017, /* Lo0 */
0x3E200017); /* Lo1 */
#endif /* CONFIG_IDE_PCMCIA */
/* Wait for GPIO ports to become stable */
udelay(5000); /* FIXME */
/* Release reset of ethernet PHY chips */
/* Always do this, because linux does not know about it */
*sys_outputset = GPIO_ERESET;
/* Kill FPGA:s */
*sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG;
udelay(2);
*sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG;
/* Turn front led yellow */
set_ledcard(0x00100000);
return 0;
}
#define POWER_OFFSET 0xF0000
#define SW_WATCHDOG_REASON 13
#define BOOTDATA_OFFSET 0xF8000
#define MAX_ATTEMPTS 5
#define FAILSAFE_BOOT 1
#define SYSTEM_BOOT 2
#define SYSTEM2_BOOT 3
#define WRITE_FLASH16(a, d) \
do \
{ \
*((volatile u16 *) (a)) = (d);\
} while(0)
static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
{
u16 data;
volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
switch(System){
case FAILSAFE_BOOT:
printf ("Setting failsafe boot in flash\n");
break;
case SYSTEM_BOOT:
printf ("Setting system boot in flash\n");
break;
case SYSTEM2_BOOT:
printf ("Setting system2 boot in flash\n");
break;
default:
printf ("Invalid system data %u, setting failsafe\n", System);
System = FAILSAFE_BOOT;
}
if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
printf ("Invalid boot count %u, setting 1\n", Count);
Count = 1;
}
printf ("Boot attempt %d\n", Count);
data = (System << 8) | Count;
/* AMD 16 bit */
WRITE_FLASH16 (&flash[0x555], 0xAAAA);
WRITE_FLASH16 (&flash[0x2AA], 0x5555);
WRITE_FLASH16 (&flash[0x555], 0xA0A0);
WRITE_FLASH16 (addr, data);
}
static int random_system(void){
/* EEPROM read failed. Just try to choose one
system release and hope it works */
/* FIXME */
return(SYSTEM_BOOT);
}
static int switch_system(int old_system){
u8 Rx[10];
u8 Tx[5];
int valid_release;
if(old_system==FAILSAFE_BOOT){
/* Find out which system release to use */
/* Copy from nvram to scratchpad */
Tx[0] = RECALL_MEMORY;
Tx[1] = 7; /* Page */
if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
printf ("EE user page 7 recall failed\n");
return (random_system());
}
Tx[0] = READ_SCRATCHPAD;
if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) {
printf ("EE user page 7 read failed\n");
return (random_system());
}
/* Crc in 9:th byte */
if (!ee_crc_ok (Rx, 8, *(Rx + 8))) {
printf ("EE read failed, page 7. CRC error\n");
return (random_system());
}
valid_release = Rx[7];
if((valid_release==0xFF)|
((valid_release&1) == 0)){
return(SYSTEM_BOOT);
}
else{
return(SYSTEM2_BOOT);
}
}
else{
return(FAILSAFE_BOOT);
}
}
static void check_boot_tries (void)
{
/* Count the number of boot attemps
switch system if too many */
int i;
volatile u16 *addr;
volatile u16 data;
u8 system = FAILSAFE_BOOT;
u8 count;
addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET);
if (*addr == 0xFFFF) {
printf ("*** No bootdata exists. ***\n");
write_bootdata (addr, FAILSAFE_BOOT, 1);
} else {
/* Search for latest written bootdata */
i = 0;
while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
addr++;
i++;
}
if (i >= 8000) {
/* Whoa, dont write any more */
printf ("*** No bootdata found. Not updating flash***\n");
} else {
/* See how many times we have tried to boot real system */
data = *addr;
system = data >> 8;
count = data & 0xFF;
if ((system != SYSTEM_BOOT) &
(system != SYSTEM2_BOOT) &
(system != FAILSAFE_BOOT)) {
printf ("*** Wrong system %d\n", system);
system = FAILSAFE_BOOT;
count = 1;
} else {
switch (count) {
case 0:
case 1:
case 2:
case 3:
case 4:
/* Try same system again if needed */
count++;
break;
case 5:
/* Switch system and reset tries */
count = 1;
system = switch_system(system);
printf ("***Too many boot attempts, switching system***\n");
break;
default:
/* Switch system, start over and hope it works */
printf ("***Unexpected data on addr 0x%x, %u***\n",
(u32) addr, data);
count = 1;
system = switch_system(system);
}
}
write_bootdata (addr + 1, system, count);
}
}
switch(system){
case FAILSAFE_BOOT:
printf ("Booting failsafe system\n");
setenv ("bootargs", "panic=1 root=/dev/hda7");
setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm");
break;
case SYSTEM_BOOT:
printf ("Using normal system\n");
setenv ("bootargs", "panic=1 root=/dev/hda4");
setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm");
break;
case SYSTEM2_BOOT:
printf ("Using normal system2\n");
setenv ("bootargs", "panic=1 root=/dev/hda9");
setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm");
break;
default:
printf ("Invalid system %d\n", system);
printf ("Hanging\n");
while(1);
}
}
int misc_init_r(void){
u8 Rx[80];
u8 Tx[5];
int page;
int read = 0;
WATCHDOG_RESET();
if (ee_init_cpu_data ()) {
printf ("EEPROM init failed\n");
return (0);
}
/* Check which release to boot */
check_boot_tries ();
/* Read the pages where ethernet address is stored */
for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
/* Copy from nvram to scratchpad */
Tx[0] = RECALL_MEMORY;
Tx[1] = page;
if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
printf ("EE user page %d recall failed\n", page);
return (0);
}
Tx[0] = READ_SCRATCHPAD;
if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) {
printf ("EE user page %d read failed\n", page);
return (0);
}
/* Crc in 9:th byte */
if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
printf ("EE read failed, page %d. CRC error\n", page);
return (0);
}
read += 8;
}
/* Add eos after eth addr */
Rx[17] = 0;
printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
if ((Rx[2] != ':') |
(Rx[5] != ':') |
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
printf ("*** ethernet addr invalid, using default ***\n");
} else {
setenv ("ethaddr", Rx);
}
return (0);
}

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/* Memory sub-system initialization code */
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#define CP0_Config0 $16
#define MEM_1MS ((CFG_MHZ) * 1000)
#define GPIO_RJ1LY (1<<22)
#define GPIO_CFRESET (1<<10)
.text
.set noreorder
.set mips32
.globl lowlevel_init
lowlevel_init:
/*
* Step 2) Establish Status Register
* (set BEV, clear ERL, clear EXL, clear IE)
*/
li t1, 0x00400000
mtc0 t1, CP0_STATUS
/*
* Step 3) Establish CP0 Config0
* (set OD, set K0=3)
*/
li t1, 0x00080003
mtc0 t1, CP0_CONFIG
/*
* Step 4) Disable Watchpoint facilities
*/
li t1, 0x00000000
mtc0 t1, CP0_WATCHLO
mtc0 t1, CP0_IWATCHLO
/*
* Step 5) Disable the performance counters
*/
mtc0 zero, CP0_PERFORMANCE
nop
/*
* Step 6) Establish EJTAG Debug register
*/
mtc0 zero, CP0_DEBUG
nop
/*
* Step 7) Establish Cause
* (set IV bit)
*/
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
/* Establish Wired (and Random) */
mtc0 zero, CP0_WIRED
nop
/* No workaround if running from ram */
lui t0, 0xffc0
lui t3, 0xbfc0
and t1, ra, t0
bne t1, t3, noCacheJump
nop
/*** From AMD YAMON ***/
/*
* Step 8) Initialize the caches
*/
li t0, (16*1024)
li t1, 32
li t2, 0x80000000
addu t3, t0, t2
cacheloop:
cache 0, 0(t2)
cache 1, 0(t2)
addu t2, t1
bne t2, t3, cacheloop
nop
/* Save return address */
move t3, ra
/* Run from cacheable space now */
bal cachehere
nop
cachehere:
li t1, ~0x20000000 /* convert to KSEG0 */
and t0, ra, t1
addi t0, 5*4 /* 5 insns beyond cachehere */
jr t0
nop
/* Restore return address */
move ra, t3
/*
* Step 9) Initialize the TLB
*/
li t0, 0 # index value
li t1, 0x00000000 # entryhi value
li t2, 32 # 32 entries
tlbloop:
/* Probe TLB for matching EntryHi */
mtc0 t1, CP0_ENTRYHI
tlbp
nop
/* Examine Index[P], 1=no matching entry */
mfc0 t3, CP0_INDEX
li t4, 0x80000000
and t3, t4, t3
addiu t1, t1, 1 # increment t1 (asid)
beq zero, t3, tlbloop
nop
/* Initialize the TLB entry */
mtc0 t0, CP0_INDEX
mtc0 zero, CP0_ENTRYLO0
mtc0 zero, CP0_ENTRYLO1
mtc0 zero, CP0_PAGEMASK
tlbwi
/* Do it again */
addiu t0, t0, 1
bne t0, t2, tlbloop
nop
/* First setup pll:s to make serial work ok */
/* We have a 12.5 MHz crystal */
li t0, SYS_CPUPLL
li t1, 0x28 /* CPU clock, 500 MHz */
sw t1, 0(t0)
sync
nop
nop
/* wait 1mS for clocks to settle */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* Setup AUX PLL */
li t0, SYS_AUXPLL
li t1, 0
sw t1, 0(t0) /* aux pll */
sync
/* Static memory controller */
/* RCE0 - can not change while fetching, do so from icache */
move t2, ra /* Store return address */
bal getAddr
nop
getAddr:
move t1, ra
move ra, t2 /* Move return addess back */
cache 0x14,0(t1)
cache 0x14,32(t1)
/*** /From YAMON ***/
noCacheJump:
/* Static memory controller */
/* RCE0 AMD 29LV800 Flash */
li t0, MEM_STCFG0
li t1, 0x00000243
sw t1, 0(t0)
li t0, MEM_STTIME0
li t1, 0x040181D7 /* FIXME */
sw t1, 0(t0)
li t0, MEM_STADDR0
li t1, 0x11E03F80
sw t1, 0(t0)
/* RCE1 PCMCIA 250ns */
li t0, MEM_STCFG1
li t1, 0x00000002
sw t1, 0(t0)
li t0, MEM_STTIME1
li t1, 0x280E3E07
sw t1, 0(t0)
li t0, MEM_STADDR1
li t1, 0x10000000
sw t1, 0(t0)
/* RCE2 CP Altera */
li t0, MEM_STCFG2
li t1, 0x00000280 /* BE, EW */
sw t1, 0(t0)
li t0, MEM_STTIME2
li t1, 0x0303000c
sw t1, 0(t0)
li t0, MEM_STADDR2
li t1, 0x10c03f80 /* 1 MB */
sw t1, 0(t0)
/* RCE3 DP Altera */
li t0, MEM_STCFG3
li t1, 0x00000280 /* BE, EW */
sw t1, 0(t0)
li t0, MEM_STTIME3
li t1, 0x0303000c
sw t1, 0(t0)
li t0, MEM_STADDR3
li t1, 0x10e03f80 /* 1 MB */
sw t1, 0(t0)
sync
/* Set peripherals to a known state */
li t0, IC0_CFG0CLR
li t1, 0xFFFFFFFF
sw t1, 0(t0)
li t0, IC0_CFG0CLR
sw t1, 0(t0)
li t0, IC0_CFG1CLR
sw t1, 0(t0)
li t0, IC0_CFG2CLR
sw t1, 0(t0)
li t0, IC0_SRCSET
sw t1, 0(t0)
li t0, IC0_ASSIGNSET
sw t1, 0(t0)
li t0, IC0_WAKECLR
sw t1, 0(t0)
li t0, IC0_RISINGCLR
sw t1, 0(t0)
li t0, IC0_FALLINGCLR
sw t1, 0(t0)
li t0, IC0_TESTBIT
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, IC1_CFG0CLR
li t1, 0xFFFFFFFF
sw t1, 0(t0)
li t0, IC1_CFG0CLR
sw t1, 0(t0)
li t0, IC1_CFG1CLR
sw t1, 0(t0)
li t0, IC1_CFG2CLR
sw t1, 0(t0)
li t0, IC1_SRCSET
sw t1, 0(t0)
li t0, IC1_ASSIGNSET
sw t1, 0(t0)
li t0, IC1_WAKECLR
sw t1, 0(t0)
li t0, IC1_RISINGCLR
sw t1, 0(t0)
li t0, IC1_FALLINGCLR
sw t1, 0(t0)
li t0, IC1_TESTBIT
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, SYS_FREQCTRL0
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_FREQCTRL1
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_CLKSRC
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_PININPUTEN
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, 0xB1100100
li t1, 0x00000000
sw t1, 0(t0)
li t0, 0xB1400100
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_WAKEMSK
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_WAKESRC
li t1, 0x00000000
sw t1, 0(t0)
/* wait 1mS before setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* SDCS 0 SDRAM */
li t0, MEM_SDMODE0
li t1, 0x592CD1
sw t1, 0(t0)
li t0, MEM_SDMODE1
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_SDMODE2
li t1, 0x00000000
sw t1, 0(t0)
/* 64 MB SDRAM at addr 0 */
li t0, MEM_SDADDR0
li t1, 0x001003F0
sw t1, 0(t0)
li t0, MEM_SDADDR1
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_SDADDR2
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x880007A1 /* Disable */
sw t1, 0(t0)
sync
li t0, MEM_SDPRECMD
sw zero, 0(t0)
sync
li t0, MEM_SDAUTOREF
sw zero, 0(t0)
sync
sw zero, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x8A0007A1 /* Enable */
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD0
li t1, 0x00000023
sw t1, 0(t0)
sync
/* wait 1mS after setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* Setup GPIO pins */
li t0, SYS_PINFUNC
li t1, 0x00007025 /* 0x8080 */
sw t1, 0(t0)
li t0, SYS_TRIOUTCLR
li t1, 0xFFFFFFFF /* 0x1FFF */
sw t1, 0(t0)
/* Turn yellow front led on */
/* Release reset on CF */
li t0, SYS_OUTPUTCLR
li t1, GPIO_RJ1LG
sw t1, 0(t0)
li t0, SYS_OUTPUTSET
li t1, GPIO_RJ1LY|GPIO_CFRESET
sw t1, 0(t0)
sync
j clearmem
nop
.globl memtest
memtest:
/* Fill memory with address */
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
mt0: sw t0, 0(t0)
add t1, -1
add t0, 4
bne t1, zero, mt0
nop
nop
/* Verify addr */
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
mt1: lw t2, 0(t0)
bne t0, t2, memhang
add t1, -1
add t0, 4
bne t1, zero, mt1
nop
nop
.globl clearmem
clearmem:
/* Clear memory */
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
mtc: sw zero, 0(t0)
add t1, -1
add t0, 4
bne t1, zero, mtc
nop
nop
memtestend:
j ra
nop
memhang:
b memhang
nop

68
board/gth2/u-boot.lds Normal file
View File

@ -0,0 +1,68 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

2
board/icu862/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

268
board/icu862/pcmcia.c Normal file
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@ -0,0 +1,268 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "ICU862"
static void cfg_port_B (void)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
uint reg;
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure Port B for TPS2205 PC-Card Power-Interface Switch
*
* Switch off all voltages, assert shutdown
*/
reg = cp->cp_pbdat;
reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */
TPS2205_SHDN); /* enable switch */
cp->cp_pbdat = reg;
cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS);
reg = cp->cp_pbdir & ~(TPS2205_INPUTS);
cp->cp_pbdir = reg | TPS2205_OUTPUTS;
debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
}
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, pipr, mask;
int i;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* Configure Port B for TPS2205 PC-Card Power-Interface Switch */
cfg_port_B ();
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
pipr = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
pipr,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
reg = cp->cp_pbdat;
if ((pipr & mask) == mask) {
reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
TPS2205_VCC3); /* 3V off */
reg &= ~(TPS2205_VCC5); /* 5V on */
puts (" 5.0V card found: ");
} else {
reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
TPS2205_VCC5); /* 5V off */
reg &= ~(TPS2205_VCC3); /* 3V on */
puts (" 3.3V card found: ");
}
debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n",
reg,
(reg & TPS2205_VCC3) ? "off" : "on",
(reg & TPS2205_VCC5) ? "off" : "on",
(reg & TPS2205_VPP_PGM) ? "off" : "on",
(reg & TPS2205_VPP_VCC) ? "off" : "on" );
cp->cp_pbdat = reg;
/* Wait 500 ms; use this to check for over-current */
for (i=0; i<5000; ++i) {
if ((cp->cp_pbdat & TPS2205_OC) == 0) {
printf (" *** Overcurrent - Safety shutdown ***\n");
cp->cp_pbdat &= ~(TPS2205_SHDN);
return (1);
}
udelay (100);
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* Shut down */
cp->cp_pbdat &= ~(TPS2205_SHDN);
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable,
* Turn all power pins to Hi-Z
*/
debug ("PCMCIA power OFF\n");
cfg_port_B (); /* Enables switch, but all in Hi-Z */
reg = cp->cp_pbdat;
switch(vcc) {
case 0: break; /* Switch off */
case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */
case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */
default: goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
cp->cp_pbdat = reg;
#ifdef DEBUG
{
char *s;
if ((reg & TPS2205_VCC3) == 0) {
s = "at 3.3V";
} else if ((reg & TPS2205_VCC5) == 0) {
s = "at 5.0V";
} else {
s = "down";
}
printf ("PCMCIA powered %s\n", s);
}
#endif
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

225
board/kup/common/pcmcia.c Normal file
View File

@ -0,0 +1,225 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "KUP"
#define KUP4K_PCMCIA_B_3V3 (0x00020000)
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(slot);
pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(2500);
/*
* Configure Port B pins for
* 3 Volts enable
*/
if (slot) { /* Slot A is built-in */
cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
/* remove all power */
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
}
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot);
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
if ((reg & mask) == mask) {
puts (" 5.0V card found: NOT SUPPORTED !!!\n");
} else {
if(slot)
cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
puts (" 3.3V card found: ");
}
#if 0
/* VCC switch error flag, PCMCIA slot INPACK_ pin */
cp->cp_pbdir &= ~(0x0020 | 0x0010);
cp->cp_pbpar &= ~(0x0020 | 0x0010);
udelay(500000);
#endif
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* remove all power */
if (slot)
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("voltage_set: " \
PCMCIA_BOARD_MSG \
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
if (!slot) /* Slot A is not configurable */
return 0;
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(slot);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug ("PCMCIA power OFF\n");
/*
* Configure Port B pins for
* 3 Volts enable
*/
cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
/* remove all power */
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
switch(vcc) {
case 0: break;
case 33:
cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
debug ("PCMCIA powered at 3.3V\n");
break;
case 50:
debug ("PCMCIA: 5Volt vcc not supported\n");
break;
default:
puts("PCMCIA: vcc not supported");
break;
}
udelay(10000);
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
? "only 5 V --> NOT SUPPORTED"
: "can do 3.3V");
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

2
board/kup/kup4k/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o
OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

2
board/kup/kup4x/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o
OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

2
board/lwmon/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

240
board/lwmon/pcmcia.c Normal file
View File

@ -0,0 +1,240 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#include <i2c.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "LWMON"
/* #define's for MAX1604 Power Switch */
#define MAX1604_OP_SUS 0x80
#define MAX1604_VCCBON 0x40
#define MAX1604_VCC_35 0x20
#define MAX1604_VCCBHIZ 0x10
#define MAX1604_VPPBON 0x08
#define MAX1604_VPPBPBPGM 0x04
#define MAX1604_VPPBHIZ 0x02
/* reserved 0x01 */
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
uchar val;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
/* Switch on PCMCIA port in PIC register 0x60 */
reg = pic_read (0x60);
debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
reg &= ~0x10;
/* reg |= 0x08; Vpp not needed */
pic_write (0x60, reg);
#ifdef DEBUG
reg = pic_read (0x60);
printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
#endif
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
if ((reg & mask) == mask) {
val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */
puts (" 5.0V card found: ");
} else {
val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */
puts (" 3.3V card found: ");
}
/* switch VCC on */
val |= MAX1604_OP_SUS | MAX1604_VCCBON;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
udelay(500000);
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
uchar val;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* remove all power, put output in high impedance state */
val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
/* Switch off PCMCIA port in PIC register 0x60 */
reg = pic_read (0x60);
debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
reg |= 0x10;
reg &= ~0x08;
pic_write (0x60, reg);
#ifdef DEBUG
reg = pic_read (0x60);
printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
#endif
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
uchar val;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Turn off all power (switch to high impedance)
*/
debug ("PCMCIA power OFF\n");
val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
val = 0;
switch(vcc) {
case 0: break;
case 33: val = MAX1604_VCC_35; break;
case 50: break;
default: goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
if (val) {
debug ("PCMCIA powered at %sV\n",
(val & MAX1604_VCC_35) ? "3.3" : "5.0");
} else {
debug ("PCMCIA powered down\n");
}
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

2
board/mbx8xx/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o vpd.o
OBJS = $(BOARD).o flash.o vpd.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

166
board/mbx8xx/pcmcia.c Normal file
View File

@ -0,0 +1,166 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#include "csr.h"
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
/* A lot of this has been taken from the RPX code in this file it works from me.
I have added the voltage selection for the MBX board. */
/* MBX voltage bit in control register #2 */
#define CR2_VPP12 ((uchar)0x10)
#define CR2_VPPVDD ((uchar)0x20)
#define CR2_VDD5 ((uchar)0x40)
#define CR2_VDD3 ((uchar)0x80)
#define PCMCIA_BOARD_MSG "MBX860"
int pcmcia_voltage_set (int slot, int vcc, int vpp)
{
uchar reg = 0;
debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10);
switch (vcc) {
case 0:
break;
case 33:
reg |= CR2_VDD3;
break;
case 50:
reg |= CR2_VDD5;
break;
default:
return 1;
}
switch (vpp) {
case 0:
break;
case 33:
case 50:
if (vcc == vpp) {
reg |= CR2_VPPVDD;
} else {
return 1;
}
break;
case 120:
reg |= CR2_VPP12;
break;
default:
return 1;
}
/* first, turn off all power */
MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL);
/* enable new powersettings */
MBX_CSR2 |= reg;
debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2);
return (0);
}
int pcmcia_hardware_enable (int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n",
'A' + slot);
udelay (10000);
immap = (immap_t *) CFG_IMMR;
sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (500);
/* remove all power */
pcmcia_voltage_set (slot, 0, 0);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
#ifndef CONFIG_HMI10
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
#else
if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
#endif /* CONFIG_HMI10 */
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
(reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
(reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
if ((reg & mask) == mask) {
pcmcia_voltage_set (_slot_, 50, 0);
printf (" 5.0V card found: ");
} else {
pcmcia_voltage_set (_slot_, 33, 0);
printf (" 3.3V card found: ");
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX (_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable (int slot)
{
return 0; /* No hardware to disable */
}
#endif /* CFG_CMD_PCMCIA */
#endif /* CONFIG_PCMCIA */

10
board/mcc200/config.mk
View File

@ -26,16 +26,18 @@
#
# Valid values for TEXT_BASE are:
#
# 0xFFF00000 boot high (standard configuration)
# 0xFE000000 boot low
# 0xFC000000 boot low (standard configuration)
# 0xFFF00000 boot high
# 0x00100000 boot from RAM (for testing only)
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
TEXT_BASE = 0xFFF00000
## Standard: boot low
TEXT_BASE = 0xFC000000
## Boot high
# TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
# TEXT_BASE = 0x00100000
endif

17
board/mcc200/mcc200.c
View File

@ -28,7 +28,16 @@
#include <mpc5xxx.h>
#include <pci.h>
#include "mt48lc8m32b2-6-7.h"
/* Two MT48LC8M32B2 for 32 MB */
/* #include "mt48lc8m32b2-6-7.h" */
/* One MT48LC16M32S2 for 64 MB */
/* #include "mt48lc16m32s2-75.h" */
#if defined (CONFIG_MCC200_SDRAM)
#include "mt48lc16m16a2-75.h"
#else
#include "mt46v16m16-75.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -74,6 +83,8 @@ static void sdram_start (int hi_addr)
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
udelay(10);
}
#endif
@ -242,8 +253,8 @@ int misc_init_r (void)
/* Unprotect the upper bank of the Flash */
*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
flash_protect (FLAG_PROTECT_CLEAR,
flash_info[0].start[0],
(flash_info[0].start[0] + flash_info[0].size) / 2 - 1,
flash_info[0].start[0] + flash_info[0].size / 2,
(flash_info[0].start[0] - 1) + flash_info[0].size,
&flash_info[0]);
*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
}

43
board/mcc200/mt48lc16m32s2-75.h Normal file
View File

@ -0,0 +1,43 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
#elif defined(CONFIG_MGT5100)
/* Settings for XLB = 66 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xC2222600
#define SDRAM_CONFIG2 0x88B70004
#define SDRAM_ADDRSEL 0x02000000
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

80
board/netstar/crcek.S
View File

@ -13,6 +13,7 @@
* u32 - crc32
*/
#include <config.h>
#include "crcek.h"
/**
@ -39,7 +40,7 @@
.macro crcuj, offset, size
mov r0, #0
ldr r1, \offset
ldr r2, [r1]
ldr r2, [r1], #4
cmp r2, r0 @ no data, no problem
beq 2f
tst r2, #3 @ unaligned size
@ -47,7 +48,6 @@
ldr r3, \size
cmp r2, r3 @ bogus size
bhi 2f
add r1, r1, #4
do_crc32
ldr r1, [r1]
2:
@ -55,16 +55,71 @@
.endm
.macro wait, reg
mov \reg, #0x1000
mov \reg, #0x100000
3:
subs \reg, \reg, #0x1
bne 3b
.endm
.text
.globl crcek
crcek:
b crc2_bad
/* Enable I-cache */
mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
mov r1, #0x00
mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
nop
nop
nop
nop
/* Setup clocking mode */
ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable
mov r2, #0
loop:
cmp r2, #1 @ this loop will wait for at least 100 cycles
streqh r1, [r0, #0x18] @ before issuing next request from MPU
add r2, r2, #1 @ on the 1st run code is loaded into I-cache
cmp r2, #16 @ and second run will set clocking mode
bne loop
nop
/* Setup clock dividers */
ldr r1, CKCTL_VAL
orr r1, r1, #0x2000 @ enable DSP clock
strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */
ldr r0, DPLL1_BASE @ base of DPLL1 register
mov r1, #0x0010 @ set PLL_ENABLE
orr r1, r1, #0x2000 @ set IOB to new locking
orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
strh r1, [r0] @ write
locking:
ldrh r1, [r0] @ get DPLL value
tst r1, #0x01
beq locking @ while LOCK not set
/* Enable clock */
ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
mov r1, #(1 << 10) @ disable idle mode do not check
@ nWAKEUP pin, other remain active
strh r1, [r0, #0x04]
ldr r1, EN_CLK_VAL
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
mov r6, #0
crcuj _LOADER1_OFFSET, _LOADER_SIZE
bne crc1_bad
@ -76,9 +131,8 @@ crc1_bad:
crc2_bad:
ldr r3, _LOADER1_OFFSET
ldr r4, _LOADER2_OFFSET
b boot_2nd
tst r6, #3
beq one_is_bad @ one of them (or both) has bad crc
teq r6, #3
bne one_is_bad @ one of them (or both) has bad crc
ldr r1, [r3, #4]
ldr r2, [r4, #4]
cmp r1, r2 @ boot 2nd loader if versions differ
@ -90,6 +144,7 @@ one_is_bad:
tst r6, #2
bne boot_2nd
@ We are doomed, so let user know.
hell:
ldr r0, GPIO_BASE @ configure GPIO pins
ldr r1, GPIO_DIRECTION
strh r1, [r0, #0x08]
@ -171,6 +226,15 @@ CRC32_TABLE:
GPIO_BASE:
.word 0xfffce000
MPU_CLKM_BASE:
.word 0xfffece00
DPLL1_BASE:
.word 0xfffecf00
CKCTL_VAL:
.word OMAP5910_ARM_CKCTL
EN_CLK_VAL:
.word OMAP5910_ARM_EN_CLK
GPIO_DIRECTION:
.word 0x0000ffe7

BIN
board/netstar/crcit
View File

Binary file not shown.

2
board/netstar/crcit.c
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@ -77,7 +77,7 @@ int main(int argc, char **argv)
} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
char *endptr, *nptr = argv[2];
unsigned ver = strtoul(nptr, &endptr, 0);
if (nptr != '\0' && endptr == '\0')
if (*nptr != '\0' && *endptr == '\0')
return doit(argv[3], ver);
}
fprintf(stderr, "Usage: crcit [-v version] <image>\n");

5
board/netstar/netstar.c
View File

@ -27,7 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* arch number of NetStar board */
/* TODO: use define from asm/mach-types.h */
gd->bd->bi_arch_number = 692;
/* adress of boot parameters */
@ -51,15 +50,11 @@ int dram_init(void)
return 0;
}
extern void partition_flash(void);
int misc_init_r(void)
{
return 0;
}
extern void nand_init(void);
int board_late_init(void)
{
return 0;

27
board/netstar/setup.S
View File

@ -145,25 +145,23 @@ lowlevel_init:
nop
/* Setup clocking mode */
ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
ldrh r1, [r0, #0x18] @ get reset status
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable
mov r2, #0 @ set wait counter to 100 clock cycles
icache_loop:
cmp r2, #0x01
streqh r1, [r0, #0x18]
add r2, r2, #0x01
cmp r2, #0x10
bne icache_loop
mov r2, #0
loop:
cmp r2, #1 @ this loop will wait for at least 100 cycles
streqh r1, [r0, #0x18] @ before issuing next request from MPU
add r2, r2, #1 @ on the 1st run code is loaded into I-cache
cmp r2, #16 @ and second run will set clocking mode
bne loop
nop
/* Setup clock divisors */
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
/* Setup clock dividers */
ldr r1, _OMAP5910_ARM_CKCTL
orr r1, r1, #0x2000 @ enable DSP clock
strh r1, [r0, #0x00] @ setup clock divisors
strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */
ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
@ -186,8 +184,7 @@ locking:
ldr r1, _OMAP5910_ARM_EN_CLK
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
@ max delayed ( 32 x CLKIN )
strh r1, [r0, #0x0c]
strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
/* Configure 5910 pins functions to match our board. */
ldr r0, MUX_CONFIG_BASE

2
board/netta/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o dsp.o codec.o
OBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

370
board/netta/pcmcia.c Normal file
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@ -0,0 +1,370 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
/* some sane bit macros */
#define _BD(_b) (1U << (31-(_b)))
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
#define _BW(_b) (1U << (15-(_b)))
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
#define _BB(_b) (1U << (7-(_b)))
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
#define _B(_b) _BD(_b)
#define _BR(_l, _h) _BDR(_l, _h)
#define PCMCIA_BOARD_MSG "NETTA"
static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
static void cfg_vppd(int no)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
return;
mask = vppd_masks[no];
immap->im_ioport.iop_papar &= ~mask;
immap->im_ioport.iop_paodr &= ~mask;
immap->im_ioport.iop_padir |= mask;
}
static void set_vppd(int no, int what)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
return;
mask = vppd_masks[no];
if (what)
immap->im_ioport.iop_padat |= mask;
else
immap->im_ioport.iop_padat &= ~mask;
}
static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
static void cfg_vccd(int no)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
return;
mask = vccd_masks[no];
immap->im_ioport.iop_papar &= ~mask;
immap->im_ioport.iop_paodr &= ~mask;
immap->im_ioport.iop_padir |= mask;
}
static void set_vccd(int no, int what)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
return;
mask = vccd_masks[no];
if (what)
immap->im_ioport.iop_padat |= mask;
else
immap->im_ioport.iop_padat &= ~mask;
}
static const unsigned short oc_mask = _BW(8);
static void cfg_oc(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask = oc_mask;
immap->im_ioport.iop_pcdir &= ~mask;
immap->im_ioport.iop_pcso &= ~mask;
immap->im_ioport.iop_pcint &= ~mask;
immap->im_ioport.iop_pcpar &= ~mask;
}
static int get_oc(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask = oc_mask;
int what;
what = !!(immap->im_ioport.iop_pcdat & mask);;
return what;
}
static const unsigned short shdn_mask = _BW(12);
static void cfg_shdn(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
mask = shdn_mask;
immap->im_ioport.iop_papar &= ~mask;
immap->im_ioport.iop_paodr &= ~mask;
immap->im_ioport.iop_padir |= mask;
}
static void set_shdn(int what)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
mask = shdn_mask;
if (what)
immap->im_ioport.iop_padat |= mask;
else
immap->im_ioport.iop_padat &= ~mask;
}
static void cfg_ports (void)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */
cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */
cfg_shdn();
cfg_oc();
/*
* Configure Port A for TPS2211 PC-Card Power-Interface Switch
*
* Switch off all voltages, assert shutdown
*/
set_vppd(0, 1); set_vppd(1, 1);
set_vccd(0, 0); set_vccd(1, 0);
set_shdn(1);
udelay(100000);
}
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, pipr, mask;
int i;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
cfg_ports ();
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
pipr = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
pipr,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
if ((pipr & mask) == mask) {
set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */
puts (" 5.0V card found: ");
} else {
set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */
puts (" 3.3V card found: ");
}
/* Wait 500 ms; use this to check for over-current */
for (i=0; i<5000; ++i) {
if (!get_oc()) {
printf (" *** Overcurrent - Safety shutdown ***\n");
set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */
return (1);
}
udelay (100);
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
/* All voltages off / Hi-Z */
set_vppd(0, 1); set_vppd(1, 1);
set_vccd(0, 1); set_vccd(1, 1);
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
ushort sreg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable,
* Turn all power pins to Hi-Z
*/
debug ("PCMCIA power OFF\n");
cfg_ports (); /* Enables switch, but all in Hi-Z */
sreg = immap->im_ioport.iop_pcdat;
set_vppd(0, 1); set_vppd(1, 1);
switch(vcc) {
case 0:
break; /* Switch off */
case 33:
set_vccd(0, 1); set_vccd(1, 0);
break;
case 50:
set_vccd(0, 0); set_vccd(1, 1);
break;
default:
goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

47
board/ppmc7xx/Makefile Normal file
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@ -0,0 +1,47 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := ppmc7xx.o pci.o flash.o
SOBJS := init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

28
board/ppmc7xx/config.mk Normal file
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@ -0,0 +1,28 @@
#
# (C) Copyright 2005
# Richard Danter, Wind River Systems
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
TEXT_BASE = 0xFFF00000
TEXT_END = 0xFFF40000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

494
board/ppmc7xx/flash.c Normal file
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@ -0,0 +1,494 @@
/*
* flash.c
* -------
*
* Flash programming routines for the Wind River PPMC 74xx/7xx
* based on flash.c from the TQM8260 board.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#include <common.h>
#include <asm/processor.h>
#include <74xx_7xx.h>
#define DWORD unsigned long long
/* Local function prototypes */
static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
static void write_via_fpu (volatile DWORD* addr, DWORD* data);
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
*/
void flash_reset (void)
{
unsigned long msr;
DWORD cmd_reset = 0x00F000F000F000F0LL;
if (flash_info[0].flash_id != FLASH_UNKNOWN) {
msr = get_msr ();
set_msr (msr | MSR_FP);
write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
set_msr (msr);
}
}
/*-----------------------------------------------------------------------
*/
ulong flash_get_size (ulong baseaddr, flash_info_t * info)
{
int i;
unsigned long msr;
DWORD flashtest;
DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x0090009000900090LL };
/* Enable FPU */
msr = get_msr ();
set_msr (msr | MSR_FP);
/* Write auto-select command sequence */
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
/* Restore FPU */
set_msr (msr);
/* Read manufacturer ID */
flashtest = *(volatile DWORD*)baseaddr;
switch ((int)flashtest) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
/* No, faulty or unknown flash */
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0);
}
/* Read device ID */
flashtest = *(volatile DWORD*)(baseaddr + 8);
switch ((long)flashtest) {
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00400000;
break;
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00400000;
break;
case AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00800000;
break;
case AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00800000;
break;
case AMD_ID_DL322T:
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL322B:
info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL323T:
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL323B:
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_LV640U:
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x02000000;
break;
default:
/* Unknown flash type */
info->flash_id = FLASH_UNKNOWN;
return (0);
}
if ((long)flashtest == AMD_ID_LV640U) {
/* set up sector start adress table (uniform sector type) */
for (i = 0; i < info->sector_count; i++)
info->start[i] = baseaddr + (i * 0x00040000);
} else if (info->flash_id & FLASH_BTYPE) {
/* set up sector start adress table (bottom sector type) */
info->start[0] = baseaddr + 0x00000000;
info->start[1] = baseaddr + 0x00010000;
info->start[2] = baseaddr + 0x00018000;
info->start[3] = baseaddr + 0x00020000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
}
} else {
/* set up sector start adress table (top sector type) */
i = info->sector_count - 1;
info->start[i--] = baseaddr + info->size - 0x00010000;
info->start[i--] = baseaddr + info->size - 0x00018000;
info->start[i--] = baseaddr + info->size - 0x00020000;
for (; i >= 0; i--) {
info->start[i] = baseaddr + i * 0x00040000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
info->protect[i] = 1; /* D0 = 1 if protected */
} else {
info->protect[i] = 0;
}
}
flash_reset ();
return (info->size);
}
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0 = 0;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here (only one bank) */
size_b0 = flash_get_size (CFG_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 >> 20);
}
/*
* protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
#endif
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf ("AMD ");
break;
case FLASH_MAN_FUJ:
printf ("FUJITSU ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM800T:
printf ("29LV800T (8 M, top sector)\n");
break;
case FLASH_AM800B:
printf ("29LV800T (8 M, bottom sector)\n");
break;
case FLASH_AM160T:
printf ("29LV160T (16 M, top sector)\n");
break;
case FLASH_AM160B:
printf ("29LV160B (16 M, bottom sector)\n");
break;
case FLASH_AMDL322T:
printf ("29DL322T (32 M, top sector)\n");
break;
case FLASH_AMDL322B:
printf ("29DL322B (32 M, bottom sector)\n");
break;
case FLASH_AMDL323T:
printf ("29DL323T (32 M, top sector)\n");
break;
case FLASH_AMDL323B:
printf ("29DL323B (32 M, bottom sector)\n");
break;
case FLASH_AM640U:
printf ("29LV640D (64 M, uniform sector)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect, l_sect;
ulong start, now, last;
unsigned long msr;
DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x0080008000800080LL, 0x00AA00AA00AA00AALL,
0x0055005500550055LL, 0x0030003000300030LL };
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect])
prot++;
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Enable FPU */
msr = get_msr();
set_msr ( msr | MSR_FP );
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
udelay (1000);
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* Restore FPU */
set_msr (msr);
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
!= 0x0080008000800080LL )
{
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
serial_putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
flash_reset ();
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong dp;
static unsigned char bb[8];
int i, l, rc, cc = cnt;
dp = (addr & ~7); /* get lower dword aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - dp) != 0) {
for (i = 0; i < 8; i++)
bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
if ((rc = write_dword (info, dp, bb)) != 0) {
return (rc);
}
dp += 8;
cc -= 8 - l;
}
/*
* handle word aligned part
*/
while (cc >= 8) {
if ((rc = write_dword (info, dp, src)) != 0) {
return (rc);
}
dp += 8;
src += 8;
cc -= 8;
}
if (cc <= 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
for (i = 0; i < 8; i++) {
bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
}
return (write_dword (info, dp, bb));
}
/*-----------------------------------------------------------------------
* Write a dword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
{
ulong start;
unsigned long msr;
int flag, i;
DWORD data;
DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x00A000A000A000A0LL };
for (data = 0, i = 0; i < 8; i++)
data = (data << 8) + *pdata++;
/* Check if Flash is (sufficiently) erased */
if ((*(DWORD*)dest & data) != data) {
return (2);
}
/* Enable FPU */
msr = get_msr();
set_msr( msr | MSR_FP );
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
write_via_fpu ((DWORD*)dest, &data );
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* Restore FPU */
set_msr(msr);
/* data polling for D7 */
start = get_timer (0);
while (*(volatile DWORD*)dest != data ) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/
static void write_via_fpu (volatile DWORD* addr, DWORD* data)
{
__asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
__asm__ __volatile__ ("eieio");
}

336
board/ppmc7xx/init.S Normal file
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/*
* init.S
* ------
*
* Wind River PPMC 7xx/74xx init code.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*
* NOTE: The following code was generated automatically by Workbench
* from the ppmc7400_107.reg register file.
*/
#include <ppc_asm.tmpl>
.globl board_asm_init
board_asm_init:
lis r4,0xFEC0
ori r4,r4,0x0000
lis r5,0xFEE0
ori r5,r5,0x0000
lis r3,0x8000 # ADDR_00
ori r3,r3,0x0000
stwbrx r3,0,r4
li r3,0x1057 # VENDOR
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_02
ori r3,r3,0x0002
stwbrx r3,0,r4
li r3,0x0004 # ID
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_04
ori r3,r3,0x0004
stwbrx r3,0,r4
li r3,0x0006 # PCICMD
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_06
ori r3,r3,0x0006
stwbrx r3,0,r4
li r3,0x00A0 # PCISTAT
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_08
ori r3,r3,0x0008
stwbrx r3,0,r4
li r3,0x10 # REVID
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_09
ori r3,r3,0x0009
stwbrx r3,0,r4
li r3,0x00 # PROGIR
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_0A
ori r3,r3,0x000A
stwbrx r3,0,r4
li r3,0x00 # SUBCCODE
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_0B
ori r3,r3,0x000B
stwbrx r3,0,r4
li r3,0x06 # PBCCR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_0C
ori r3,r3,0x000C
stwbrx r3,0,r4
li r3,0x08 # PCLSR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_0D
ori r3,r3,0x000D
stwbrx r3,0,r4
li r3,0x00 # PLTR
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_0E
ori r3,r3,0x000E
stwbrx r3,0,r4
li r3,0x00 # HEADTYPE
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_0F
ori r3,r3,0x000F
stwbrx r3,0,r4
li r3,0x00 # BISTCTRL
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_10
ori r3,r3,0x0010
stwbrx r3,0,r4
lis r3,0x0000 # LMBAR
ori r3,r3,0x0008
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_14
ori r3,r3,0x0014
stwbrx r3,0,r4
lis r3,0xF000 # PCSRBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_3C
ori r3,r3,0x003C
stwbrx r3,0,r4
li r3,0x00 # ILR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_3D
ori r3,r3,0x003D
stwbrx r3,0,r4
li r3,0x01 # INTPIN
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_3E
ori r3,r3,0x003E
stwbrx r3,0,r4
li r3,0x00 # MIN_GNT
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_3F
ori r3,r3,0x003F
stwbrx r3,0,r4
li r3,0x00 # MAX_LAT
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_40
ori r3,r3,0x0040
stwbrx r3,0,r4
li r3,0x00 # BUSNB
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_41
ori r3,r3,0x0041
stwbrx r3,0,r4
li r3,0x00 # SBUSNB
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_46
ori r3,r3,0x0046
stwbrx r3,0,r4
# li r3,0xE080 # PCIARB
li r3,-0x1F80 # PCIARB
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_70
ori r3,r3,0x0070
stwbrx r3,0,r4
li r3,0x0000 # PMCR1
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_72
ori r3,r3,0x0072
stwbrx r3,0,r4
li r3,0xC0 # PMCR2
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_73
ori r3,r3,0x0073
stwbrx r3,0,r4
li r3,0xEF # ODCR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_74
ori r3,r3,0x0074
stwbrx r3,0,r4
li r3,0x7D00 # CLKDCR
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_76
ori r3,r3,0x0076
stwbrx r3,0,r4
li r3,0x00 # MDCR
stb r3,0x2(r5)
lis r6,0xFCE0
ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
lis r3,0x8000 # ADDR_78
ori r3,r3,0x0078
stwbrx r3,0,r4
lis r3,0xFCE0 # EUMBBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_80
ori r3,r3,0x0080
stwbrx r3,0,r4
lis r3,0xFFFF # MSADDR1
ori r3,r3,0x4000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_84
ori r3,r3,0x0084
stwbrx r3,0,r4
lis r3,0xFFFF # MSADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_88
ori r3,r3,0x0088
stwbrx r3,0,r4
lis r3,0x0303 # EMSADDR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_8C
ori r3,r3,0x008C
stwbrx r3,0,r4
lis r3,0x0303 # EMSADDR2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_90
ori r3,r3,0x0090
stwbrx r3,0,r4
lis r3,0xFFFF # EMEADDR1
ori r3,r3,0x7F3F
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_94
ori r3,r3,0x0094
stwbrx r3,0,r4
lis r3,0xFFFF # EMEADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_98
ori r3,r3,0x0098
stwbrx r3,0,r4
lis r3,0x0303 # EXTEMEM1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_9C
ori r3,r3,0x009C
stwbrx r3,0,r4
lis r3,0x0303 # EXTEMEM2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_A0
ori r3,r3,0x00A0
stwbrx r3,0,r4
li r3,0x03 # MEMBNKEN
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_A3
ori r3,r3,0x00A3
stwbrx r3,0,r4
li r3,0x00 # MEMPMODE
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_B8
ori r3,r3,0x00B8
stwbrx r3,0,r4
li r3,0x00 # ECCCNT
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_B9
ori r3,r3,0x00B9
stwbrx r3,0,r4
li r3,0x00 # ECCTRG
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C0
ori r3,r3,0x00C0
stwbrx r3,0,r4
li r3,0xFF # ERRENR1
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_C1
ori r3,r3,0x00C1
stwbrx r3,0,r4
li r3,0x00 # ERRDR1
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C3
ori r3,r3,0x00C3
stwbrx r3,0,r4
li r3,0x50 # IPBESR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_C4
ori r3,r3,0x00C4
stwbrx r3,0,r4
li r3,0xBF # ERRENR2
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_C5
ori r3,r3,0x00C5
stwbrx r3,0,r4
li r3,0x00 # ERRDR2
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C7
ori r3,r3,0x00C7
stwbrx r3,0,r4
li r3,0x00 # PCIBESR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_C8
ori r3,r3,0x00C8
stwbrx r3,0,r4
lis r3,0x0000 # BERRADDR
ori r3,r3,0xE0FE
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_E0
ori r3,r3,0x00E0
stwbrx r3,0,r4
li r3,0xC0 # AMBOR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_F4
ori r3,r3,0x00F4
stwbrx r3,0,r4
lis r3,0x0000 # MCCR2
ori r3,r3,0x020C
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_F8
ori r3,r3,0x00F8
stwbrx r3,0,r4
lis r3,0x0230 # MCCR3
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_FC
ori r3,r3,0x00FC
stwbrx r3,0,r4
lis r3,0x2532 # MCCR4
ori r3,r3,0x2220
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_F0
ori r3,r3,0x00F0
stwbrx r3,0,r4
lis r3,0xFFC8 # MCCR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_A8
ori r3,r3,0x00A8
stwbrx r3,0,r4
lis r3,0xFF14 # PICR1
ori r3,r3,0x1CC8
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_AC
ori r3,r3,0x00AC
stwbrx r3,0,r4
lis r3,0x0000 # PICR2
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
blr

97
board/ppmc7xx/pci.c Normal file
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/*
* (C) Copyright 2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCI initialisation for the MPC10x.
*/
#include <common.h>
#include <pci.h>
#include <mpc106.h>
#ifdef CONFIG_PCI
struct pci_controller local_hose;
void pci_init_board(void)
{
struct pci_controller* hose = (struct pci_controller *)&local_hose;
u16 reg16;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CFG_PCI_MEM_BUS,
CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* ISA/PCI memory space */
pci_set_region(hose->regions + 2,
CFG_ISA_MEM_BUS,
CFG_ISA_MEM_PHYS,
CFG_ISA_MEM_SIZE,
PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region(hose->regions + 3,
CFG_PCI_IO_BUS,
CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE,
PCI_REGION_IO);
/* ISA/PCI I/O space */
pci_set_region(hose->regions + 4,
CFG_ISA_IO_BUS,
CFG_ISA_IO_PHYS,
CFG_ISA_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 5;
pci_setup_indirect(hose,
MPC106_REG_ADDR,
MPC106_REG_DATA);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
/* Initialises the MPC10x PCI Configuration regs. */
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
/* Clear non-reserved bits in status register */
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
}
#endif /* CONFIG_PCI */

104
board/ppmc7xx/ppmc7xx.c Normal file
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/*
* ppmc7xx.c
* ---------
*
* Main board-specific routines for Wind River PPMC 7xx/74xx board.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#include <common.h>
#include <command.h>
/* Define some MPC107 (memory controller) registers */
#define MPC107_EUMB_GCR 0xfce41020
#define MPC107_EUMB_IACKR 0xfce600a0
/* Function prototypes */
extern void unlock_ram_in_cache( void );
extern void _start_warm(void);
/*
* initdram()
*
* This function normally initialises the (S)DRAM of the system. For this board
* the SDRAM was already initialised by board_asm_init (see init.S) so we just
* return the size of RAM.
*/
long initdram( int board_type )
{
return CFG_SDRAM_SIZE;
}
/*
* after_reloc()
*
* This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
* us an opportunity to do some additional setup before the rest of the system
* is initialised. We don't need to do anything, so we just call board_init_r()
* which should never return.
*/
void after_reloc( ulong dest_addr, gd_t* gd )
{
/* Jump to the main U-Boot board init code */
board_init_r( gd, dest_addr );
}
/*
* checkboard()
*
* We could do some board level checks here, such as working out what version
* it is, but for this board we simply display it's name (on the console).
*/
int checkboard( void )
{
puts( "Board: Wind River PPMC 7xx/74xx\n" );
return 0;
}
/*
* misc_init_r
*
* Used for other setup which needs to be done late in the bring-up phase.
*/
int misc_init_r( void )
{
/* Reset the EPIC and clear pending interrupts */
out32r(MPC107_EUMB_GCR, 0xa0000000);
while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
out32r( MPC107_EUMB_GCR, 0x20000000 );
while( in32r( MPC107_EUMB_IACKR ) != 0xff );
/* Enable the I-Cache */
icache_enable();
return 0;
}
/*
* do_reset()
*
* Shell command to reset the board.
*/
void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
{
printf( "Resetting...\n" );
/* Disabe and invalidate cache */
icache_disable();
dcache_disable();
/* Jump to warm start (in RAM) */
_start_warm();
/* Should never get here */
while(1);
}

135
board/ppmc7xx/u-boot.lds Normal file
View File

@ -0,0 +1,135 @@
/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

57
board/psyent/common/AMDLV065D.c
View File

@ -26,7 +26,7 @@
#if defined(CONFIG_NIOS)
#include <nios.h>
#else
#include <nios2.h>
#include <asm/io.h>
#endif
#define SECTSZ (64 * 1024)
@ -56,9 +56,8 @@ unsigned long flash_init (void)
void flash_print_info (flash_info_t * info)
{
int i, k;
unsigned long size;
int erased;
volatile unsigned char *flash;
unsigned long *addr;
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
@ -66,14 +65,10 @@ void flash_print_info (flash_info_t * info)
for (i = 0; i < info->sector_count; ++i) {
/* Check if whole sector is erased */
if (i != (info->sector_count - 1))
size = info->start[i + 1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]);
for (k = 0; k < size; k++) {
if (*flash++ != 0xff) {
addr = (unsigned long *) info->start[i];
for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
if ( readl(addr++) != (unsigned long)-1) {
erased = 0;
break;
}
@ -83,7 +78,7 @@ void flash_print_info (flash_info_t * info)
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s%s",
CACHE_NO_BYPASS(info->start[i]),
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " ");
}
@ -95,9 +90,8 @@ void flash_print_info (flash_info_t * info)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)
CACHE_BYPASS(info->start[0]);
volatile CFG_FLASH_WORD_SIZE *addr2;
unsigned char *addr = (unsigned char *) info->start[0];
unsigned char *addr2;
int prot, sect;
ulong start;
@ -127,19 +121,18 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
*/
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CFG_FLASH_WORD_SIZE *)
CACHE_BYPASS((info->start[sect]));
*addr = 0xaa;
*addr = 0x55;
*addr = 0x80;
*addr = 0xaa;
*addr = 0x55;
*addr2 = 0x30;
addr2 = (unsigned char *) info->start[sect];
writeb (addr, 0xaa);
writeb (addr, 0x55);
writeb (addr, 0x80);
writeb (addr, 0xaa);
writeb (addr, 0x55);
writeb (addr2, 0x30);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
start = get_timer (0);
while (*addr2 != 0xff) {
while ( readb (addr2) != 0xff) {
udelay (1000 * 1000);
putc ('.');
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
@ -163,27 +156,27 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]);
vu_char *dst = (vu_char *) CACHE_BYPASS(addr);
vu_char *cmd = (vu_char *) info->start[0];
vu_char *dst = (vu_char *) addr;
unsigned char b;
ulong start;
while (cnt) {
/* Check for sufficient erase */
b = *src;
if ((*dst & b) != b) {
printf ("%02x : %02x\n", *dst, b);
if ((readb (dst) & b) != b) {
printf ("%02x : %02x\n", readb (dst), b);
return (2);
}
*cmd = 0xaa;
*cmd = 0x55;
*cmd = 0xa0;
*dst = b;
writeb (cmd, 0xaa);
writeb (cmd, 0x55);
writeb (cmd, 0xa0);
writeb (dst, b);
/* Verify write */
start = get_timer (0);
while (*dst != b) {
while (readb (dst) != b) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return 1;
}

2
board/psyent/pk1c20/config.mk
View File

@ -21,7 +21,7 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0x018e0000
TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include

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