ppc4xx: Add T3COPR board support (PPC460GT based)
This patch adds support for the T3CORP board, based on the AppliedMicro (APM) PPC460GT. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
4978e60584
commit
273ed0370d
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@ -392,6 +392,7 @@ Stefan Roese <sr@denx.de>
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rainier PPC440GRx
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sequoia PPC440EPx
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sycamore PPC405GPr
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t3corp PPC460GT
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taishan PPC440GX
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walnut PPC405GP
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yellowstone PPC440GR
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1
MAKEALL
1
MAKEALL
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@ -262,6 +262,7 @@ LIST_4xx=" \
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sc3 \
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sequoia \
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sequoia_nand \
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t3corp \
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taihu \
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taishan \
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v5fx30teval \
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@ -0,0 +1,53 @@
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#
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# (C) Copyright 2010
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
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SOBJS := init.o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,59 @@
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/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/ppc4xx_config.h>
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struct ppc4xx_config ppc4xx_config_val[] = {
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{
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"600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
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{
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0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
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{
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0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"1000", "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
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{
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0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"1066", "CPU:1066 PLB: 266 OPB: 88 EBC: 88",
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{
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0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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}
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},
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};
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int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
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@ -0,0 +1,39 @@
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#
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# (C) Copyright 2010
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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ifndef TEXT_BASE
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TEXT_BASE = 0xFFFA0000
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endif
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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endif
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ifeq ($(dbcr),1)
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif
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@ -0,0 +1,99 @@
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/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <config.h>
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#include <asm/mmu.h>
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/*
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/*
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
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* use the speed up boot process. It is patched after relocation to
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* enable SA_I
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*/
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
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CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
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/*
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* TLB entries for SDRAM are not needed on this platform.
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* They are dynamically generated in the DDR(2) detection
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* routine.
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*/
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#ifdef CONFIG_SYS_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
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AC_RWX | SA_G)
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#endif
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
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AC_RW | SA_IG)
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/* PCIe UTL register */
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tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
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/* TLB-entry for FPGA(s) */
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tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4,
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AC_RW | SA_IG)
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/* TLB-entry for OCM */
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tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
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AC_RWX | SA_I)
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/* TLB-entry for Local Configuration registers => peripherals */
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tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
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CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
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tlbtab_end
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@ -0,0 +1,193 @@
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/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc440.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/4xx_pcie.h>
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#include <asm/gpio.h>
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int board_early_init_f(void)
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{
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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mtdcr(UIC3ER, 0x00000000); /* disable all */
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mtdcr(UIC3CR, 0x00000000); /* all non-critical */
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mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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/*
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* Configure PFC (Pin Function Control) registers
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* enable GPIO 49-63
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* UART0: 4 pins
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*/
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mtsdr(SDR0_PFC0, 0x00007fff);
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mtsdr(SDR0_PFC1, 0x00040000);
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/* Enable PCI host functionality in SDR0_PCI0 */
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mtsdr(SDR0_PCI0, 0xe0000000);
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mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
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/* Setup PLB4-AHB bridge based on the system address map */
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mtdcr(AHB_TOP, 0x8000004B);
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mtdcr(AHB_BOT, 0x8000004B);
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: T3CORP");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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int board_early_init_r(void)
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{
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/*
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* T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
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* boot EBC mapping only supports a maximum of 16MBytes
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* (4.ff00.0000 - 4.ffff.ffff).
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* To solve this problem, the flash has to get remapped to another
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* EBC address which accepts bigger regions:
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*
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* 0xfn00.0000 -> 4.cn00.0000
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*/
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/* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
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mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
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EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
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/* Remove TLB entry of boot EBC mapping */
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remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
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/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
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program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
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CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
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/*
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* Now accessing of the whole 64Mbytes of NOR flash at virtual address
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* 0xfc00.0000 is possible
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*/
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/*
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* Clear potential errors resulting from auto-calibration.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return 0;
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}
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int misc_init_r(void)
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{
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u32 sdr0_srst1 = 0;
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u32 eth_cfg;
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/*
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* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
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* This is board specific, so let's do it here.
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*/
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mfsdr(SDR0_ETH_CFG, eth_cfg);
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/* disable SGMII mode */
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eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
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SDR0_ETH_CFG_SGMII1_ENABLE |
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SDR0_ETH_CFG_SGMII0_ENABLE);
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/* Set the for 2 RGMII mode */
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/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
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eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
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eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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mtsdr(SDR0_ETH_CFG, eth_cfg);
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/*
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* The AHB Bridge core is held in reset after power-on or reset
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* so enable it now
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*/
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mfsdr(SDR0_SRST1, sdr0_srst1);
|
||||
sdr0_srst1 &= ~SDR0_SRST1_AHB;
|
||||
mtsdr(SDR0_SRST1, sdr0_srst1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_pcie_last(void)
|
||||
{
|
||||
/*
|
||||
* Only PCIe0 for now, PCIe1 hangs on this board
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Board specific WRDTR and CLKTR values used by the auto-
|
||||
* calibration code (4xx_ibm_ddr2_autocalib.c).
|
||||
*/
|
||||
static struct sdram_timing board_scan_options[] = {
|
||||
{1, 2},
|
||||
{-1, -1}
|
||||
};
|
||||
|
||||
struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
|
||||
{
|
||||
return board_scan_options;
|
||||
}
|
||||
|
|
@ -183,6 +183,7 @@ lwmon5 powerpc ppc4xx
|
|||
ML2 powerpc ppc4xx
|
||||
sbc405 powerpc ppc4xx
|
||||
sc3 powerpc ppc4xx
|
||||
t3corp powerpc ppc4xx
|
||||
zeus powerpc ppc4xx
|
||||
acadia powerpc ppc4xx - amcc
|
||||
bamboo powerpc ppc4xx - amcc
|
||||
|
|
|
|||
|
|
@ -0,0 +1,544 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* t3corp.h - configuration for T3CORP (460GT)
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_460GT 1 /* Specific PPC460GT */
|
||||
#define CONFIG_440 1
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
|
||||
#define CONFIG_HOSTNAME t3corp
|
||||
|
||||
/*
|
||||
* Include common defines/options for all AMCC/APM eval boards
|
||||
*/
|
||||
#include "amcc-common.h"
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */
|
||||
#define CONFIG_FIT
|
||||
#define CFG_ALT_MEMTEST
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
|
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
|
||||
|
||||
#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe mem */
|
||||
#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe */
|
||||
#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
|
||||
|
||||
#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
|
||||
#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
|
||||
#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
|
||||
#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
|
||||
|
||||
#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit phys addr */
|
||||
|
||||
/* base address of inbound PCIe window */
|
||||
#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit phys addr */
|
||||
|
||||
/* EBC stuff */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
|
||||
#define CONFIG_SYS_FLASH_SIZE (64 << 20)
|
||||
|
||||
#define CONFIG_SYS_FPGA1_BASE 0xe0000000
|
||||
#define CONFIG_SYS_FPGA2_BASE 0xe0100000
|
||||
#define CONFIG_SYS_FPGA3_BASE 0xe0200000
|
||||
|
||||
#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS \
|
||||
(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
|
||||
| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
|
||||
|
||||
#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
|
||||
#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
|
||||
#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
|
||||
|
||||
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */
|
||||
|
||||
#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
|
||||
|
||||
/*
|
||||
* Initial RAM & stack pointer (placed in OCM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
|
||||
#define CONFIG_SYS_INIT_RAM_END (4 << 10)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
/*
|
||||
* Define here the location of the environment variables (flash).
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH /* use flash for environment vars */
|
||||
|
||||
/*
|
||||
* Flash related
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buff'd writes (20x faster)*/
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* sector size */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - \
|
||||
CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* env sector size */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
/*
|
||||
* DDR2 SDRAM
|
||||
*/
|
||||
#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
|
||||
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
|
||||
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
|
||||
#undef CONFIG_PPC4xx_DDR_METHOD_A
|
||||
|
||||
/* DDR1/2 SDRAM Device Control Register Data Values */
|
||||
/* Memory Queue */
|
||||
#define CONFIG_SYS_SDRAM_R0BAS (SDRAM_RXBAS_SDBA_ENCODE(0) | \
|
||||
SDRAM_RXBAS_SDSZ_256)
|
||||
#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
|
||||
#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
|
||||
#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
|
||||
#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
|
||||
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_SYS_MBYTES_SDRAM 256
|
||||
|
||||
#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK
|
||||
|
||||
/* DDR1/2 SDRAM Device Control Register Data Values */
|
||||
#define CONFIG_SYS_SDRAM0_MB0CF (SDRAM_RXBAS_SDAM_MODE7 | \
|
||||
SDRAM_RXBAS_SDBE_ENABLE)
|
||||
#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
|
||||
#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
|
||||
#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
|
||||
#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_MCHK_GEN | \
|
||||
SDRAM_MCOPT1_PMU_OPEN | \
|
||||
SDRAM_MCOPT1_DMWD_32 | \
|
||||
SDRAM_MCOPT1_8_BANKS | \
|
||||
SDRAM_MCOPT1_DDR2_TYPE | \
|
||||
SDRAM_MCOPT1_QDEP | \
|
||||
SDRAM_MCOPT1_RWOO_DISABLED | \
|
||||
SDRAM_MCOPT1_WOOO_DISABLED | \
|
||||
SDRAM_MCOPT1_DREF_NORMAL)
|
||||
#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
|
||||
#define CONFIG_SYS_SDRAM0_MODT0 SDRAM_MODT_EB0W_ENABLE
|
||||
#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
|
||||
#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
|
||||
#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
|
||||
#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
|
||||
SDRAM_CODT_DQS_1_8_V_DDR2 | \
|
||||
SDRAM_CODT_IO_NMODE)
|
||||
#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR0 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(80) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR1 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(3) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR2 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR3 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(0))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR4 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE | \
|
||||
JEDEC_MA_EMR_RTT_150OHM))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR5 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(200) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
|
||||
CAS_LATENCY | \
|
||||
JEDEC_MA_MR_BLEN_4 | \
|
||||
JEDEC_MA_MR_DLL_RESET))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR6 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(3) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(0x0) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR7 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(26) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR8 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(26) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR9 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(26) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR10 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(26) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR11 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
|
||||
CAS_LATENCY | \
|
||||
JEDEC_MA_MR_BLEN_4))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR12 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
|
||||
JEDEC_MA_EMR_RDQS_DISABLE | \
|
||||
JEDEC_MA_EMR_DQS_ENABLE | \
|
||||
JEDEC_MA_EMR_RTT_150OHM | \
|
||||
JEDEC_MA_EMR_ODS_NORMAL))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR13 \
|
||||
(SDRAM_INITPLR_ENABLE | \
|
||||
SDRAM_INITPLR_IMWT_ENCODE(2) | \
|
||||
SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
|
||||
SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
|
||||
SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
|
||||
JEDEC_MA_EMR_RDQS_DISABLE | \
|
||||
JEDEC_MA_EMR_DQS_ENABLE | \
|
||||
JEDEC_MA_EMR_RTT_150OHM | \
|
||||
JEDEC_MA_EMR_ODS_NORMAL))
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR14 SDRAM_INITPLR_DISABLE
|
||||
#define CONFIG_SYS_SDRAM0_INITPLR15 SDRAM_INITPLR_DISABLE
|
||||
#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
|
||||
SDRAM_RQDC_RQFD_ENCODE(56))
|
||||
#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(599)
|
||||
#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
|
||||
#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
|
||||
SDRAM_DLCR_DLCS_CONT_DONE | \
|
||||
SDRAM_DLCR_DLCV_ENCODE(155))
|
||||
#define CONFIG_SYS_SDRAM0_CLKTR SDRAM_CLKTR_CLKP_90_DEG_ADV
|
||||
#define CONFIG_SYS_SDRAM0_WRDTR SDRAM_WRDTR_WTR_90_DEG_ADV
|
||||
#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
|
||||
SDRAM_SDTR1_RTW_2_CLK | \
|
||||
SDRAM_SDTR1_RTRO_1_CLK)
|
||||
#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
|
||||
SDRAM_SDTR2_WTR_2_CLK | \
|
||||
SDRAM_SDTR2_XSNR_32_CLK | \
|
||||
SDRAM_SDTR2_WPC_4_CLK | \
|
||||
SDRAM_SDTR2_RPC_2_CLK | \
|
||||
SDRAM_SDTR2_RP_3_CLK | \
|
||||
SDRAM_SDTR2_RRD_2_CLK)
|
||||
#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
|
||||
SDRAM_SDTR3_RC_ENCODE(11) | \
|
||||
SDRAM_SDTR3_XCS | \
|
||||
SDRAM_SDTR3_RFC_ENCODE(26))
|
||||
#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
|
||||
CAS_LATENCY | \
|
||||
SDRAM_MMODE_BLEN_4)
|
||||
#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_ENABLE | \
|
||||
SDRAM_MEMODE_RTT_150OHM)
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
|
||||
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
/* I2C bootstrap EEPROM */
|
||||
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
|
||||
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
|
||||
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define CONFIG_IBM_EMAC4_V4 1
|
||||
|
||||
#define CONFIG_HAS_ETH0
|
||||
|
||||
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
|
||||
#define CONFIG_M88E1111_PHY
|
||||
/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
|
||||
#define CONFIG_M88E1111_DISABLE_FIBER
|
||||
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
#define CONFIG_PHY_DYNAMIC_ANEG 1
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_AMCC_DEF_ENV \
|
||||
CONFIG_AMCC_DEF_ENV_POWERPC \
|
||||
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
||||
"kernel_addr=fc000000\0" \
|
||||
"fdt_addr=fc1e0000\0" \
|
||||
"ramdisk_addr=fc200000\0" \
|
||||
"pciconfighost=1\0" \
|
||||
"pcie_mode=RP:RP\0" \
|
||||
""
|
||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h
|
||||
*/
|
||||
#define CONFIG_CMD_CHIP_CONFIG
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
/*
|
||||
* PCI stuff
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
|
||||
|
||||
/* Board-specific PCI, no PCI support, only PCIe */
|
||||
#undef CONFIG_SYS_PCI_TARGET_INIT
|
||||
#undef CONFIG_SYS_PCI_MASTER_INIT
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/*
|
||||
* T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
|
||||
* boot EBC mapping only supports a maximum of 16MBytes
|
||||
* (4.ff00.0000 - 4.ffff.ffff).
|
||||
* To solve this problem, the flash has to get remapped to another
|
||||
* EBC address which accepts bigger regions:
|
||||
*
|
||||
* 0xfc00.0000 -> 4.cc00.0000
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (NOR-flash) */
|
||||
#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
|
||||
EBC_BXAP_TWT_ENCODE(16) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(1) | \
|
||||
EBC_BXAP_OEN_ENCODE(1) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(7) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_DELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
|
||||
EBC_BXCR_BS_16MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT)
|
||||
|
||||
/* Memory Bank 1 (FPGA 1) */
|
||||
#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
|
||||
EBC_BXAP_TWT_ENCODE(5) | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(4) | \
|
||||
EBC_BXAP_WBN_ENCODE(0) | \
|
||||
EBC_BXAP_WBF_ENCODE(0) | \
|
||||
EBC_BXAP_TH_ENCODE(1) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_DELAYED | \
|
||||
EBC_BXAP_BEM_RW | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
|
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_32BIT)
|
||||
|
||||
/* Memory Bank 2 (FPGA 2) */
|
||||
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
|
||||
EBC_BXAP_TWT_ENCODE(5) | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(4) | \
|
||||
EBC_BXAP_WBN_ENCODE(0) | \
|
||||
EBC_BXAP_WBF_ENCODE(0) | \
|
||||
EBC_BXAP_TH_ENCODE(1) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_DELAYED | \
|
||||
EBC_BXAP_BEM_RW | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
|
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_32BIT)
|
||||
|
||||
/* Memory Bank 3 (FPGA 3) */
|
||||
#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \
|
||||
EBC_BXAP_TWT_ENCODE(5) | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(4) | \
|
||||
EBC_BXAP_WBN_ENCODE(0) | \
|
||||
EBC_BXAP_WBF_ENCODE(0) | \
|
||||
EBC_BXAP_TH_ENCODE(1) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_DELAYED | \
|
||||
EBC_BXAP_BEM_RW | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
|
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_32BIT)
|
||||
|
||||
/*
|
||||
* PPC4xx GPIO Configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
|
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
|
||||
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
|
||||
}, \
|
||||
{ \
|
||||
/* GPIO Core 1 */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue