diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c
index fa2e212bb..bc3e6ad58 100644
--- a/drivers/net/ax88180.c
+++ b/drivers/net/ax88180.c
@@ -267,20 +267,35 @@ static int ax88180_phy_initial (struct eth_device *dev)
 	{
 		priv->PhyAddr = phyaddr;
 		priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
+		priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2);
 
 		switch (priv->PhyID0) {
-		case MARVELL_88E1111_PHYSID0:
-			debug("ax88180: Found Marvell 88E1111 PHY."
+		case MARVELL_ALASKA_PHYSID0:
+			debug("ax88180: Found Marvell Alaska PHY family."
 			      " (PHY Addr=0x%x)\n", priv->PhyAddr);
 
-			tmp_regval = ax88180_mdio_read(dev, M88_EXT_SSR);
-			if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE) {
-				ax88180_mdio_write(dev, M88_EXT_SCR, DEFAULT_EXT_SCR);
-				if (ax88180_phy_reset(dev) < 0)
-					return 0;
-				ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
+			switch (priv->PhyID1) {
+			case MARVELL_88E1118_PHYSID1:
+				ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2);
+				ax88180_mdio_write(dev, M88E1118_CR,
+					M88E1118_CR_DEFAULT);
+				ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3);
+				ax88180_mdio_write(dev, M88E1118_LEDCTL,
+					M88E1118_LEDCTL_DEFAULT);
+				ax88180_mdio_write(dev, M88E1118_LEDMIX,
+					M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15);
+				ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0);
+			default: /* Default to 88E1111 Phy */
+				tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR);
+				if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE)
+					ax88180_mdio_write(dev, M88E1111_EXT_SCR,
+						DEFAULT_EXT_SCR);
 			}
 
+			if (ax88180_phy_reset(dev) < 0)
+				return 0;
+			ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
+
 			return 1;
 
 		case CICADA_CIS8201_PHYSID0:
@@ -358,7 +373,7 @@ static void ax88180_media_config (struct eth_device *dev)
 
 		/* Get real media mode here */
 		switch (priv->PhyID0) {
-		case MARVELL_88E1111_PHYSID0:
+		case MARVELL_ALASKA_PHYSID0:
 			RealMediaMode = get_MarvellPHY_media_mode(dev);
 			break;
 		case CICADA_CIS8201_PHYSID0:
diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h
index c793e92db..f26a91bf8 100644
--- a/drivers/net/ax88180.h
+++ b/drivers/net/ax88180.h
@@ -33,6 +33,7 @@ struct ax88180_private {
 	unsigned char PadSize;
 	unsigned short PhyAddr;
 	unsigned short PhyID0;
+	unsigned short PhyID1;
 	unsigned short FirstTxDesc;
 	unsigned short NextTxDesc;
 	ax88180_link_state LinkState;
@@ -63,7 +64,8 @@ struct ax88180_private {
 /* Max Rx Jumbo size is 15K Bytes */
 #define MAX_RX_SIZE			0x3C00
 
-#define MARVELL_88E1111_PHYSID0	0x0141
+#define MARVELL_ALASKA_PHYSID0	0x141
+#define MARVELL_88E1118_PHYSID1	0xE40
 
 #define CICADA_CIS8201_PHYSID0		0x000F
 
@@ -296,14 +298,36 @@ struct ax88180_private {
   #define LINK_CHANGE_INT	0x0400
 #define M88_ISR		0x0013
   #define LINK_CHANGE_STATUS	0x0400
-#define M88_EXT_SCR	0x0014
+#define M88E1111_EXT_SCR	0x0014
   #define RGMII_RXCLK_DELAY	0x0080
   #define RGMII_TXCLK_DELAY	0x0002
   #define DEFAULT_EXT_SCR	(RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
-#define M88_EXT_SSR	0x001B
+#define M88E1111_EXT_SSR	0x001B
   #define HWCFG_MODE_MASK	0x000F
   #define RGMII_COPPER_MODE	0x000B
 
+/* Marvell 88E1118 Gigabit PHY Register Definition */
+#define M88E1118_CR			0x14
+  #define M88E1118_CR_RGMII_RXCLK_DELAY	0x0020
+  #define M88E1118_CR_RGMII_TXCLK_DELAY	0x0010
+  #define M88E1118_CR_DEFAULT		(M88E1118_CR_RGMII_TXCLK_DELAY | \
+					 M88E1118_CR_RGMII_RXCLK_DELAY)
+#define M88E1118_LEDCTL		0x10		/* Reg 16 on page 3 */
+  #define M88E1118_LEDCTL_LED2INT			0x200
+  #define M88E1118_LEDCTL_LED2BLNK			0x400
+  #define M88E1118_LEDCTL_LED0DUALMODE1	0xc
+  #define M88E1118_LEDCTL_LED0DUALMODE2	0xd
+  #define M88E1118_LEDCTL_LED0DUALMODE3	0xe
+  #define M88E1118_LEDCTL_LED0DUALMODE4	0xf
+  #define M88E1118_LEDCTL_DEFAULT	(M88E1118_LEDCTL_LED2BLNK | \
+					 M88E1118_LEDCTL_LED0DUALMODE4)
+
+#define M88E1118_LEDMIX		0x11		/* Reg 17 on page 3 */
+  #define M88E1118_LEDMIX_LED050				0x4
+  #define M88E1118_LEDMIX_LED150				0x8
+
+#define M88E1118_PAGE_SEL	0x16		/* Reg page select */
+
 /* CICADA CIS8201 Gigabit PHY Register Definition */
 #define CIS_IMR		0x0019
   #define CIS_INT_ENABLE	0x8000