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Merge branch 'master' of git://git.denx.de/u-boot-arm

This commit is contained in:
Wolfgang Denk 2008-10-12 23:55:12 +02:00
parent 72c55878ec 747f316cca
commit 22a871a464
9 changed files with 84 additions and 81 deletions
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13
README.imx31
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@ -1,13 +0,0 @@
i.MX31 specific Configuration Options:
--------------------------------------
- Timer precision:
CONFIG_MX31_TIMER_HIGH_PRECISION
Enable higher precision timer. The low-precision timer
(default) provides approximately 4% error, whereas the
high-precision timer is about 0.4% accurate. The extra
accuracy is achieved at the cost of higher computational
overhead, which, in places where time is measured, should
not be critical, so, it should be safe to enable this
option.

75
cpu/arm1136/mx31/interrupts.c
View File

@ -27,30 +27,49 @@
#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
/* General purpose timers registers */
#define GPTCR __REG(TIMER_BASE) /* Control register */
#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
#define GPTCR __REG(TIMER_BASE) /* Control register */
#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
/* "time" is measured in 1 / CFG_HZ seconds, "tick" is internal timer period */
#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
#define TICK_TO_TIME(t) ((t) * CFG_HZ / CONFIG_MX31_CLK32)
#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CFG_HZ)
#define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \
999999) / 1000000)
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CFG_HZ / 2) / CFG_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
#define TICK_TO_TIME(t) ((t) / TICK_PER_TIME)
#define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME)
#define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK)
#endif
static ulong timestamp;
static ulong lastinc;
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int interrupt_init (void)
{
int i;
/* setup GP Timer 1 */
GPTCR = GPTCR_SWR;
for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */
for (i = 0; i < 100; i++)
GPTCR = 0; /* We have no udelay by now */
GPTPR = 0; /* 32Khz */
GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
/* Freerun Mode, PERCLK1 input */
GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
return 0;
}
@ -67,7 +86,7 @@ void reset_timer(void)
reset_timer_masked();
}
ulong get_timer_masked (void)
unsigned long long get_ticks (void)
{
ulong now = GPTCNT; /* current tick value */
@ -80,6 +99,17 @@ ulong get_timer_masked (void)
return timestamp;
}
ulong get_timer_masked (void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CFG_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return TICK_TO_TIME(get_ticks());
}
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
@ -87,29 +117,20 @@ ulong get_timer (ulong base)
void set_timer (ulong t)
{
timestamp = TIME_TO_TICK(t);
}
/* delay x useconds AND perserve advance timstamp value */
void udelay (unsigned long usec)
{
ulong tmo, tmp;
unsigned long long tmp;
ulong tmo;
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo /= (1000*1000);
}
tmo = US_TO_TICK(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
tmp = get_timer (0); /* get current timestamp */
if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
else
tmo += tmp; /* else, set advancing stamp wake up time */
while (get_timer_masked () < tmo)/* loop till event */
/*NOP*/;
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
void reset_cpu (ulong addr)

29
doc/README.imx31 Normal file
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@ -0,0 +1,29 @@
U-Boot for Freescale i.MX31
This file contains information for the port of U-Boot to the Freescale
i.MX31 SoC.
1. CONFIGURATION OPTIONS/SETTINGS
---------------------------------
1.1 Configuration of MC13783 SPI bus
------------------------------------
The power management companion chip MC13783 is connected to the
i.MX31 via an SPI bus. Use the following configuration options
to setup the bus and chip select used for a particular board.
CONFIG_MC13783_SPI_BUS -- defines the SPI bus the MC13783 is connected to.
Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
CONFIG_MC13783_SPI_CS -- define the chip select the MC13783 s connected to.
1.2 Timer precision
-------------------
CONFIG_MX31_TIMER_HIGH_PRECISION
Enable higher precision timer. The low-precision timer
(default) provides approximately 4% error, whereas the
high-precision timer is about 0.4% accurate. The extra
accuracy is achieved at the cost of higher computational
overhead, which, in places where time is measured, should
not be critical, so, it should be safe to enable this
option.

17
doc/README.mx31
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@ -1,17 +0,0 @@
U-Boot for Freescale i.MX31
This file contains information for the port of U-Boot to the Freescale
i.MX31 SoC.
1. CONFIGURATION OPTIONS/SETTINGS
---------------------------------
1.1 Configuration of MC13783 SPI bus
------------------------------------
The power management companion chip MC13783 is connected to the
i.MX31 via an SPI bus. Use the following configuration options
to setup the bus and chip select used for a particular board.
CONFIG_MC13783_SPI_BUS -- defines the SPI bus the MC13783 is connected to.
Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
CONFIG_MC13783_SPI_CS -- define the chip select the MC13783 s connected to.

2
doc/uImage.FIT/multi.its
View File

@ -56,6 +56,7 @@
data = /incbin/("./eldk-4.2-ramdisk");
type = "ramdisk";
arch = "ppc";
os = "linux";
compression = "gzip";
hash@1 {
algo = "sha1";
@ -67,6 +68,7 @@
data = /incbin/("./eldk-3.1-ramdisk");
type = "ramdisk";
arch = "ppc";
os = "linux";
compression = "gzip";
hash@1 {
algo = "crc32";

4
include/configs/imx31_litekit.h
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@ -122,11 +122,9 @@
#define CFG_MEMTEST_START 0 /* memtest works on */
#define CFG_MEMTEST_END 0x10000
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0 /* default load address */
#define CFG_HZ 32000
#define CFG_HZ 1000
#define CONFIG_CMDLINE_EDITING 1

2
include/configs/imx31_phycore.h
View File

@ -126,7 +126,7 @@
#define CFG_LOAD_ADDR 0 /* default load address */
#define CFG_HZ 32000
#define CFG_HZ 1000
#define CONFIG_CMDLINE_EDITING 1

4
include/configs/mx31ads.h
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@ -139,11 +139,9 @@
#define CFG_MEMTEST_START 0 /* memtest works on */
#define CFG_MEMTEST_END 0x10000
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR CONFIG_LOADADDR
#define CFG_HZ CONFIG_MX31_CLK32 /* use 32kHz clock as source */
#define CFG_HZ 1000
#define CONFIG_CMDLINE_EDITING 1

19
lib_arm/board.c
View File

@ -220,18 +220,6 @@ static int init_func_i2c (void)
}
#endif
#ifdef CONFIG_SKIP_RELOCATE_UBOOT
/*
* This routine sets the relocation done flag, because even if
* relocation is skipped, the flag is used by other generic code.
*/
static int reloc_init(void)
{
gd->flags |= GD_FLG_RELOC;
return 0;
}
#endif
/*
* Breathe some life into the board...
*
@ -261,11 +249,6 @@ int print_cpuinfo (void); /* test-only */
init_fnc_t *init_sequence[] = {
cpu_init, /* basic cpu dependent setup */
#if defined(CONFIG_SKIP_RELOCATE_UBOOT)
reloc_init, /* Set the relocation done flag, must
do this AFTER cpu_init(), but as soon
as possible */
#endif
board_init, /* basic board dependent setup */
interrupt_init, /* set up exceptions */
env_init, /* initialize environment */
@ -307,6 +290,8 @@ void start_armboot (void)
gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
memset (gd->bd, 0, sizeof (bd_t));
gd->flags |= GD_FLG_RELOC;
monitor_flash_len = _bss_start - _armboot_start;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {