ppc4xx: Add initial AMCC Makalu 405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
fa8aea2045
commit
211ea91ac6
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@ -306,6 +306,7 @@ Stefan Roese <sr@denx.de>
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katmai PPC440SPe
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kilauea PPC405EX
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lwmon5 PPC440EPx
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makalu PPC405EX
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ocotea PPC440GX
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p3p440 PPC440GP
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pcs440ep PPC440EP
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1
MAKEALL
1
MAKEALL
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@ -190,6 +190,7 @@ LIST_4xx=" \
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kilauea \
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luan \
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lwmon5 \
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makalu \
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METROBOX \
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MIP405 \
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MIP405T \
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3
Makefile
3
Makefile
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@ -1177,6 +1177,9 @@ luan_config: unconfig
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lwmon5_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5
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makalu_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx makalu amcc
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METROBOX_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
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@ -0,0 +1,50 @@
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o cmd_pll.o memory.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend *~
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,297 @@
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/*
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* (C) Copyright 2000, 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/*
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* ehnus: change pll frequency.
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* Wed Sep 5 11:45:17 CST 2007
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* hsun@udtech.com.cn
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*/
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#include <common.h>
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#include <config.h>
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#include <command.h>
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#include <i2c.h>
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#ifdef CONFIG_CMD_EEPROM
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#define EEPROM_CONF_OFFSET 0
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#define EEPROM_TEST_OFFSET 16
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#define EEPROM_SDSTP_PARAM 16
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#define PLL_NAME_MAX 12
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#define BUF_STEP 8
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/* eeprom_wirtes 8Byte per op. */
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#define EEPROM_ALTER_FREQ(freq) \
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do { \
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int __i; \
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for (__i = 0; __i < 2; __i++) \
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eeprom_write (CFG_I2C_EEPROM_ADDR, \
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EEPROM_CONF_OFFSET + __i*BUF_STEP, \
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pll_select[freq], \
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BUF_STEP + __i*BUF_STEP); \
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} while (0)
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#define PDEBUG
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#ifdef PDEBUG
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#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
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#else
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#define PLL_DEBUG
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#endif
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typedef enum {
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PLL_ebc20,
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PLL_333,
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PLL_4001,
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PLL_4002,
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PLL_533,
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PLL_600,
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PLL_666, /* For now, kilauea can't support */
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RCONF,
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WTEST,
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PLL_TOTAL
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} pll_freq_t;
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static const char
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pll_name[][PLL_NAME_MAX] = {
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"PLL_ebc20",
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"PLL_333",
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"PLL_400@1",
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"PLL_400@2",
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"PLL_533",
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"PLL_600",
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"PLL_666",
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"RCONF",
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"WTEST",
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""
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};
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/*
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* ehnus:
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*/
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static uchar
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pll_select[][EEPROM_SDSTP_PARAM] = {
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/* 0: CPU 333MHz EBC 20MHz, for test only */
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{
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0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 0: 333 */
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{
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0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 1: 400_266 */
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{
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0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 2: 400 */
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{
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0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 3: 533 */
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{
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0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 4: 600 */
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{
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0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 5: 666 */
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{
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0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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{}
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};
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static uchar
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testbuf[EEPROM_SDSTP_PARAM] = {
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0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
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0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
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};
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static void
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pll_debug(int off)
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{
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int i;
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uchar buffer[EEPROM_SDSTP_PARAM];
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memset(buffer, 0, sizeof(buffer));
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eeprom_read(CFG_I2C_EEPROM_ADDR, off,
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buffer, EEPROM_SDSTP_PARAM);
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printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
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for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
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printf("%02x ", buffer[i]);
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printf("\n");
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}
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static void
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test_write(void)
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{
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printf("Debug: test eeprom_write ... ");
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/*
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* Write twice, 8 bytes per write
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*/
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eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
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testbuf, 8);
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eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
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testbuf, 16);
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printf("done\n");
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pll_debug(EEPROM_TEST_OFFSET);
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}
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int
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do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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char c = '\0';
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pll_freq_t pll_freq;
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if (argc < 2) {
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printf("Usage: \n%s\n", cmdtp->usage);
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goto ret;
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}
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for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
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if (!strcmp(pll_name[pll_freq], argv[1]))
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break;
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switch (pll_freq) {
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case PLL_ebc20:
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case PLL_333:
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case PLL_4001:
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case PLL_4002:
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case PLL_533:
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case PLL_600:
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EEPROM_ALTER_FREQ(pll_freq);
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break;
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case PLL_666: /* not support */
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printf("Choose this option will result in a boot failure."
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"\nContinue? (Y/N): ");
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c = getc(); putc('\n');
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if ((c == 'y') || (c == 'Y')) {
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EEPROM_ALTER_FREQ(pll_freq);
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break;
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}
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goto ret;
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case RCONF:
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pll_debug(EEPROM_CONF_OFFSET);
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goto ret;
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case WTEST:
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printf("DEBUG: write test\n");
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test_write();
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goto ret;
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default:
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printf("Invalid options"
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"\n\nUsage: \n%s\n", cmdtp->usage);
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goto ret;
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}
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printf("PLL set to %s, "
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"reset the board to take effect\n", pll_name[pll_freq]);
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PLL_DEBUG;
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ret:
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return 0;
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}
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U_BOOT_CMD(
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pllalter, CFG_MAXARGS, 1, do_pll_alter,
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"pllalter- change pll frequence \n",
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"pllalter <selection> - change pll frequence \n\n\
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** New freq take effect after reset. ** \n\
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----------------------------------------------\n\
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PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
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\t Same as PLL_333 \n\
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\t except \n\
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\t EBC: 20 MHz \n\
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----------------------------------------------\n\
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PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 666 MHz \n\
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\t CPU: 333 MHz \n\
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\t PLB: 166 MHz \n\
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\t OPB: 83 MHz \n\
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\t DDR: 83 MHz \n\
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------------------------------------------------\n\
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PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 800 MHz \n\
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\t CPU: 400 MHz \n\
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\t PLB: 133 MHz \n\
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\t OPB: 66 MHz \n\
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\t DDR: 133 MHz \n\
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------------------------------------------------\n\
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PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 800 MHz \n\
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\t CPU: 400 MHz \n\
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\t PLB: 200 MHz \n\
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\t OPB: 100 MHz \n\
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\t DDR: 200 MHz \n\
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----------------------------------------------\n\
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PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 1066 MHz \n\
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\t CPU: 533 MHz \n\
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\t PLB: 177 MHz \n\
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\t OPB: 88 MHz \n\
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\t DDR: 177 MHz \n\
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----------------------------------------------\n\
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PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 1200 MHz \n\
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\t CPU: 600 MHz \n\
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\t PLB: 200 MHz \n\
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\t OPB: 100 MHz \n\
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\t DDR: 200 MHz \n\
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----------------------------------------------\n\
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PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 1333 MHz \n\
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\t CPU: 666 MHz \n\
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\t PLB: 166 MHz \n\
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\t OPB: 83 MHz \n\
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\t DDR: 166 MHz \n\
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-----------------------------------------------\n\
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RCONF: Read current eeprom configuration. \n\
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-----------------------------------------------\n\
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WTEST: Test EEPROM write with predefined values\n\
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-----------------------------------------------\n"
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);
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#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
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@ -0,0 +1,24 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
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# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
|
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#
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TEXT_BASE = 0xFFFA0000
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@ -0,0 +1,154 @@
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/*
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* (C) Copyright 2007
|
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
|
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* Based on code provided from Senao and AMCC
|
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*
|
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* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
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*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
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#include <config.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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|
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#define mtsdram_as(reg, value) \
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addi r4,0,reg ; \
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mtdcr memcfga,r4 ; \
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addis r4,0,value@h ; \
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ori r4,r4,value@l ; \
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mtdcr memcfgd,r4 ;
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|
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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/*
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* DDR2 setup
|
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*/
|
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|
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/* Following the DDR Core Manual, here is the initialization */
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|
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/* Step 1 */
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/* Step 2 */
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/* Step 3 */
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/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
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mtsdram_as(SDRAM_MB0CF, 0x00005201);
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/* SET SDRAM_MB1CF - Not enabled */
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mtsdram_as(SDRAM_MB1CF, 0x00000000);
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/* SET SDRAM_MB2CF - Not enabled */
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mtsdram_as(SDRAM_MB2CF, 0x00000000);
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/* SET SDRAM_MB3CF - Not enabled */
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mtsdram_as(SDRAM_MB3CF, 0x00000000);
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/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
|
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mtsdram_as(SDRAM_CLKTR,0x80000000);
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|
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/* Refresh Time register (0x30) Refresh every 7.8125uS */
|
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mtsdram_as(SDRAM_RTR, 0x06180000);
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/* SDRAM_SDTR1 */
|
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mtsdram_as(SDRAM_SDTR1, 0x80201000);
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/* SDRAM_SDTR2 */
|
||||
mtsdram_as(SDRAM_SDTR2, 0x32204232);
|
||||
|
||||
/* SDRAM_SDTR3 */
|
||||
mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
|
||||
|
||||
mtsdram_as(SDRAM_MMODE, 0x00000442);
|
||||
mtsdram_as(SDRAM_MEMODE, 0x00000404);
|
||||
|
||||
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
|
||||
mtsdram_as(SDRAM_MCOPT1, 0x04322000);
|
||||
|
||||
/* NOP */
|
||||
mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram_as(SDRAM_INITPLR1, 0x81900400);
|
||||
/* EMR2 twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR2, 0x81020000);
|
||||
/* EMR3 twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR3, 0x81030000);
|
||||
/* EMR DLL ENABLE twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR4, 0x81010404);
|
||||
/* MR w/ DLL reset
|
||||
* Note: 5 is CL. May need to be changed
|
||||
*/
|
||||
mtsdram_as(SDRAM_INITPLR5, 0x81000542);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram_as(SDRAM_INITPLR6, 0x81900400);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
|
||||
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
|
||||
mtsdram_as(SDRAM_INITPLR11, 0x81000442);
|
||||
mtsdram_as(SDRAM_INITPLR12, 0x81010780);
|
||||
mtsdram_as(SDRAM_INITPLR13, 0x81010400);
|
||||
mtsdram_as(SDRAM_INITPLR14, 0x00000000);
|
||||
mtsdram_as(SDRAM_INITPLR15, 0x00000000);
|
||||
|
||||
/* SET MCIF0_CODT Die Termination On */
|
||||
mtsdram_as(SDRAM_CODT, 0x0080f837);
|
||||
mtsdram_as(SDRAM_MODT0, 0x01800000);
|
||||
#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
|
||||
mtsdram_as(SDRAM_MODT1, 0x00000000);
|
||||
#endif
|
||||
|
||||
mtsdram_as(SDRAM_WRDTR, 0x00000000);
|
||||
|
||||
/* SDRAM0_MCOPT2 (0X21) Start initialization */
|
||||
mtsdram_as(SDRAM_MCOPT2, 0x20000000);
|
||||
|
||||
/* Step 5 */
|
||||
lis r3,0x1 /* 400000 = wait 100ms */
|
||||
mtctr r3
|
||||
|
||||
pll_wait:
|
||||
bdnz pll_wait
|
||||
|
||||
/* Step 6 */
|
||||
|
||||
/* SDRAM_DLCR */
|
||||
mtsdram_as(SDRAM_DLCR, 0x030000a5);
|
||||
|
||||
/* SDRAM_RDCC */
|
||||
mtsdram_as(SDRAM_RDCC, 0x40000000);
|
||||
|
||||
/* SDRAM_RQDC */
|
||||
mtsdram_as(SDRAM_RQDC, 0x80000038);
|
||||
|
||||
/* SDRAM_RFDC */
|
||||
mtsdram_as(SDRAM_RFDC, 0x00000209);
|
||||
|
||||
/* Enable memory controller */
|
||||
mtsdram_as(SDRAM_MCOPT2, 0x28000000);
|
||||
|
||||
blr
|
||||
|
|
@ -0,0 +1,378 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <ppc405.h>
|
||||
#include <libfdt.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm-ppc/io.h>
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#include <pci.h>
|
||||
#include <asm/4xx_pcie.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*
|
||||
* Board early initialization function
|
||||
*/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*--------------------------------------------------------------------+
|
||||
| Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
|
||||
+--------------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------+
|
||||
|Interrupt| Source | Pol. | Sensi.| Crit. |
|
||||
+---------+-----------------------------------+-------+-------+-------+
|
||||
| IRQ 00 | UART0 | High | Level | Non |
|
||||
| IRQ 01 | UART1 | High | Level | Non |
|
||||
| IRQ 02 | IIC0 | High | Level | Non |
|
||||
| IRQ 03 | TBD | High | Level | Non |
|
||||
| IRQ 04 | TBD | High | Level | Non |
|
||||
| IRQ 05 | EBM | High | Level | Non |
|
||||
| IRQ 06 | BGI | High | Level | Non |
|
||||
| IRQ 07 | IIC1 | Rising| Edge | Non |
|
||||
| IRQ 08 | SPI | High | Lvl/ed| Non |
|
||||
| IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
|
||||
| IRQ 10 | MAL TX EOB | High | Level | Non |
|
||||
| IRQ 11 | MAL RX EOB | High | Level | Non |
|
||||
| IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
|
||||
| IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
|
||||
| IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
|
||||
| IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
|
||||
| IRQ 16 | PCIE0 AL | high | Level | Non |
|
||||
| IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
|
||||
| IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
|
||||
| IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
|
||||
| IRQ 20 | PCIE0 TCR | High | Level | Non |
|
||||
| IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
|
||||
| IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
|
||||
| IRQ 23 | Security EIP-94 | High | Level | Non |
|
||||
| IRQ 24 | EMAC0 interrupt | High | Level | Non |
|
||||
| IRQ 25 | EMAC1 interrupt | High | Level | Non |
|
||||
| IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
|
||||
| IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
|
||||
| IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
|
||||
| IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
|
||||
| IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
|
||||
| IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
|
||||
|----------------------------------------------------------------------
|
||||
| IRQ 32 | MAL Serr | High | Level | Non |
|
||||
| IRQ 33 | MAL Txde | High | Level | Non |
|
||||
| IRQ 34 | MAL Rxde | High | Level | Non |
|
||||
| IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
|
||||
| IRQ 36 | PCIE0 DCR Error | High | Level | Non |
|
||||
| IRQ 37 | EBC | High |Lvl Edg| Non |
|
||||
| IRQ 38 | NDFC | High | Level | Non |
|
||||
| IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
|
||||
| IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
|
||||
| IRQ 41 | PCIE1 AL | high | Level | Non |
|
||||
| IRQ 42 | PCIE1 VPD access | rising| edge | Non |
|
||||
| IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
|
||||
| IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
|
||||
| IRQ 45 | PCIE1 TCR | High | Level | Non |
|
||||
| IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
|
||||
| IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
|
||||
| IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
|
||||
| IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
|
||||
| IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
|
||||
| IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
|
||||
| IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
|
||||
| IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
|
||||
| IRQ 55 | Serial ROM | High | Level | Non |
|
||||
| IRQ 56 | GPT Decrement Pulse | High | Level | Non |
|
||||
| IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 60 | EMAC0 Wake-up | High | Level | Non |
|
||||
| IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 62 | EMAC1 Wake-up | High | Level | Non |
|
||||
|----------------------------------------------------------------------
|
||||
| IRQ 64 | PE0 AL | High | Level | Non |
|
||||
| IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 68 | PE0 TCR | High | Level | Non |
|
||||
| IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 70 | PE0 DCR Error | High | Level | Non |
|
||||
| IRQ 71 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 72 | PE1 AL | High | Level | Non |
|
||||
| IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 76 | PE1 TCR | High | Level | Non |
|
||||
| IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 78 | PE1 DCR Error | High | Level | Non |
|
||||
| IRQ 79 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 80 | PE2 AL | High | Level | Non |
|
||||
| IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 84 | PE2 TCR | High | Level | Non |
|
||||
| IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 86 | PE2 DCR Error | High | Level | Non |
|
||||
| IRQ 87 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 88 | External IRQ(5) | Progr | Progr | Non |
|
||||
| IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
|
||||
| IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 94 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 95 | Reserved | N/A | N/A | Non |
|
||||
|---------------------------------------------------------------------
|
||||
+---------+-----------------------------------+-------+-------+------*/
|
||||
/*--------------------------------------------------------------------+
|
||||
| Initialise UIC registers. Clear all interrupts. Disable all
|
||||
| interrupts.
|
||||
| Set critical interrupt values. Set interrupt polarities. Set
|
||||
| interrupt trigger levels. Make bit 0 High priority. Clear all
|
||||
| interrupts again.
|
||||
+-------------------------------------------------------------------*/
|
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
|
||||
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
|
||||
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
|
||||
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
|
||||
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
|
||||
/* Except cascade UIC0 and UIC1 */
|
||||
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
|
||||
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
/*
|
||||
* Note: Some cores are still in reset when the chip starts, so
|
||||
* take them out of reset
|
||||
*/
|
||||
mtsdr(SDR0_SRST, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
/* Monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int pci_pre_init(struct pci_controller * hose )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller * hose )
|
||||
{
|
||||
/*-------------------------------------------------------------------+
|
||||
* Disable everything
|
||||
*-------------------------------------------------------------------*/
|
||||
out32r( PCIX0_PIM0SA, 0 ); /* disable */
|
||||
out32r( PCIX0_PIM1SA, 0 ); /* disable */
|
||||
out32r( PCIX0_PIM2SA, 0 ); /* disable */
|
||||
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
|
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
|
||||
* strapping options to not support sizes such as 128/256 MB.
|
||||
*-------------------------------------------------------------------*/
|
||||
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
|
||||
out32r( PCIX0_PIM0LAH, 0 );
|
||||
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
|
||||
|
||||
out32r( PCIX0_BAR0, 0 );
|
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id
|
||||
*-------------------------------------------------------------------*/
|
||||
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
|
||||
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
|
||||
|
||||
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static struct pci_controller pcie_hose[2] = {{0},{0}};
|
||||
|
||||
void pcie_setup_hoses(int busno)
|
||||
{
|
||||
struct pci_controller *hose;
|
||||
int i, bus;
|
||||
int ret = 0;
|
||||
bus = busno;
|
||||
char *env;
|
||||
unsigned int delay;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
|
||||
if (is_end_point(i)) {
|
||||
printf("PCIE%d: will be configured as endpoint\n", i);
|
||||
ret = ppc4xx_init_pcie_endport(i);
|
||||
} else {
|
||||
printf("PCIE%d: will be configured as root-complex\n", i);
|
||||
ret = ppc4xx_init_pcie_rootport(i);
|
||||
}
|
||||
if (ret) {
|
||||
printf("PCIE%d: initialization failed\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
hose = &pcie_hose[i];
|
||||
hose->first_busno = bus;
|
||||
hose->last_busno = bus;
|
||||
hose->current_busno = bus;
|
||||
|
||||
/* setup mem resource */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMSIZE,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count = 1;
|
||||
pci_register_hose(hose);
|
||||
|
||||
if (is_end_point(i)) {
|
||||
ppc4xx_setup_pcie_endpoint(hose, i);
|
||||
/*
|
||||
* Reson for no scanning is endpoint can not generate
|
||||
* upstream configuration accesses.
|
||||
*/
|
||||
} else {
|
||||
ppc4xx_setup_pcie_rootpoint(hose, i);
|
||||
env = getenv ("pciscandelay");
|
||||
if (env != NULL) {
|
||||
delay = simple_strtoul(env, NULL, 10);
|
||||
if (delay > 5)
|
||||
printf("Warning, expect noticable delay before "
|
||||
"PCIe scan due to 'pciscandelay' value!\n");
|
||||
mdelay(delay * 1000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Config access can only go down stream
|
||||
*/
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
bus = hose->last_busno + 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
return 0; /* No hotkeys supported */
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 val[4];
|
||||
int rc;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* Fixup NOR mapping */
|
||||
val[0] = 0; /* chip select number */
|
||||
val[1] = 0; /* always 0 */
|
||||
val[2] = gd->bd->bi_flashstart;
|
||||
val[3] = gd->bd->bi_flashsize;
|
||||
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
||||
val, sizeof(val), 1);
|
||||
if (rc)
|
||||
printf("Unable to update property NOR mapping, err=%s\n",
|
||||
fdt_strerror(rc));
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
/*
|
||||
* Same as on Kilauea, Makalu generates exception 0x200
|
||||
* (machine check) after trap_init() in board_init_f,
|
||||
* when SDRAM is initialized here (late) and d-cache is
|
||||
* used earlier as INIT_RAM.
|
||||
* So for now, initialize DDR2 in init.S very early and
|
||||
* also use it for INIT_RAM. Then this exception doesn't
|
||||
* occur.
|
||||
*/
|
||||
#if 0
|
||||
u32 val;
|
||||
|
||||
/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
|
||||
mtsdram(SDRAM_MB0CF, 0x00005201);
|
||||
|
||||
/* SET SDRAM_MB1CF - Not enabled */
|
||||
mtsdram(SDRAM_MB1CF, 0x00000000);
|
||||
|
||||
/* SET SDRAM_MB2CF - Not enabled */
|
||||
mtsdram(SDRAM_MB2CF, 0x00000000);
|
||||
|
||||
/* SET SDRAM_MB3CF - Not enabled */
|
||||
mtsdram(SDRAM_MB3CF, 0x00000000);
|
||||
|
||||
/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
|
||||
mtsdram(SDRAM_CLKTR, 0x80000000);
|
||||
|
||||
/* Refresh Time register (0x30) Refresh every 7.8125uS */
|
||||
mtsdram(SDRAM_RTR, 0x06180000);
|
||||
|
||||
/* SDRAM_SDTR1 */
|
||||
mtsdram(SDRAM_SDTR1, 0x80201000);
|
||||
|
||||
/* SDRAM_SDTR2 */
|
||||
mtsdram(SDRAM_SDTR2, 0x32204232);
|
||||
|
||||
/* SDRAM_SDTR3 */
|
||||
mtsdram(SDRAM_SDTR3, 0x080b0d1a);
|
||||
|
||||
mtsdram(SDRAM_MMODE, 0x00000442);
|
||||
mtsdram(SDRAM_MEMODE, 0x00000404);
|
||||
|
||||
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
|
||||
mtsdram(SDRAM_MCOPT1, 0x04322000);
|
||||
|
||||
/* NOP */
|
||||
mtsdram(SDRAM_INITPLR0, 0xa8380000);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram(SDRAM_INITPLR1, 0x81900400);
|
||||
/* EMR2 twr = 2tck */
|
||||
mtsdram(SDRAM_INITPLR2, 0x81020000);
|
||||
/* EMR3 twr = 2tck */
|
||||
mtsdram(SDRAM_INITPLR3, 0x81030000);
|
||||
/* EMR DLL ENABLE twr = 2tck */
|
||||
mtsdram(SDRAM_INITPLR4, 0x81010404);
|
||||
/* MR w/ DLL reset
|
||||
* Note: 5 is CL. May need to be changed
|
||||
*/
|
||||
mtsdram(SDRAM_INITPLR5, 0x81000542);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram(SDRAM_INITPLR6, 0x81900400);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram(SDRAM_INITPLR7, 0x8D080000);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram(SDRAM_INITPLR8, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram(SDRAM_INITPLR9, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram(SDRAM_INITPLR10, 0x8D080000);
|
||||
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
|
||||
mtsdram(SDRAM_INITPLR11, 0x81000442);
|
||||
mtsdram(SDRAM_INITPLR12, 0x81010780);
|
||||
mtsdram(SDRAM_INITPLR13, 0x81010400);
|
||||
mtsdram(SDRAM_INITPLR14, 0x00000000);
|
||||
mtsdram(SDRAM_INITPLR15, 0x00000000);
|
||||
|
||||
/* SET MCIF0_CODT Die Termination On */
|
||||
mtsdram(SDRAM_CODT, 0x0080f837);
|
||||
mtsdram(SDRAM_MODT0, 0x01800000);
|
||||
mtsdram(SDRAM_MODT1, 0x00000000);
|
||||
|
||||
mtsdram(SDRAM_WRDTR, 0x00000000);
|
||||
|
||||
/* SDRAM0_MCOPT2 (0X21) Start initialization */
|
||||
mtsdram(SDRAM_MCOPT2, 0x20000000);
|
||||
|
||||
/* Step 5 */
|
||||
do {
|
||||
mfsdram(SDRAM_MCSTAT, val);
|
||||
} while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
|
||||
|
||||
/* Step 6 */
|
||||
|
||||
/* SDRAM_DLCR */
|
||||
mtsdram(SDRAM_DLCR, 0x030000a5);
|
||||
|
||||
/* SDRAM_RDCC */
|
||||
mtsdram(SDRAM_RDCC, 0x40000000);
|
||||
|
||||
/* SDRAM_RQDC */
|
||||
mtsdram(SDRAM_RQDC, 0x80000038);
|
||||
|
||||
/* SDRAM_RFDC */
|
||||
mtsdram(SDRAM_RFDC, 0x00000209);
|
||||
|
||||
/* Enable memory controller */
|
||||
mfsdram(SDRAM_MCOPT2, val);
|
||||
val |= SDRAM_MCOPT2_DCEN_ENABLE;
|
||||
mtsdram(SDRAM_MCOPT2, val);
|
||||
#endif
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
printf ("testdram\n");
|
||||
#if defined (CONFIG_NAND_U_BOOT)
|
||||
return 0;
|
||||
#endif
|
||||
uint *pstart = (uint *) 0x00000000;
|
||||
uint *pend = (uint *) 0x00001000;
|
||||
uint *p;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
*p = 0xaaaaaaaa;
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
*p = 0x55555555;
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test passed!!!\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* To compile successfully, uncomment the following section.
|
||||
* To go in ram, remove the section.
|
||||
* Added by SunHe.
|
||||
*/
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,387 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* makalu.h - configuration for AMCC Makalu (405EX)
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_MAKALU 1 /* Board is Makalu */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_405EX 1 /* Specifc 405EX support*/
|
||||
#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xFE000000
|
||||
#define CFG_FPGA_BASE 0xF0000000
|
||||
#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
|
||||
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_MONITOR_BASE (TEXT_BASE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
|
||||
#define CFG_INIT_RAM_END (4 << 10)
|
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
/* reserve some memory for POST and BOOT limit info */
|
||||
#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
|
||||
|
||||
/* extra data in init-ram */
|
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
|
||||
#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
|
||||
#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
|
||||
#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
/* define this if you want console on UART1 */
|
||||
#undef CONFIG_UART1_CONSOLE
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#endif /* CFG_ENV_IS_IN_FLASH */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MBYTES_SDRAM 128
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
|
||||
#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
|
||||
/* Standard DTT sensor configuration */
|
||||
#define CONFIG_DTT_DS1775 1
|
||||
#define CONFIG_DTT_SENSORS { 0 }
|
||||
#define CFG_I2C_DTT_ADDR 0x48
|
||||
|
||||
/* RTC configuration */
|
||||
#define CONFIG_RTC_X1205 1
|
||||
#define CFG_I2C_RTC_ADDR 0x6f
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Ethernet
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_M88E1111_PHY 1
|
||||
#define CONFIG_IBM_EMAC4_V4 1
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
|
||||
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
|
||||
#define CONFIG_HAS_ETH0 1
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
|
||||
#define CONFIG_PHY1_ADDR 2
|
||||
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"logversion=2\0" \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=makalu\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};" \
|
||||
"run nfsargs addip addtty addmisc;" \
|
||||
"bootm 200000\0" \
|
||||
"net_nfs_fdt=tftp 200000 ${bootfile};" \
|
||||
"tftp ${fdt_addr} ${fdt_file};" \
|
||||
"run nfsargs addip addtty addmisc;" \
|
||||
"bootm 200000 - ${fdt_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=makalu/uImage\0" \
|
||||
"fdt_file=makalu/makalu.dtb\0" \
|
||||
"fdt_addr=400000\0" \
|
||||
"kernel_addr=fe000000\0" \
|
||||
"ramdisk_addr=fe200000\0" \
|
||||
"initrd_high=30000000\0" \
|
||||
"load=tftp 200000 makalu/u-boot.bin\0" \
|
||||
"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
|
||||
"cp.b ${fileaddr} fffa0000 ${filesize};" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load update\0" \
|
||||
"pciconfighost=1\0" \
|
||||
"pcie_mode=RP:RP\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_DTT
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_LOG
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CFG_POST_MEMORY | \
|
||||
CFG_POST_CACHE | \
|
||||
CFG_POST_CPU | \
|
||||
CFG_POST_ETHER | \
|
||||
CFG_POST_I2C | \
|
||||
CFG_POST_MEMORY | \
|
||||
CFG_POST_UART)
|
||||
|
||||
/* Define here the base-addresses of the UARTs to test in POST */
|
||||
#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
|
||||
|
||||
#define CONFIG_LOGBUFFER
|
||||
#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
|
||||
|
||||
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
|
||||
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCIe stuff
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
|
||||
#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
|
||||
|
||||
#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
|
||||
#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
|
||||
#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
|
||||
|
||||
#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
|
||||
#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
|
||||
#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
|
||||
|
||||
#define CFG_PCIE0_UTLBASE 0xef502000
|
||||
#define CFG_PCIE1_UTLBASE 0xef503000
|
||||
|
||||
/* base address of inbound PCIe window */
|
||||
#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_DCACHE_SIZE (16 << 10) /* For IBM 405EX */
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x04011000
|
||||
#define CFG_EBC_PB0CR 0xFE0BA000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit*/
|
||||
|
||||
/* Memory Bank 2 (CPLD) initialization */
|
||||
#define CFG_EBC_PB2AP 0x9400C800
|
||||
#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* GPIO Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EX specific)
|
||||
*
|
||||
* GPIO0[0-3] - EBC data 0-3 inputs/outputs
|
||||
* GPIO0[4-7] - USB data 4-7 inputs/outputs
|
||||
* GPIO0[8-11] - NFCE# 1-3 inputs/outputs, GPIO11: IRQ6 inputs
|
||||
* GPIO0[12-15] - USB data 0-3 inputs/outputs
|
||||
* GPIO0[16-21] - UART0 control signal inputs/outputs
|
||||
*
|
||||
* GPIO0[22-25,27] - EBC control signal inputs/outputs
|
||||
* GPIO0[26] - Instruction trace outputs
|
||||
* GPIO0[28] - Float, N/C
|
||||
* GPIO0[29-31] - DMA control signal inputs/outputs
|
||||
*/
|
||||
#define CFG_GPIO0_OSRL 0x00AA54AA
|
||||
#define CFG_GPIO0_OSRH 0x55500000
|
||||
#define CFG_GPIO0_TSRL 0x00AA54AA
|
||||
#define CFG_GPIO0_TSRH 0x55500000
|
||||
#define CFG_GPIO0_ISR1L 0x00005400
|
||||
#define CFG_GPIO0_ISR1H 0x55500000
|
||||
#define CFG_GPIO0_ISR2L 0x00550055
|
||||
#define CFG_GPIO0_ISR2H 0x00000000
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#define OF_CPU "PowerPC,405EX@0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue