AT91SAM9RLEK support
This patch adds support for the AT91SAM9RL chip and the AT91SAM9RLEK board. Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Stelian Pop
Jean-Christophe PLAGNIOL-VILLARD
parent
8e429b3eee
commit
2118ebb44d
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@ -540,6 +540,7 @@ Stelian Pop <stelian.pop@leadtechdesign.com>
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at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
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at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
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at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
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at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
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Stefan Roese <sr@denx.de>
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1
MAKEALL
1
MAKEALL
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@ -461,6 +461,7 @@ LIST_ARM9=" \
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at91sam9260ek \
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at91sam9261ek \
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at91sam9263ek \
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at91sam9rlek \
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cmc_pu2 \
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ap920t \
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ap922_XA10 \
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3
Makefile
3
Makefile
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@ -2332,6 +2332,9 @@ at91sam9261ek_config : unconfig
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at91sam9263ek_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
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at91sam9rlek_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
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cmc_pu2_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
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@ -0,0 +1,57 @@
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian.pop@leadtechdesign.com>
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# Lead Tech Design <www.leadtechdesign.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += at91sam9rlek.o
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COBJS-y += led.o
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COBJS-y += partition.o
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COBJS-$(CONFIG_CMD_NAND) += nand.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,152 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/at91sam9rl_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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static void at91sam9rlek_serial_hw_init(void)
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{
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#ifdef CONFIG_USART0
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at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
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at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
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#endif
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#ifdef CONFIG_USART1
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at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
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at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
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#endif
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#ifdef CONFIG_USART2
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at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
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at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
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#endif
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#ifdef CONFIG_USART3 /* DBGU */
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at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
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at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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#endif
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}
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#ifdef CONFIG_CMD_NAND
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static void at91sam9rlek_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
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AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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#ifdef CFG_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CFG_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(1));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
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/* Configure RDY/BSY */
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at91_set_gpio_input(AT91_PIN_PD17, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(AT91_PIN_PB6, 1);
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at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
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at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
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}
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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static void at91sam9rlek_spi_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PA28, 0); /* SPI0_NPCS0 */
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at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
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at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
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at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
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}
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of AT91SAM9RLEK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91sam9rlek_serial_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91sam9rlek_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91sam9rlek_spi_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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@ -0,0 +1 @@
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TEXT_BASE = 0x23f00000
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@ -0,0 +1,77 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#define RED_LED AT91_PIN_PD14 /* this is the power led */
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#define GREEN_LED AT91_PIN_PD15 /* this is the user1 led */
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#define YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */
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void red_LED_on(void)
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{
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at91_set_gpio_value(RED_LED, 1);
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}
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void red_LED_off(void)
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{
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at91_set_gpio_value(RED_LED, 0);
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}
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void green_LED_on(void)
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{
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at91_set_gpio_value(GREEN_LED, 0);
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}
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void green_LED_off(void)
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{
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at91_set_gpio_value(GREEN_LED, 1);
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}
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void yellow_LED_on(void)
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{
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at91_set_gpio_value(YELLOW_LED, 0);
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}
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void yellow_LED_off(void)
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{
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at91_set_gpio_value(YELLOW_LED, 1);
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}
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void coloured_LED_init(void)
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{
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
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at91_set_gpio_output(RED_LED, 1);
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at91_set_gpio_output(GREEN_LED, 1);
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at91_set_gpio_output(YELLOW_LED, 1);
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at91_set_gpio_value(RED_LED, 0);
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at91_set_gpio_value(GREEN_LED, 1);
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at91_set_gpio_value(YELLOW_LED, 1);
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}
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@ -0,0 +1,79 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91_pio.h>
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#include <nand.h>
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/*
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* hardware specific access to control-lines
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*/
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#define MASK_ALE (1 << 21) /* our ALE is AD21 */
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#define MASK_CLE (1 << 22) /* our CLE is AD22 */
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static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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struct nand_chip *this = mtd->priv;
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
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switch (cmd) {
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case NAND_CTL_SETCLE:
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IO_ADDR_W |= MASK_CLE;
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break;
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case NAND_CTL_SETALE:
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IO_ADDR_W |= MASK_ALE;
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break;
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case NAND_CTL_CLRNCE:
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at91_set_gpio_value(AT91_PIN_PB6, 1);
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break;
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case NAND_CTL_SETNCE:
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at91_set_gpio_value(AT91_PIN_PB6, 0);
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break;
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}
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this->IO_ADDR_W = (void *) IO_ADDR_W;
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}
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static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
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{
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return at91_get_gpio_value(AT91_PIN_PD17);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->eccmode = NAND_ECC_SOFT;
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#ifdef CFG_NAND_DBW_16
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nand->options = NAND_BUSWIDTH_16;
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#endif
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nand->hwcontrol = at91sam9rlek_nand_hwcontrol;
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nand->dev_ready = at91sam9rlek_nand_ready;
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nand->chip_delay = 20;
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return 0;
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}
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@ -0,0 +1,39 @@
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/*
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* (C) Copyright 2008
|
||||
* Ulf Samuelsson <ulf@atmel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
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#include <common.h>
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#include <config.h>
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#include <asm/hardware.h>
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#include <dataflash.h>
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AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
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struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
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{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
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};
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/*define the area offsets*/
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dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
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{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
|
||||
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
|
||||
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
|
||||
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
|
||||
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
|
||||
};
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9RL_H
|
||||
#define AT91SAM9RL_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Controller */
|
||||
#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
|
||||
#define AT91SAM9RL_ID_US0 6 /* USART 0 */
|
||||
#define AT91SAM9RL_ID_US1 7 /* USART 1 */
|
||||
#define AT91SAM9RL_ID_US2 8 /* USART 2 */
|
||||
#define AT91SAM9RL_ID_US3 9 /* USART 3 */
|
||||
#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
|
||||
#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
|
||||
#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
|
||||
#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
|
||||
#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
|
||||
#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
|
||||
#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
|
||||
#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
|
||||
#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
|
||||
#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
|
||||
#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
|
||||
#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
|
||||
#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
|
||||
#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
|
||||
#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9RL_BASE_TCB0 0xfffa0000
|
||||
#define AT91SAM9RL_BASE_TC0 0xfffa0000
|
||||
#define AT91SAM9RL_BASE_TC1 0xfffa0040
|
||||
#define AT91SAM9RL_BASE_TC2 0xfffa0080
|
||||
#define AT91SAM9RL_BASE_MCI 0xfffa4000
|
||||
#define AT91SAM9RL_BASE_TWI0 0xfffa8000
|
||||
#define AT91SAM9RL_BASE_TWI1 0xfffac000
|
||||
#define AT91SAM9RL_BASE_US0 0xfffb0000
|
||||
#define AT91SAM9RL_BASE_US1 0xfffb4000
|
||||
#define AT91SAM9RL_BASE_US2 0xfffb8000
|
||||
#define AT91SAM9RL_BASE_US3 0xfffbc000
|
||||
#define AT91SAM9RL_BASE_SSC0 0xfffc0000
|
||||
#define AT91SAM9RL_BASE_SSC1 0xfffc4000
|
||||
#define AT91SAM9RL_BASE_PWMC 0xfffc8000
|
||||
#define AT91SAM9RL_BASE_SPI 0xfffcc000
|
||||
#define AT91SAM9RL_BASE_TSC 0xfffd0000
|
||||
#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
|
||||
#define AT91SAM9RL_BASE_AC97C 0xfffd8000
|
||||
#define AT91_BASE_SYS 0xffffc000
|
||||
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91_USART0 AT91SAM9RL_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9RL_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9RL_BASE_US2
|
||||
#define AT91_USART3 AT91SAM9RL_BASE_US3
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
|
||||
|
||||
#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
|
||||
#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h]
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9RL_MATRIX_H
|
||||
#define AT91SAM9RL_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
|
||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -37,6 +37,8 @@
|
|||
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
|
||||
#elif defined(CONFIG_AT91SAM9RL)
|
||||
#include <asm/arch/at91sam9rl.h>
|
||||
#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI
|
||||
#define AT91_ID_UHP AT91SAM9RL_ID_UHP
|
||||
#elif defined(CONFIG_AT91CAP9)
|
||||
#include <asm/arch/at91cap9.h>
|
||||
#define AT91_BASE_EMAC AT91CAP9_BASE_EMAC
|
||||
|
|
|
|||
|
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
*
|
||||
* Configuation settings for the AT91SAM9RLEK board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
#define AT91_MAIN_CLOCK 200000000 /* from 12.000 MHz crystal */
|
||||
#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
|
||||
#define CFG_HZ 1000000 /* 1us resolution */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/
|
||||
#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
#undef CONFIG_USART2
|
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/* #define CONFIG_ENV_OVERWRITE 1 */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_AUTOSCRIPT
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_USB
|
||||
|
||||
#define CONFIG_CMD_NAND 1
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
|
||||
|
||||
/* DataFlash */
|
||||
#define CONFIG_HAS_DATAFLASH 1
|
||||
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
|
||||
#define CFG_MAX_DATAFLASH_BANKS 1
|
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
|
||||
#define AT91_SPI_CLK 15000000
|
||||
#define DATAFLASH_TCSS (0x1a << 16)
|
||||
#define DATAFLASH_TCHS (0x1 << 24)
|
||||
|
||||
/* NOR flash - not present */
|
||||
#define CFG_NO_FLASH 1
|
||||
|
||||
/* NAND flash */
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define CFG_NAND_BASE 0x40000000
|
||||
#define CFG_NAND_DBW_8 1
|
||||
|
||||
/* Ethernet - not present */
|
||||
|
||||
/* USB - not supported */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM
|
||||
#define CFG_MEMTEST_END 0x23e00000
|
||||
|
||||
#define CFG_USE_DATAFLASH 1
|
||||
#undef CFG_USE_NANDFLASH
|
||||
|
||||
#ifdef CFG_USE_DATAFLASH
|
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
|
||||
#define CFG_ENV_IS_IN_DATAFLASH 1
|
||||
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
|
||||
#define CFG_ENV_OFFSET 0x4200
|
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
|
||||
#define CFG_ENV_SIZE 0x4200
|
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||
"root=/dev/mtdblock0 " \
|
||||
"mtdparts=at91_nand:-(root) "\
|
||||
"rw rootfstype=jffs2"
|
||||
|
||||
#else /* CFG_USE_NANDFLASH */
|
||||
|
||||
/* bootstrap + u-boot + env + linux in nandflash */
|
||||
#define CFG_ENV_IS_IN_NAND 1
|
||||
#define CFG_ENV_OFFSET 0x60000
|
||||
#define CFG_ENV_OFFSET_REDUND 0x80000
|
||||
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
|
||||
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||
"root=/dev/mtdblock5 " \
|
||||
"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
|
||||
"rw rootfstype=jffs2"
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CFG_PROMPT "U-Boot> "
|
||||
#define CFG_CBSIZE 256
|
||||
#define CFG_MAXARGS 16
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
|
||||
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue