[PATCH] Update Prodrive ALPR board support (440GX)
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
48c7d6dba9
commit
1c2ce22620
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o fpga.o nand.o
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COBJS = $(BOARD).o fpga.o nand.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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@ -26,6 +26,7 @@
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <ppc4xx_enet.h>
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#include <miiphy.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -33,24 +34,14 @@ extern int alpr_fpga_init(void);
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int board_early_init_f (void)
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{
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unsigned long mfr;
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/*-------------------------------------------------------------------------+
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| Initialize EBC CONFIG
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+-------------------------------------------------------------------------*/
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#if 0
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mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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#else
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/*-------------------------------------------------------------------------
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* Initialize EBC CONFIG
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*-------------------------------------------------------------------------*/
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mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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#endif
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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@ -58,8 +49,8 @@ int board_early_init_f (void)
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic0er, 0x00000000); /* disable all */
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mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr (uic0pr, 0xfffffe03); /* per manual */
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mtdcr (uic0tr, 0x01c00000); /* per manual */
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mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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@ -85,12 +76,57 @@ int board_early_init_f (void)
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mtdcr (uicb0pr, 0xfc000000); /* */
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mtdcr (uicb0tr, 0x00000000); /* */
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mtdcr (uicb0vr, 0x00000001); /* */
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mfsdr (sdr_mfr, mfr);
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mfr &= ~SDR0_MFR_ECS_MASK;
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/* Setup GPIO/IRQ multiplexing */
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mtsdr(sdr_pfc0, 0x01a03e00);
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return 0;
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}
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int last_stage_init(void)
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{
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unsigned short reg;
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/*
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* Configure LED's of both Marvell 88E1111 PHY's
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*
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* This has to be done after the 4xx ethernet driver is loaded,
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* so "last_stage_init()" is the right place.
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*/
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miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®);
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reg |= 0x0001;
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miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
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miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®);
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reg |= 0x0001;
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miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
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return 0;
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}
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static int board_rev(void)
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{
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int rev;
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u32 pfc0;
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/* Setup GPIO14 & 15 as GPIO */
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mfsdr(sdr_pfc0, pfc0);
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pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1;
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mtsdr(sdr_pfc0, pfc0);
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/* Setup as input */
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
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rev = (in32(GPIO0_IR) >> 16) & 0x3;
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/* Setup GPIO14 & 15 as non GPIO again */
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mfsdr(sdr_pfc0, pfc0);
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pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1);
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mtsdr(sdr_pfc0, pfc0);
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return rev;
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}
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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@ -100,7 +136,7 @@ int checkboard (void)
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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printf(" (Rev. %d)\n", board_rev());
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return (0);
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}
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@ -224,10 +260,26 @@ void pci_target_init(struct pci_controller * hose )
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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static void wait_for_pci_ready(void)
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{
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/*
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* Configure EREADY as input
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*/
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
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udelay(1000);
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for (;;) {
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if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
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return;
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}
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}
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int is_pci_host(struct pci_controller *hose)
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{
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/* The ocotea board is always configured as host. */
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return(1);
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wait_for_pci_ready();
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return 1; /* return 1 for host controller */
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}
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#endif /* defined(CONFIG_PCI) */
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@ -274,11 +326,3 @@ int post_hotkeys_pressed(void)
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return (ctrlc());
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}
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#endif
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void board_reset(void)
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{
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/*
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* Initiate chip reset in debug control register DBCR
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*/
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mtspr(dbcr0, 0x20000000);
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}
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@ -36,7 +36,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if (CONFIG_FPGA)
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#if defined(CONFIG_FPGA)
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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@ -44,46 +44,38 @@ DECLARE_GLOBAL_DATA_PTR;
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#define PRINTF(fmt,args...)
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#endif
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static unsigned long regval;
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static unsigned long regval;
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#define SET_GPIO_REG_0(reg, bit) {\
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regval = in32(reg);\
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regval &= ~(0x80000000 >> bit);\
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out32(reg, regval);\
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}
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#define SET_GPIO_REG_0(reg, bit) { \
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regval = in32(reg); \
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regval &= ~(0x80000000 >> bit); \
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out32(reg, regval); \
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}
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#define SET_GPIO_REG_1(reg, bit) {\
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regval = in32(reg);\
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regval |= (0x80000000 >> bit);\
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out32(reg, regval);\
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}
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#define SET_GPIO_REG_1(reg, bit) { \
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regval = in32(reg); \
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regval |= (0x80000000 >> bit); \
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out32(reg, regval); \
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}
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#define GPIO_CLK_PIN 0x00002000
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#define GPIO_CLK_PIN_I 0xffffdfff
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#define GPIO_DAT_PIN 0x00001000
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#define GPIO_DAT_PIN_I 0xffffefff
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#define GPIO_CLKDAT_PIN_I 0xffffcfff
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#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
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#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
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#define SET_GPIO_CLK_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLK_PIN_I);
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#define SET_GPIO_CLK_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_CLK_PIN);
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#define SET_GPIO_DAT_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_DAT_PIN_I);
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#define SET_GPIO_DAT_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_DAT_PIN);
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#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN)
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#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG)
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#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA)
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#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK)
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#define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
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#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
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#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
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#define SET_FPGA(data) out32(GPIO0_OR, data)
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#define SET_GPIO_CLK_0_Z1 out32(GPIO0_OR, (in32(GPIO0_OR) & GPIO_CLK_PIN_I) | GPIO_DAT_PIN);
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#define SET_GPIO_CLK_0_Z0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLKDAT_PIN_I);
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#define FPGA_WRITE_1 { \
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SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
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SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
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#define FPGA_WRITE_1 { \
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SET_GPIO_CLK_0_Z1\
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SET_GPIO_CLK_1}
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#define FPGA_WRITE_0 { \
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SET_GPIO_CLK_0_Z0\
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SET_GPIO_CLK_1}
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#define P_GP(reg) (reg & 0x00023f00)
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#define FPGA_WRITE_0 { \
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SET_FPGA(OLD_VAL | 0 | 0 ); /* set data to 0 */ \
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SET_FPGA(OLD_VAL | FPGA_CLK | 0 );} /* set data to 1 */
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/* Plattforminitializations */
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/* Here we have to set the FPGA Chain */
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@ -102,7 +94,7 @@ int fpga_pre_fn (int cookie)
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SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR);
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SET_GPIO_0((CFG_GPIO_SEL_DPR));
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/* initialize the GPIO Pins */
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/* initialize the GPIO Pins */
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/* output */
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SET_GPIO_0(CFG_GPIO_CLK);
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SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK);
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@ -174,7 +166,7 @@ int fpga_done_fn (int cookie)
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}
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/* writes the complete buffer to the FPGA
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writing the complete buffer in one function is very faster,
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writing the complete buffer in one function is much faster,
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then calling it for every bit */
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int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
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{
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@ -182,14 +174,10 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
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unsigned char *data = (unsigned char *) buf;
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unsigned char val=0;
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int i;
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int len_40 = len / 40;
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while (bytecount < len) {
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#ifdef CFG_FPGA_CHECK_CTRLC
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if (ctrlc ()) {
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return FPGA_FAIL;
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}
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#endif
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val = data[bytecount ++ ];
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val = data[bytecount++];
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i = 8;
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do {
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if (val & 0x01) {
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@ -202,8 +190,13 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
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} while (i > 0);
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#ifdef CFG_FPGA_PROG_FEEDBACK
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if (bytecount % (len / 40) == 0)
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if (bytecount % len_40 == 0) {
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putc ('.'); /* let them know we are alive */
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#ifdef CFG_FPGA_CHECK_CTRLC
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if (ctrlc ())
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return FPGA_FAIL;
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#endif
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}
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#endif
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}
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return FPGA_SUCCESS;
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@ -34,7 +34,6 @@
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#define SZ_64K 0x00000030
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#define SZ_256K 0x00000040
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#define SZ_1M 0x00000050
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#define SZ_8M 0x00000060
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#define SZ_16M 0x00000070
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#define SZ_256M 0x00000090
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@ -32,19 +32,19 @@
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#include <nand.h>
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struct alpr_ndfc_regs {
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u16 cmd[4];
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u16 addr_wait;
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u16 term;
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u16 dummy;
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u16 dummy2;
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u16 data;
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u8 cmd[4];
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u8 addr_wait;
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u8 term;
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u8 dummy;
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u8 dummy2;
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u8 data;
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};
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static u8 hwctl;
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static struct alpr_ndfc_regs *alpr_ndfc = NULL;
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#define readb(addr) (u8)(*(volatile u16 *)(addr))
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#define writeb(d,addr) *(volatile u16 *)(addr) = ((u16)(d))
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#define readb(addr) (u8)(*(volatile u8 *)(addr))
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#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
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/*
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* The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
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@ -470,8 +470,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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#else
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if ((devnum == 0) || (devnum == 1)) {
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out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
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}
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else { /* ((devnum == 2) || (devnum == 3)) */
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} else { /* ((devnum == 2) || (devnum == 3)) */
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out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
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out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
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(RGMII_FER_RGMII << RGMII_FER_V (3))));
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@ -808,7 +807,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
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hw_p->rx_ready[i] = -1;
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#if 0
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printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
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printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr);
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#endif
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}
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@ -426,8 +426,8 @@ int ppc440spe_revB() {
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#if defined(CONFIG_BOARD_RESET)
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board_reset();
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#if defined(CFG_4xx_RESET_TYPE)
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mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
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#else
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/*
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* Initiate system reset in debug control register DBCR
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@ -320,6 +320,10 @@ cpu_init_f (void)
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val |= 0xb8000000; /* generate system reset after 1.34 seconds */
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#else
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val |= 0xf0000000; /* generate system reset after 2.684 seconds */
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#endif
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#if defined(CFG_4xx_RESET_TYPE)
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val &= ~0x30000000; /* clear WRC bits */
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val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
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#endif
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mtspr(tcr, val);
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@ -31,25 +31,25 @@
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#define CONFIG_440GX 1 /* Specifc GX support */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_BOARD_RESET 1 /* call board_reset() */
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#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
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#undef CFG_DRAM_TEST /* Disable-takes long time! */
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#define CONFIG_SYS_CLK_FREQ 33333000 /* external freq to pll */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */
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#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
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#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
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#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
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#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
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#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */
|
||||
#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
|
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
|
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
|
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
|
||||
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
|
||||
|
||||
|
||||
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
|
||||
|
|
@ -84,26 +84,13 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
|
||||
|
||||
#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
|
||||
#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
|
||||
#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
|
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface.
|
||||
* All other boards should use the standard values (CPCI405 etc.)
|
||||
*/
|
||||
#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
|
||||
#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
|
||||
#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
|
||||
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
|
|
@ -154,7 +141,7 @@
|
|||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"netdev=eth3\0" \
|
||||
"hostname=alpr\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
|
|
@ -162,18 +149,19 @@
|
|||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
|
||||
"mem=193M\0" \
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=/tftpboot/alpr/uImage\0" \
|
||||
"rootpath=/opt/projects/alpr/nfs_root\0" \
|
||||
"bootfile=/alpr/uImage\0" \
|
||||
"kernel_addr=fff00000\0" \
|
||||
"ramdisk_addr=fff10000\0" \
|
||||
"load=tftp 100000 /tftpboot/alpr/u-boot.bin\0" \
|
||||
"load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
|
|
@ -181,7 +169,7 @@
|
|||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
|
|
@ -192,8 +180,8 @@
|
|||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
|
||||
#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
|
||||
#define CONFIG_PHY2_ADDR 0x00 /* test-only: will be changed */
|
||||
#define CONFIG_PHY3_ADDR 0x01 /* PHY address for EMAC3 */
|
||||
#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
|
||||
#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
|
|
@ -251,9 +239,11 @@
|
|||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
|
|
@ -264,7 +254,7 @@
|
|||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
|
||||
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
|
||||
#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
|
|
@ -276,11 +266,10 @@
|
|||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
*-----------------------------------------------------------------------*/
|
||||
#define CONFIG_FPGA CFG_ALTERA_CYCLON2
|
||||
#undef CFG_FPGA_CHECK_CTRLC
|
||||
#undef CFG_FPGA_PROG_FEEDBACK
|
||||
#define CFG_FPGA_CHECK_CTRLC
|
||||
#define CFG_FPGA_PROG_FEEDBACK
|
||||
#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
|
||||
Reihe geschaltet -> sollte gehen,
|
||||
aufpassen mit Datasize ist jetzt
|
||||
|
|
@ -299,9 +288,16 @@
|
|||
#define CFG_GPIO_SEL_AVR 15 /* cpu output */
|
||||
#define CFG_GPIO_PROG_EN 23 /* cpu output */
|
||||
|
||||
/*
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup
|
||||
*-----------------------------------------------------------------------*/
|
||||
#define CFG_GPIO_EREADY (0x80000000 >> 26)
|
||||
#define CFG_GPIO_REV0 (0x80000000 >> 14)
|
||||
#define CFG_GPIO_REV1 (0x80000000 >> 15)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND-FLASH stuff
|
||||
*/
|
||||
*-----------------------------------------------------------------------*/
|
||||
#define CFG_MAX_NAND_DEVICE 4
|
||||
#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
|
||||
#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
|
||||
|
|
@ -320,7 +316,7 @@
|
|||
|
||||
/* Memory Bank 1 (NAND-FLASH) initialization */
|
||||
#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */
|
||||
#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
|
||||
#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
|
|
@ -333,9 +329,7 @@
|
|||
*/
|
||||
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
|
|
|
|||
Loading…
Reference in New Issue