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85xx: Fix the clock adjust of mpc8569mds board 

Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.

Signed-off-by: Dave Liu <daveliu@freescale.com>
This commit is contained in:
Dave Liu 2009-03-27 14:32:43 +08:00 committed by Wolfgang Denk
parent f97db54d7e
commit 1b5291dddf
1 changed files with 1 additions and 1 deletions
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2
board/freescale/mpc8569mds/ddr.c
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@ -54,7 +54,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
popts->clk_adjust = 6;
popts->clk_adjust = 4;
/*
* Factors to consider for CPO: