Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx
This commit is contained in:
Wolfgang Denk
commit
1b33a62bf9
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@ -31,6 +31,8 @@
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#include <i2c.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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@ -38,6 +40,7 @@
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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@ -101,6 +104,9 @@ int board_early_init_f (void)
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*/
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im->clk.sccr[0] = SCCR1_CLOCKS_EN;
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im->clk.sccr[1] = SCCR2_CLOCKS_EN;
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN;
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#endif
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return 0;
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}
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@ -290,17 +296,28 @@ static iopin_t ioregs_init[] = {
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}
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};
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static iopin_t rev2_silicon_pci_ioregs_init[] = {
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/* FUNC0=PCI Sets next 54 to PCI pads */
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{
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IOCTL_PCI_AD31, 54, 0,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
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}
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};
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int checkboard (void)
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{
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ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
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uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
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brd_rev, cpld_rev);
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/* initialize function mux & slew rate IO inter alia on IO Pins */
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iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
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if (SVR_MJREV (im->sysconf.spridr) >= 2) {
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iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
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}
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return 0;
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}
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@ -312,3 +329,104 @@ void ft_board_setup(void *blob, bd_t *bd)
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
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void init_ide_reset (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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debug ("init_ide_reset\n");
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/*
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* Clear the reset bit to reset the interface
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* cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
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*/
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immr->pata.pata_ata_control = 0;
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udelay(100);
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/* Assert the reset bit to enable the interface */
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immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
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udelay(100);
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}
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void ide_set_reset (int idereset)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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debug ("ide_set_reset(%d)\n", idereset);
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if (idereset) {
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immr->pata.pata_ata_control = 0;
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udelay(100);
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} else {
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immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
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udelay(100);
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}
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}
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#define CALC_TIMING(t) (t + period - 1) / period
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int ide_preinit (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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long t;
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const struct {
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short t0;
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short t1;
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short t2_8;
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short t2_16;
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short t2i;
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short t4;
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short t9;
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short tA;
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} pio_specs = {
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.t0 = 600,
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.t1 = 70,
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.t2_8 = 290,
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.t2_16 = 165,
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.t2i = 0,
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.t4 = 30,
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.t9 = 20,
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.tA = 50,
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};
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union {
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u32 config;
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struct {
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u8 field1;
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u8 field2;
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u8 field3;
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u8 field4;
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}bytes;
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}cfg;
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debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
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(u32)&immr->pata);
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/* Set the reset bit to 1 to enable the interface */
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immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
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/* Init timings : we use PIO mode 0 timings */
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t = 1000000000 / gd->ips_clk; /* period in ns */
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cfg.bytes.field1 = 3;
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cfg.bytes.field2 = 3;
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cfg.bytes.field3 = (pio_specs.t1 + t) / t;
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cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
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immr->pata.pata_time1 = cfg.config;
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cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
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cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
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cfg.bytes.field3 = 1;
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cfg.bytes.field4 = (pio_specs.t4 + t) / t;
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immr->pata.pata_time2 = cfg.config;
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cfg.config = immr->pata.pata_time3;
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cfg.bytes.field1 = (pio_specs.t9 + t) / t;
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immr->pata.pata_time3 = cfg.config;
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debug ("PATA preinit complete.\n");
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return 0;
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}
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#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
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@ -37,7 +37,11 @@
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#include <video_fb.h>
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#endif
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#ifdef CONFIG_FSL_DIU_LOGO_BMP
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extern unsigned int FSL_Logo_BMP[];
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#else
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#define FSL_Logo_BMP NULL
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#endif
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static int xres, yres;
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@ -61,16 +65,40 @@ void diu_set_pixel_clock(unsigned int pixclock)
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debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
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}
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char *valid_bmp(char *addr)
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{
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unsigned long h_addr;
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h_addr = simple_strtoul(addr, NULL, 16);
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if (h_addr < CONFIG_SYS_FLASH_BASE ||
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h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
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printf("bmp addr %lx is not a valid flash address\n", h_addr);
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return 0;
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} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
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printf("bmp addr is not a bmp\n");
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return 0;
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} else
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return (char *)h_addr;
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}
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int ads5121_diu_init(void)
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{
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unsigned int pixel_format;
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char *bmp = NULL;
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char *bmp_env;
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xres = 1024;
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yres = 768;
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pixel_format = 0x88883316;
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return fsl_diu_init(xres, pixel_format, 0,
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(unsigned char *)FSL_Logo_BMP);
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debug("ads5121_diu_init\n");
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bmp_env = getenv("diu_bmp_addr");
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if (bmp_env) {
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bmp = valid_bmp(bmp_env);
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}
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if (!bmp)
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bmp = FSL_Logo_BMP;
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return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp);
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}
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int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
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@ -45,6 +45,10 @@
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#include <mpc5xxx.h>
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#endif
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#ifdef CONFIG_MPC512X
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#include <mpc512x.h>
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#endif
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#include <ide.h>
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#include <ata.h>
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@ -26,6 +26,9 @@ LIB = $(obj)lib$(CPU).a
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START = start.o
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COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
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ifdef CONFIG_IIM
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COBJS += iim.o
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endif
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -0,0 +1,394 @@
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/*
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* Copyright 2008 Silicon Turnkey Express, Inc.
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* Martha Marx <mmarx@silicontkx.com>
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*
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* ADS5121 IIM (Fusebox) Interface
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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|
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#ifdef CONFIG_CMD_FUSE
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DECLARE_GLOBAL_DATA_PTR;
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|
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static char cur_bank = '1';
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|
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char *iim_err_msg(u32 err)
|
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{
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static char *IIM_errs[] = {
|
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"Parity Error in cache",
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"Explicit Sense Cycle Error",
|
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"Write to Locked Register Error",
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"Read Protect Error",
|
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"Override Protect Error",
|
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"Write Protect Error"};
|
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|
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int i;
|
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|
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if (!err)
|
||||
return "";
|
||||
for (i = 1; i < 8; i++)
|
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if (err & (1 << i))
|
||||
printf("IIM - %s\n", IIM_errs[i-1]);
|
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return "";
|
||||
}
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|
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int in_range(int n, int min, int max, char *err, char *usg)
|
||||
{
|
||||
if (n > max || n < min) {
|
||||
printf(err);
|
||||
printf("Usage:\n%s\n", usg);
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
int ads5121_fuse_read(int bank, int fstart, int num)
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||||
{
|
||||
iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
|
||||
u32 *iim_fb, dummy;
|
||||
int f, ctr;
|
||||
|
||||
out_be32(&iim->err, in_be32(&iim->err));
|
||||
if (bank == 0)
|
||||
iim_fb = (u32 *)&(iim->fbac0);
|
||||
else
|
||||
iim_fb = (u32 *)&(iim->fbac1);
|
||||
/* try a read to see if Read Protect is set */
|
||||
dummy = in_be32(&iim_fb[0]);
|
||||
if (in_be32(&iim->err) & IIM_ERR_RPE) {
|
||||
printf("\tRead protect fuse is set\n");
|
||||
out_be32(&iim->err, IIM_ERR_RPE);
|
||||
return 0;
|
||||
}
|
||||
printf("Reading Bank %d cache\n", bank);
|
||||
for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) {
|
||||
if (ctr % 4 == 0)
|
||||
printf("F%2d:", f);
|
||||
printf("\t%#04x", (u8)(iim_fb[f]));
|
||||
if (ctr % 4 == 3)
|
||||
printf("\n");
|
||||
}
|
||||
if (ctr % 4 != 0)
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
int ads5121_fuse_override(int bank, int f, u8 val)
|
||||
{
|
||||
iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
|
||||
u32 *iim_fb;
|
||||
u32 iim_stat;
|
||||
int i;
|
||||
|
||||
out_be32(&iim->err, in_be32(&iim->err));
|
||||
if (bank == 0)
|
||||
iim_fb = (u32 *)&(iim->fbac0);
|
||||
else
|
||||
iim_fb = (u32 *)&(iim->fbac1);
|
||||
/* try a read to see if Read Protect is set */
|
||||
iim_stat = in_be32(&iim_fb[0]);
|
||||
if (in_be32(&iim->err) & IIM_ERR_RPE) {
|
||||
printf("Read protect fuse is set on bank %d;"
|
||||
"Override protect may also be set\n", bank);
|
||||
printf("An attempt will be made to override\n");
|
||||
out_be32(&iim->err, IIM_ERR_RPE);
|
||||
}
|
||||
if (iim_stat & IIM_FBAC_FBOP) {
|
||||
printf("Override protect fuse is set on bank %d\n", bank);
|
||||
return 1;
|
||||
}
|
||||
if (f > IIM_FMAX) /* reset the entire bank */
|
||||
for (i = 0; i < IIM_FMAX + 1; i++)
|
||||
out_be32(&iim_fb[i], 0);
|
||||
else
|
||||
out_be32(&iim_fb[f], val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ads5121_fuse_prog(cmd_tbl_t *cmdtp, int bank, char *fuseno_bitno)
|
||||
{
|
||||
iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
|
||||
int f, i, bitno;
|
||||
u32 stat, err;
|
||||
|
||||
f = simple_strtol(fuseno_bitno, NULL, 10);
|
||||
if (f == 0 && fuseno_bitno[0] != '0')
|
||||
f = -1;
|
||||
if (!in_range(f, 0, IIM_FMAX,
|
||||
"<frow> must be between 0-31\n\n", cmdtp->usage))
|
||||
return 1;
|
||||
bitno = -1;
|
||||
for (i = 0; i < 6; i++) {
|
||||
if (fuseno_bitno[i] == '_') {
|
||||
bitno = simple_strtol(&(fuseno_bitno[i+1]), NULL, 10);
|
||||
if (bitno == 0 && fuseno_bitno[i+1] != '0')
|
||||
bitno = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!in_range(bitno, 0, 7, "Bit number ranges from 0-7\n"
|
||||
"Example of <frow_bitno>: \"18_4\" sets bit 4 of row 18\n",
|
||||
cmdtp->usage))
|
||||
return 1;
|
||||
out_be32(&iim->err, in_be32(&iim->err));
|
||||
out_be32(&iim->prg_p, IIM_PRG_P_SET);
|
||||
out_be32(&iim->ua, IIM_SET_UA(bank, f));
|
||||
out_be32(&iim->la, IIM_SET_LA(f, bitno));
|
||||
#ifdef DEBUG
|
||||
printf("Programming disabled with DEBUG defined \n");
|
||||
printf(""Set up to pro
|
||||
printf("iim.ua = %x; iim.la = %x\n", iim->ua, iim->la);
|
||||
#else
|
||||
out_be32(&iim->fctl, IIM_FCTL_PROG_PULSE | IIM_FCTL_PROG);
|
||||
do
|
||||
udelay(20);
|
||||
while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
|
||||
out_be32(&iim->prg_p, 0);
|
||||
err = in_be32(&iim->err);
|
||||
if (stat & IIM_STAT_PRGD) {
|
||||
if (!(err & (IIM_ERR_WPE | IIM_ERR_WPE))) {
|
||||
printf("Fuse is successfully set");
|
||||
if (err)
|
||||
printf(" - however there are other errors");
|
||||
printf("\n");
|
||||
}
|
||||
iim->stat = 0;
|
||||
}
|
||||
if (err) {
|
||||
iim_err_msg(err);
|
||||
out_be32(&iim->err, in_be32(&iim->err));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
int ads5121_fuse_sense(int bank, int fstart, int num)
|
||||
{
|
||||
iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
|
||||
u32 iim_fbac;
|
||||
u32 stat, err, err_hold = 0;
|
||||
int f, ctr;
|
||||
|
||||
out_be32(&iim->err, in_be32(&iim->err));
|
||||
if (bank == 0)
|
||||
iim_fbac = in_be32(&iim->fbac0);
|
||||
else
|
||||
iim_fbac = in_be32(&iim->fbac1);
|
||||
if (iim_fbac & IIM_FBAC_FBESP) {
|
||||
printf("\tSense Protect disallows this operation\n");
|
||||
out_be32(&iim->err, IIM_FBAC_FBESP);
|
||||
return 1;
|
||||
}
|
||||
err = in_be32(&iim->err);
|
||||
if (err) {
|
||||
iim_err_msg(err);
|
||||
err_hold |= err;
|
||||
}
|
||||
if (err & IIM_ERR_RPE)
|
||||
printf("\tRead protect fuse is set; "
|
||||
"Sense Protect may be set but will be attempted\n");
|
||||
if (err)
|
||||
out_be32(&iim->err, err);
|
||||
printf("Sensing fuse(s) on Bank %d\n", bank);
|
||||
for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) {
|
||||
out_be32(&iim->ua, IIM_SET_UA(bank, f));
|
||||
out_be32(&iim->la, IIM_SET_LA(f, 0));
|
||||
out_be32(&iim->fctl, IIM_FCTL_ESNS_N);
|
||||
do
|
||||
udelay(20);
|
||||
while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
|
||||
err = in_be32(&iim->err);
|
||||
if (err & IIM_ERR_SNSE) {
|
||||
iim_err_msg(err);
|
||||
out_be32(&iim->err, IIM_ERR_SNSE);
|
||||
return 1;
|
||||
}
|
||||
if (stat & IIM_STAT_SNSD) {
|
||||
out_be32(&iim->stat, 0);
|
||||
if (ctr % 4 == 0)
|
||||
printf("F%2d:", f);
|
||||
printf("\t%#04x", (u8)iim->sdat);
|
||||
if (ctr % 4 == 3)
|
||||
printf("\n");
|
||||
}
|
||||
if (err) {
|
||||
err_hold |= err;
|
||||
out_be32(&iim->err, err);
|
||||
}
|
||||
}
|
||||
if (ctr % 4 != 0)
|
||||
printf("\n");
|
||||
if (err_hold)
|
||||
iim_err_msg(err_hold);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ads5121_fuse_stat(int bank)
|
||||
{
|
||||
iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
|
||||
u32 iim_fbac;
|
||||
u32 err;
|
||||
|
||||
out_be32(&iim->err, in_be32(&iim->err));
|
||||
if (bank == 0)
|
||||
iim_fbac = in_be32(&iim->fbac0);
|
||||
else
|
||||
iim_fbac = in_be32(&iim->fbac1);
|
||||
err = in_be32(&iim->err);
|
||||
if (err)
|
||||
iim_err_msg(err);
|
||||
if (err & IIM_ERR_RPE || iim_fbac & IIM_FBAC_FBRP) {
|
||||
if (iim_fbac == 0)
|
||||
printf("Since protection settings can't be read - "
|
||||
"try sensing fuse row 0;\n");
|
||||
return 0;
|
||||
}
|
||||
if (iim_fbac & IIM_PROTECTION)
|
||||
printf("Protection Fuses Bank %d = %#04x:\n", bank, iim_fbac);
|
||||
else if (!(err & IIM_ERR_RPE))
|
||||
printf("No Protection fuses are set\n");
|
||||
if (iim_fbac & IIM_FBAC_FBWP)
|
||||
printf("\tWrite Protect fuse is set\n");
|
||||
if (iim_fbac & IIM_FBAC_FBOP)
|
||||
printf("\tOverride Protect fuse is set\n");
|
||||
if (iim_fbac & IIM_FBAC_FBESP)
|
||||
printf("\tSense Protect Fuse is set\n");
|
||||
out_be32(&iim->err, in_be32(&iim->err));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_ads5121_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int frow, n, v, bank;
|
||||
|
||||
if (cur_bank == '0')
|
||||
bank = 0;
|
||||
else
|
||||
bank = 1;
|
||||
|
||||
switch (argc) {
|
||||
case 0:
|
||||
case 1:
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
case 2:
|
||||
if (strncmp(argv[1], "stat", 4) == 0)
|
||||
return ads5121_fuse_stat(bank);
|
||||
if (strncmp(argv[1], "read", 4) == 0)
|
||||
return ads5121_fuse_read(bank, 0, IIM_FMAX + 1);
|
||||
if (strncmp(argv[1], "sense", 5) == 0)
|
||||
return ads5121_fuse_sense(bank, 0, IIM_FMAX + 1);
|
||||
if (strncmp(argv[1], "ovride", 6) == 0)
|
||||
return ads5121_fuse_override(bank, IIM_FMAX + 1, 0);
|
||||
if (strncmp(argv[1], "bank", 4) == 0) {
|
||||
printf("Active Fuse Bank is %c\n", cur_bank);
|
||||
return 0;
|
||||
}
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
case 3:
|
||||
if (strncmp(argv[1], "bank", 4) == 0) {
|
||||
if (argv[2][0] == '0')
|
||||
cur_bank = '0';
|
||||
else if (argv[2][0] == '1')
|
||||
cur_bank = '1';
|
||||
else {
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
printf("Setting Active Fuse Bank to %c\n", cur_bank);
|
||||
return 0;
|
||||
}
|
||||
if (strncmp(argv[1], "prog", 4) == 0)
|
||||
return ads5121_fuse_prog(cmdtp, bank, argv[2]);
|
||||
|
||||
frow = (int)simple_strtol(argv[2], NULL, 10);
|
||||
if (frow == 0 && argv[2][0] != '0')
|
||||
frow = -1;
|
||||
if (!in_range(frow, 0, IIM_FMAX,
|
||||
"<frow> must be between 0-31\n\n", cmdtp->usage))
|
||||
return 1;
|
||||
if (strncmp(argv[1], "read", 4) == 0)
|
||||
return ads5121_fuse_read(bank, frow, 1);
|
||||
if (strncmp(argv[1], "ovride", 6) == 0)
|
||||
return ads5121_fuse_override(bank, frow, 0);
|
||||
if (strncmp(argv[1], "sense", 5) == 0)
|
||||
return ads5121_fuse_sense(bank, frow, 1);
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
case 4:
|
||||
frow = (int)simple_strtol(argv[2], NULL, 10);
|
||||
if (frow == 0 && argv[2][0] != '0')
|
||||
frow = -1;
|
||||
if (!in_range(frow, 0, IIM_FMAX,
|
||||
"<frow> must be between 0-31\n\n", cmdtp->usage))
|
||||
return 1;
|
||||
if (strncmp(argv[1], "read", 4) == 0) {
|
||||
n = (int)simple_strtol(argv[3], NULL, 10);
|
||||
if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
|
||||
"<frow>+<n> must be between 1-32\n\n",
|
||||
cmdtp->usage))
|
||||
return 1;
|
||||
return ads5121_fuse_read(bank, frow, n);
|
||||
}
|
||||
if (strncmp(argv[1], "ovride", 6) == 0) {
|
||||
v = (int)simple_strtol(argv[3], NULL, 10);
|
||||
return ads5121_fuse_override(bank, frow, v);
|
||||
}
|
||||
if (strncmp(argv[1], "sense", 5) == 0) {
|
||||
n = (int)simple_strtol(argv[3], NULL, 10);
|
||||
if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
|
||||
"<frow>+<n> must be between 1-32\n\n",
|
||||
cmdtp->usage))
|
||||
return 1;
|
||||
return ads5121_fuse_sense(bank, frow, n);
|
||||
}
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
default: /* at least 5 args */
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
fuse, CONFIG_SYS_MAXARGS, 0, do_ads5121_fuse,
|
||||
" - Read, Sense, Override or Program Fuses\n",
|
||||
"bank <n> - sets active Fuse Bank to 0 or 1\n"
|
||||
" no args shows current active bank\n"
|
||||
"fuse stat - print active fuse bank's protection status\n"
|
||||
"fuse read [<frow> [<n>]] - print <n> fuse rows starting at <frow>\n"
|
||||
" no args to print entire bank's fuses\n"
|
||||
"fuse ovride [<frow> [<v>]]- override fuses at <frow> with <v>\n"
|
||||
" no <v> defaults to 0 for the row\n"
|
||||
" no args resets entire bank to 0\n"
|
||||
" NOTE - settings persist until hard reset\n"
|
||||
"fuse sense [<frow>] - senses current fuse at <frow>\n"
|
||||
" no args for entire bank\n"
|
||||
"fuse prog <frow_bit> - program fuse at row <frow>, bit <_bit>\n"
|
||||
" <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n"
|
||||
" WARNING - this is permanent\n"
|
||||
);
|
||||
#endif /* CONFIG_CMD_FUSE */
|
||||
|
|
@ -415,7 +415,25 @@ typedef struct ioctrl512x {
|
|||
* IIM
|
||||
*/
|
||||
typedef struct iim512x {
|
||||
u8 fixme[0x1000];
|
||||
u32 stat; /* IIM status register */
|
||||
u32 statm; /* IIM status IRQ mask */
|
||||
u32 err; /* IIM errors register */
|
||||
u32 emask; /* IIM error IRQ mask */
|
||||
u32 fctl; /* IIM fuse control register */
|
||||
u32 ua; /* IIM upper address register */
|
||||
u32 la; /* IIM lower address register */
|
||||
u32 sdat; /* IIM explicit sense data */
|
||||
u8 res0[0x08];
|
||||
u32 prg_p; /* IIM program protection register */
|
||||
u8 res1[0x10];
|
||||
u32 divide; /* IIM divide factor register */
|
||||
u8 res2[0x7c0];
|
||||
u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */
|
||||
u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */
|
||||
u8 res3[0x380];
|
||||
u32 fbac1; /* IIM fuse bank 1 protection */
|
||||
u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */
|
||||
u8 res4[0x380];
|
||||
} iim512x_t;
|
||||
|
||||
/*
|
||||
|
|
@ -451,7 +469,34 @@ typedef struct lpc512x {
|
|||
* PATA
|
||||
*/
|
||||
typedef struct pata512x {
|
||||
u8 fixme[0x100];
|
||||
/* LOCAL Registers */
|
||||
u32 pata_time1; /* Time register 1: PIO and tx timing parameter */
|
||||
u32 pata_time2; /* Time register 2: PIO timing parameter */
|
||||
u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */
|
||||
u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */
|
||||
u32 pata_time5; /* Time register 5: UDMA timing parameter */
|
||||
u32 pata_time6; /* Time register 6: UDMA timing parameter */
|
||||
u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */
|
||||
u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */
|
||||
u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/
|
||||
u32 pata_ata_control; /* ATA Interface control register */
|
||||
u32 pata_irq_pending; /* Interrupt pending register (READONLY) */
|
||||
u32 pata_irq_enable; /* Interrupt enable register */
|
||||
u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/
|
||||
u32 pata_fifo_alarm; /* fifo alarm threshold */
|
||||
u32 res1[0x1A];
|
||||
/* DRIVE Registers */
|
||||
u32 pata_drive_data; /* drive data register*/
|
||||
u32 pata_drive_features;/* drive features register */
|
||||
u32 pata_drive_sectcnt; /* drive sector count register */
|
||||
u32 pata_drive_sectnum; /* drive sector number register */
|
||||
u32 pata_drive_cyllow; /* drive cylinder low register */
|
||||
u32 pata_drive_cylhigh; /* drive cylinder high register */
|
||||
u32 pata_drive_dev_head;/* drive device head register */
|
||||
u32 pata_drive_command; /* write = drive command, read = drive status reg */
|
||||
u32 res2[0x06];
|
||||
u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
|
||||
u32 res3[0x09];
|
||||
} pata512x_t;
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@
|
|||
#define CONFIG_E300 1 /* E300 Family */
|
||||
#define CONFIG_MPC512X 1 /* MPC512X family */
|
||||
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
|
||||
#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */
|
||||
|
||||
/* video */
|
||||
#undef CONFIG_VIDEO
|
||||
|
|
@ -293,6 +294,11 @@
|
|||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IIM - IC Identification Module
|
||||
*/
|
||||
#undef CONFIG_IIM
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
|
|
@ -348,11 +354,20 @@
|
|||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_DATE
|
||||
#undef CONFIG_CMD_FUSE
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_EXT2
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_IDE)
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
#endif /* defined(CONFIG_CMD_IDE) */
|
||||
|
||||
/*
|
||||
* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
|
||||
* For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
|
||||
|
|
@ -489,4 +504,48 @@
|
|||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for IDE not supported */
|
||||
|
||||
#define CONFIG_IDE_RESET /* reset for IDE supported */
|
||||
#define CONFIG_IDE_PREINIT
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA
|
||||
|
||||
/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
|
||||
|
||||
/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
|
||||
|
||||
/* Interval between registers */
|
||||
#define CONFIG_SYS_ATA_STRIDE 4
|
||||
|
||||
#define ATA_BASE_ADDR MPC512X_PATA
|
||||
|
||||
/*
|
||||
* Control register bit definitions
|
||||
*/
|
||||
#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
|
||||
#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
|
||||
#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
|
||||
#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
|
||||
#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
|
||||
#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
|
||||
#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
|
||||
#define FSL_ATA_CTRL_IORDY_EN 0x01000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -573,6 +573,31 @@ void iopin_initialize(iopin_t *,int);
|
|||
|
||||
/* Register Offset Base */
|
||||
#define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800)
|
||||
#define MPC512X_PATA (CONFIG_SYS_IMMR + 0x10200)
|
||||
|
||||
/* IIM control */
|
||||
#define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5))
|
||||
#define IIM_SET_LA(f, bit) (((f & 0x0000001f) << 3) | bit)
|
||||
#define IIM_STAT_BUSY 0x00000080
|
||||
#define IIM_STAT_PRGD 0x00000002
|
||||
#define IIM_STAT_SNSD 0x00000001
|
||||
#define IIM_ERR_WPE 0x00000040
|
||||
#define IIM_ERR_OPE 0x00000020
|
||||
#define IIM_ERR_RPE 0x00000010
|
||||
#define IIM_ERR_WLRE 0x00000008
|
||||
#define IIM_ERR_SNSE 0x00000004
|
||||
#define IIM_ERR_PARITYE 0x00000002
|
||||
#define IIM_PRG_P_SET 0x000000aa
|
||||
#define IIM_PRG_P_UNSET 0
|
||||
#define IIM_FCTL_PROG_PULSE 0x00000020
|
||||
#define IIM_FCTL_PROG 0x00000001
|
||||
#define IIM_FCTL_ESNS_N 0x00000008
|
||||
#define IIM_FBAC_FBWP 0x00000080
|
||||
#define IIM_FBAC_FBOP 0x00000040
|
||||
#define IIM_FBAC_FBRP 0x00000020
|
||||
#define IIM_FBAC_FBESP 0x00000008
|
||||
#define IIM_PROTECTION 0x000000e8
|
||||
#define IIM_FMAX 31
|
||||
|
||||
/* Number of I2C buses */
|
||||
#define I2C_BUS_CNT 3
|
||||
|
|
|
|||
Loading…
Reference in New Issue