ARM: Add support for jadecpu board based on MB86R01 SoC
This patch adds support for the jadecpu board using the MB86R01 'Jade' SoC from Fujitsu. Signed-off-by: Matthias Weisser <weisserm@arcor.de>
This commit is contained in:
Matthias Weisser
Wolfgang Denk
parent
b2621bcb8c
commit
18a056a18f
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@ -806,6 +806,10 @@ Prafulla Wadaskar <prafulla@marvell.com>
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rd6281a ARM926EJS (Kirkwood SoC)
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sheevaplug ARM926EJS (Kirkwood SoC)
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Matthias Weisser <weisserm@arcor.de>
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jadecpu ARM926EJS (MB86R01 SoC)
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Richard Woodruff <r-woodruff2@ti.com>
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omap2420h4 ARM1136EJS
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1
MAKEALL
1
MAKEALL
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@ -579,6 +579,7 @@ LIST_ARM9=" \
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edminiv2 \
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guruplug \
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imx27lite \
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jadecpu \
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lpd7a400 \
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magnesium \
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mv88f6281gtw_ge \
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@ -0,0 +1,55 @@
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian.pop@leadtechdesign.com>
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# Lead Tech Design <www.leadtechdesign.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += jadecpu.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1 @@
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TEXT_BASE = 0x46000000
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@ -0,0 +1,170 @@
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/*
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* (c) 2010 Graf-Syteco, Matthias Weisser
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* <weisserm@arcor.de>
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*
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* (C) Copyright 2007, mycable GmbH
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* Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/mb86r0x.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
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MB86R0x_CCNT_BASE;
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/* We select mode 0 for group 2 and mode 1 for group 4 */
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writel(0x00000010, &ccnt->cmux_md);
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gd->flags = 0;
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gd->bd->bi_arch_number = MACH_TYPE_JADECPU;
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gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
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icache_enable();
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return 0;
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}
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static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
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unsigned long pwm_base)
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{
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struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
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MB86R0x_GPIO_BASE;
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struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
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const char *e;
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writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
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e = getenv(pwm_opts);
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if (e != NULL) {
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const char *s;
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uint32_t freq, init;
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freq = 0;
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init = 0;
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s = strchr(e, 'f');
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if (s != NULL)
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freq = simple_strtol(s + 2, NULL, 0);
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s = strchr(e, 'i');
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if (s != NULL)
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init = simple_strtol(s + 2, NULL, 0);
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if (freq > 0) {
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writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
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&pwm->bcr);
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writel(1002, &pwm->tpr);
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writel(1, &pwm->pr);
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writel(init * 10 + 1, &pwm->dr);
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writel(1, &pwm->cr);
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writel(1, &pwm->sr);
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}
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}
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}
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int board_late_init(void)
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{
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struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
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MB86R0x_GPIO_BASE;
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uint32_t in_word;
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#ifdef CONFIG_VIDEO_MB86R0xGDC
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/* Check if we have valid display settings and turn on power if so */
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/* Display 0 */
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if (getenv("gs_dsp_0_param") || getenv("videomode"))
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setup_display_power((1 << 3), "gs_dsp_0_pwm",
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MB86R0x_PWM0_BASE);
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/* The corresponding GPIO is always an output */
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writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
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/* Display 1 */
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if (getenv("gs_dsp_1_param") || getenv("videomode1"))
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setup_display_power((1 << 4), "gs_dsp_1_pwm",
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MB86R0x_PWM1_BASE);
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/* The corresponding GPIO is always an output */
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writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
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#endif /* CONFIG_VIDEO_MB86R0xGDC */
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/* 5V enable */
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writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
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writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
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/* We have special boot options if told by GPIOs */
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in_word = readl(&gpio->gpdr1);
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if ((in_word & 0xC0) == 0xC0) {
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setenv("stdin", "serial");
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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setenv("preboot", "run gs_slow_boot");
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} else if ((in_word & 0xC0) != 0) {
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setenv("stdout", "vga");
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setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;"
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"fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;"
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"bootelf 0x40000000; bootelf 0x10080000");
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setenv("preboot", "run gs_slow_boot");
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} else {
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setenv("stdin", "serial");
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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if (getenv("gs_devel")) {
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setenv("preboot", "run gs_slow_boot");
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} else {
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setenv("gs_bootcmd", "bootelf 0x10080000");
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setenv("preboot", "run gs_fast_boot");
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}
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}
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return 0;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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/*
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* DRAM configuration
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*/
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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@ -0,0 +1,265 @@
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/*
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* Board specific setup info
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*
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* (C) Copyright 2007, mycable GmbH
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* Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
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*
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* (C) Copyright 2003, ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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#include <asm/arch/mb86r0x.h>
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#include <asm/arch/asm-offsets.h>
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/* Set up the platform, once the cpu has been initialized */
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Initialize Clock Reset Generator (CRG)
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*/
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ldr r0, =MB86R0x_CRG_BASE
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/* Not change the initial value that is set by external pin.*/
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WAIT_PLL:
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ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
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tst r2, #MB86R0x_CRG_CRPR_PLLRDY
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beq WAIT_PLL
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/* Set clock gate control */
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ldr r1, =CONFIG_SYS_CRG_CRHA_INIT
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str r1, [r0, #CRG_CRHA]
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ldr r1, =CONFIG_SYS_CRG_CRPA_INIT
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str r1, [r0, #CRG_CRPA]
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ldr r1, =CONFIG_SYS_CRG_CRPB_INIT
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str r1, [r0, #CRG_CRPB]
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ldr r1, =CONFIG_SYS_CRG_CRHB_INIT
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str r1, [r0, #CRG_CRHB]
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ldr r1, =CONFIG_SYS_CRG_CRAM_INIT
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str r1, [r0, #CRG_CRAM]
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/*
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* Initialize External Bus Interface
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*/
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ldr r0, =MB86R0x_MEMC_BASE
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
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str r1, [r0, #MEMC_MCFMODE0]
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
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str r1, [r0, #MEMC_MCFMODE2]
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
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str r1, [r0, #MEMC_MCFMODE4]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
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str r1, [r0, #MEMC_MCFTIM0]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
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str r1, [r0, #MEMC_MCFTIM2]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
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str r1, [r0, #MEMC_MCFTIM4]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
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str r1, [r0, #MEMC_MCFAREA0]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
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str r1, [r0, #MEMC_MCFAREA2]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
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str r1, [r0, #MEMC_MCFAREA4]
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/*
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* Initialize DDR2 Controller
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*/
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/* Wait for PLL LOCK up time or more */
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wait_timer 20
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/*
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* (2) Initialize DDRIF
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*/
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ldr r0, =MB86R0x_DDR2_BASE
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ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT
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strh r1, [r0, #DDR2_DRIMS]
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/*
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* (3) Wait for 20MCKPs(120nsec) or more
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*/
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wait_timer 20
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/*
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* (4) IRESET/IUSRRST release
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*/
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ldr r0, =MB86R0x_CCNT_BASE
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ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
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str r1, [r0, #CCNT_CDCRC]
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/*
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* (5) Wait for 20MCKPs(120nsec) or more
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*/
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wait_timer 20
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/*
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* (6) IDLLRST release
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*/
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ldr r0, =MB86R0x_CCNT_BASE
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ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
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str r1, [r0, #CCNT_CDCRC]
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/*
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* (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
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*/
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wait_timer 33536
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/*
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* (9) MCKE ON
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*/
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ldr r0, =MB86R0x_DDR2_BASE
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ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT
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strh r1, [r0, #DDR2_DRCA]
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ldr r1, =MB86R0x_DDR2_DRCI_INIT
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strh r1, [r0, #DDR2_DRIC]
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/*
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* (10) Initialize SDRAM
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*/
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 67 /* 400ns wait */
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 200
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
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strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
wait_timer 18 /* 105ns wait */
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
wait_timer 200 /* MRS to OCD: 200clock */
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT
|
||||
strh r1, [r0, #DDR2_DRCM]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT
|
||||
strh r1, [r0, #DDR2_DRCST1]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT
|
||||
strh r1, [r0, #DDR2_DRCST2]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT
|
||||
strh r1, [r0, #DDR2_DRCR]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT
|
||||
strh r1, [r0, #DDR2_DRCF]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT
|
||||
strh r1, [r0, #DDR2_DRASR]
|
||||
|
||||
/*
|
||||
* (11) ODT setting
|
||||
*/
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT
|
||||
strh r1, [r0, #DDR2_DROBS]
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT
|
||||
strh r1, [r0, #DDR2_DROABA]
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
|
||||
strh r1, [r0, #DDR2_DRIBSODT1]
|
||||
|
||||
/*
|
||||
* (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
|
||||
*/
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROS_INIT
|
||||
strh r1, [r0, #DDR2_DROS]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_NORMAL
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -43,6 +43,7 @@ meesc arm arm926ejs - esd at91
|
|||
otc570 arm arm926ejs - esd at91
|
||||
pm9261 arm arm926ejs - ronetix at91
|
||||
pm9263 arm arm926ejs - ronetix at91
|
||||
jadecpu arm arm926ejs jadecpu syteco mb86r0x
|
||||
suen3 arm arm926ejs km_arm keymile kirkwood
|
||||
rd6281a arm arm926ejs - Marvell kirkwood
|
||||
mx51evk arm armv7 mx51evk freescale mx51
|
||||
|
|
|
|||
|
|
@ -0,0 +1,291 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Matthias Weisser <weisserm@arcor.de>
|
||||
*
|
||||
* Configuation settings for the jadecpu board
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MB86R0x
|
||||
#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"gs_fast_boot=setenv bootdelay 5\0" \
|
||||
"gs_slow_boot=setenv bootdelay 10\0" \
|
||||
"bootcmd=mw.l 0x40000000 0 1024; usb start;" \
|
||||
"fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
|
||||
"bootelf 0x40000000\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#define BOARD_LATE_INIT 1
|
||||
|
||||
/*
|
||||
* Compressions
|
||||
*/
|
||||
#define CONFIG_LZO
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* Serial
|
||||
*/
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */
|
||||
#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */
|
||||
#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */
|
||||
#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */
|
||||
|
||||
#define CONFIG_CONS_INDEX 4
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_BASE 0x02000000
|
||||
#define CONFIG_SMC911X_16_BIT
|
||||
|
||||
/*
|
||||
* Video
|
||||
*/
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MB86R0xGDC
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_VIDEO_BMP_GZIP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
|
||||
#define VIDEO_FB_16BPP_WORD_SWAP
|
||||
#define VIDEO_KBD_INIT_FCT 0
|
||||
#define VIDEO_TSTC_FCT serial_tstc
|
||||
#define VIDEO_GETC_FCT serial_getc
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1
|
||||
#define CONFIG_BOOTP_BOOTPATH 1
|
||||
#define CONFIG_BOOTP_GATEWAY 1
|
||||
#define CONFIG_BOOTP_HOSTNAME 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_SOURCE
|
||||
#undef CONFIG_CMD_NFS
|
||||
#undef CONFIG_CMD_XIMG
|
||||
|
||||
#define CONFIG_CMD_BMP 1
|
||||
#define CONFIG_CMD_CAN 1
|
||||
#define CONFIG_CMD_DHCP 1
|
||||
#define CONFIG_CMD_ELF 1
|
||||
#define CONFIG_CMD_FAT 1
|
||||
#define CONFIG_CMD_PING 1
|
||||
#define CONFIG_CMD_USB 1
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */
|
||||
#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0x10000000
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE (128 * 1024)
|
||||
|
||||
/*
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
|
||||
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CONFIG_SYS_PROMPT "jade> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
|
||||
#define CONFIG_PREBOOT ""
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
#define CONFIG_AUTOBOOT_KEYED
|
||||
#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
|
||||
#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
|
||||
|
||||
/*
|
||||
* Clock reset generator init
|
||||
*/
|
||||
#define CONFIG_SYS_CRG_CRHA_INIT 0xffff
|
||||
#define CONFIG_SYS_CRG_CRPA_INIT 0xffff
|
||||
#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe
|
||||
#define CONFIG_SYS_CRG_CRHB_INIT 0xffff
|
||||
#define CONFIG_SYS_CRG_CRAM_INIT 0xffef
|
||||
|
||||
/*
|
||||
* Memory controller settings
|
||||
*/
|
||||
#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */
|
||||
#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */
|
||||
#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/
|
||||
#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008
|
||||
#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008
|
||||
#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804
|
||||
#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */
|
||||
#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */
|
||||
#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */
|
||||
|
||||
/*
|
||||
* DDR2 controller init settings
|
||||
*/
|
||||
#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555
|
||||
#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002
|
||||
#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003
|
||||
#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f
|
||||
#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000
|
||||
#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */
|
||||
#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032
|
||||
#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418
|
||||
#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32
|
||||
#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141
|
||||
#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002
|
||||
#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001
|
||||
#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001
|
||||
#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103
|
||||
#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F
|
||||
#define CONFIG_SYS_DDR2_DROS_INIT 0x0001
|
||||
|
||||
/*
|
||||
* DRAM init sequence
|
||||
*/
|
||||
|
||||
/* PALL Command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400
|
||||
|
||||
/* EMR(2) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000
|
||||
|
||||
/* EMR(3) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000
|
||||
|
||||
/* EMR(1) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000
|
||||
|
||||
/* MRS command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532
|
||||
|
||||
/* PALL command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400
|
||||
|
||||
/* REF command 1 */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000
|
||||
|
||||
/* MRS command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432
|
||||
|
||||
/* EMR(1) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380
|
||||
|
||||
/* EMR(1) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -118,6 +118,9 @@ endif
|
|||
ifeq ($(VENDOR),ronetix)
|
||||
LOGO_BMP= logos/ronetix.bmp
|
||||
endif
|
||||
ifeq ($(VENDOR),syteco)
|
||||
LOGO_BMP= logos/syteco.bmp
|
||||
endif
|
||||
|
||||
# now $(obj) is defined
|
||||
HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
|
||||
|
|
|
|||
Binary file not shown.
|
After Width: | Height: | Size: 11 KiB |
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Reference in New Issue