Blackfin: add support for BF538/BF539 processors
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
2e6e1772c0
commit
180e311f28
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@ -42,6 +42,12 @@
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#ifdef __ADSPBF537__
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# include "mach-bf537/BF537_cdef.h"
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#endif
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#ifdef __ADSPBF538__
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# include "mach-bf538/BF538_cdef.h"
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#endif
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#ifdef __ADSPBF539__
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# include "mach-bf538/BF539_cdef.h"
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#endif
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#ifdef __ADSPBF541__
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# include "mach-bf548/BF541_cdef.h"
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#endif
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@ -66,6 +66,16 @@
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# include "mach-bf537/anomaly.h"
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# include "mach-bf537/def_local.h"
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#endif
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#ifdef __ADSPBF538__
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# include "mach-bf538/BF538_def.h"
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# include "mach-bf538/anomaly.h"
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# include "mach-bf538/def_local.h"
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#endif
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#ifdef __ADSPBF539__
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# include "mach-bf538/BF539_def.h"
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# include "mach-bf538/anomaly.h"
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# include "mach-bf538/def_local.h"
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#endif
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#ifdef __ADSPBF541__
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# include "mach-bf548/BF541_def.h"
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# include "mach-bf548/anomaly.h"
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#include "BF538_cdef.h"
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#include "BF538_def.h"
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/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2010 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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/* This file should be up to date with:
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* - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
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* - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support old silicon - sorry */
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#if __SILICON_REVISION__ < 4
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# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
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#endif
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#if defined(__ADSPBF538__)
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# define ANOMALY_BF538 1
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#else
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# define ANOMALY_BF538 0
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#endif
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#if defined(__ADSPBF539__)
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# define ANOMALY_BF539 1
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#else
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# define ANOMALY_BF539 0
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#endif
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
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#define ANOMALY_05000166 (1)
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/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
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#define ANOMALY_05000179 (1)
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/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
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#define ANOMALY_05000180 (1)
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/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
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#define ANOMALY_05000193 (1)
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/* Current DMA Address Shows Wrong Value During Carry Fix */
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#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
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/* NMI Event at Boot Time Results in Unpredictable State */
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#define ANOMALY_05000219 (1)
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/* SPI Slave Boot Mode Modifies Registers from Reset Value */
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#define ANOMALY_05000229 (1)
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/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
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#define ANOMALY_05000233 (1)
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/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Maximum External Clock Speed for Timers */
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#define ANOMALY_05000253 (1)
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/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
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#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
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#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* Writes to Synchronous SDRAM Memory May Be Lost */
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#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
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/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
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/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
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#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
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/* False Hardware Error Exception when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
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/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
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/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
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#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
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/* SPORTs May Receive Bad Data If FIFOs Fill Up */
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#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
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/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
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#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
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/* Hibernate Leakage Current Is Higher Than Specified */
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#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
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/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
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#define ANOMALY_05000294 (1)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
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/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
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#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
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/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
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#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
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/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
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#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
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/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
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#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
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/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
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#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
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#define ANOMALY_05000425 (1)
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* Specific GPIO Pins May Change State when Entering Hibernate */
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#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000149 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000171 (0)
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#define ANOMALY_05000182 (0)
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#define ANOMALY_05000189 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000234 (0)
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#define ANOMALY_05000242 (0)
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#define ANOMALY_05000248 (0)
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#define ANOMALY_05000250 (0)
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#define ANOMALY_05000254 (0)
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#define ANOMALY_05000257 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000274 (0)
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#define ANOMALY_05000287 (0)
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#define ANOMALY_05000305 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000362 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000364 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000386 (1)
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#define ANOMALY_05000389 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000430 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#define ANOMALY_05000456 (0)
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#define ANOMALY_05000450 (0)
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000485 (0)
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#endif
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@ -0,0 +1,5 @@
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#include "gpio.h"
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#include "portmux.h"
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#include "ports.h"
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#define BF538_FAMILY 1 /* Linux glue */
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/*
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* Copyright (C) 2008-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_GPIO_H_
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#define _MACH_GPIO_H_
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#define MAX_BLACKFIN_GPIOS 16
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#define BFIN_SPECIAL_GPIO_BANKS 3
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#define GPIO_PF0 0 /* PF */
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#define GPIO_PF1 1
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#define GPIO_PF2 2
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#define GPIO_PF3 3
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#define GPIO_PF4 4
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#define GPIO_PF5 5
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#define GPIO_PF6 6
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#define GPIO_PF7 7
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#define GPIO_PF8 8
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#define GPIO_PF9 9
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#define GPIO_PF10 10
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#define GPIO_PF11 11
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#define GPIO_PF12 12
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#define GPIO_PF13 13
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#define GPIO_PF14 14
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#define GPIO_PF15 15
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#define GPIO_PC0 16 /* PC */
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#define GPIO_PC1 17
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#define GPIO_PC4 20
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#define GPIO_PC5 21
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#define GPIO_PC6 22
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#define GPIO_PC7 23
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#define GPIO_PC8 24
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#define GPIO_PC9 25
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#define GPIO_PD0 32 /* PD */
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#define GPIO_PD1 33
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#define GPIO_PD2 34
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#define GPIO_PD3 35
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#define GPIO_PD4 36
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#define GPIO_PD5 37
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#define GPIO_PD6 38
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#define GPIO_PD7 39
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#define GPIO_PD8 40
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#define GPIO_PD9 41
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#define GPIO_PD10 42
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#define GPIO_PD11 43
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#define GPIO_PD12 44
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#define GPIO_PD13 45
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#define GPIO_PE0 48 /* PE */
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#define GPIO_PE1 49
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#define GPIO_PE2 50
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#define GPIO_PE3 51
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#define GPIO_PE4 52
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#define GPIO_PE5 53
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#define GPIO_PE6 54
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#define GPIO_PE7 55
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#define GPIO_PE8 56
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#define GPIO_PE9 57
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#define GPIO_PE10 58
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#define GPIO_PE11 59
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#define GPIO_PE12 60
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#define GPIO_PE13 61
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#define GPIO_PE14 62
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#define GPIO_PE15 63
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#define PORT_F GPIO_PF0
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#define PORT_C GPIO_PC0
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#define PORT_D GPIO_PD0
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#define PORT_E GPIO_PE0
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#endif /* _MACH_GPIO_H_ */
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@ -0,0 +1,114 @@
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/*
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* Copyright 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_PORTMUX_H_
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#define _MACH_PORTMUX_H_
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#define MAX_RESOURCES 64
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#define P_TMR2 (P_DONTCARE)
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#define P_TMR1 (P_DONTCARE)
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#define P_TMR0 (P_DONTCARE)
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#define P_TMRCLK (P_DONTCARE)
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#define P_PPI0_CLK (P_DONTCARE)
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#define P_PPI0_FS1 (P_DONTCARE)
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#define P_PPI0_FS2 (P_DONTCARE)
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#define P_TWI0_SCL (P_DONTCARE)
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#define P_TWI0_SDA (P_DONTCARE)
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#define P_TWI1_SCL (P_DONTCARE)
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#define P_TWI1_SDA (P_DONTCARE)
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#define P_SPORT1_TSCLK (P_DONTCARE)
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#define P_SPORT1_RSCLK (P_DONTCARE)
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#define P_SPORT0_TSCLK (P_DONTCARE)
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#define P_SPORT0_RSCLK (P_DONTCARE)
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#define P_SPORT1_DRSEC (P_DONTCARE)
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#define P_SPORT1_RFS (P_DONTCARE)
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#define P_SPORT1_DTPRI (P_DONTCARE)
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#define P_SPORT1_DTSEC (P_DONTCARE)
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#define P_SPORT1_TFS (P_DONTCARE)
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#define P_SPORT1_DRPRI (P_DONTCARE)
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#define P_SPORT0_DRSEC (P_DONTCARE)
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#define P_SPORT0_RFS (P_DONTCARE)
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#define P_SPORT0_DTPRI (P_DONTCARE)
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#define P_SPORT0_DTSEC (P_DONTCARE)
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#define P_SPORT0_TFS (P_DONTCARE)
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#define P_SPORT0_DRPRI (P_DONTCARE)
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#define P_UART0_RX (P_DONTCARE)
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#define P_UART0_TX (P_DONTCARE)
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#define P_SPI0_MOSI (P_DONTCARE)
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#define P_SPI0_MISO (P_DONTCARE)
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#define P_SPI0_SCK (P_DONTCARE)
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#define P_PPI0_D0 (P_DONTCARE)
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#define P_PPI0_D1 (P_DONTCARE)
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#define P_PPI0_D2 (P_DONTCARE)
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#define P_PPI0_D3 (P_DONTCARE)
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#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
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#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
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#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
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#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
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#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
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#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
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#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
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#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
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#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
|
||||
#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
|
||||
#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
|
||||
#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
|
||||
#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
|
||||
#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
|
||||
|
||||
#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
|
||||
#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
|
||||
#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
|
||||
#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
|
||||
#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
|
||||
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
|
||||
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
|
||||
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
|
||||
#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
|
||||
#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
|
||||
#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
|
||||
#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
|
||||
#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
|
||||
#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
|
||||
#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
|
||||
#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
|
||||
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
|
||||
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
|
||||
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
|
||||
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
|
||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
|
||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
|
||||
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
|
||||
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Port Masks
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_PERIPHERAL_PORT__
|
||||
#define __BFIN_PERIPHERAL_PORT__
|
||||
|
||||
#include "../mach-common/bits/ports-c.h"
|
||||
#include "../mach-common/bits/ports-d.h"
|
||||
#include "../mach-common/bits/ports-e.h"
|
||||
#include "../mach-common/bits/ports-f.h"
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue