ppc4xx/Canyonlands added USB board callbacks
Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot. Signed-off-by: Dave Mitchell <dmitchell@appliedmicro.com> Signed-off-by: Rupjyoti Sarmah <rsarmah@appliedmicro.com> Signed-off-by: Stefan Roese <sr@denx.de>
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@ -34,7 +34,17 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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#define CONFIG_SYS_BCSR3_PCIE 0x10
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struct board_bcsr {
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u8 board_id;
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u8 cpld_rev;
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u8 led_user;
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u8 board_status;
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u8 reset_ctrl;
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u8 flash_ctrl;
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u8 eth_ctrl;
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u8 usb_ctrl;
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u8 irq_ctrl;
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};
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#define BOARD_CANYONLANDS_PCIE 1
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#define BOARD_CANYONLANDS_PCIE 1
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#define BOARD_CANYONLANDS_SATA 2
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#define BOARD_CANYONLANDS_SATA 2
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@ -112,6 +122,9 @@ int board_early_init_f(void)
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{
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{
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#if !defined(CONFIG_ARCHES)
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#if !defined(CONFIG_ARCHES)
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u32 sdr0_cust0;
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u32 sdr0_cust0;
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struct board_bcsr *bcsr_data =
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(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
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#endif
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#endif
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/*
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/*
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@ -172,14 +185,10 @@ int board_early_init_f(void)
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#if !defined(CONFIG_ARCHES)
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#if !defined(CONFIG_ARCHES)
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/* Enable ethernet and take out of reset */
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/* Enable ethernet and take out of reset */
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out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
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out_8(&bcsr_data->eth_ctrl, 0) ;
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/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
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/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
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out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
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out_8(&bcsr_data->flash_ctrl, 0) ;
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/* Enable USB host & USB-OTG */
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out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
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mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
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mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
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/* Setup PLB4-AHB bridge based on the system address map */
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/* Setup PLB4-AHB bridge based on the system address map */
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@ -201,6 +210,41 @@ int board_early_init_f(void)
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return 0;
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return 0;
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}
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}
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#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
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int usb_board_init(void)
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{
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struct board_bcsr *bcsr_data =
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(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
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u8 val;
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/* Enable USB host & USB-OTG */
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val = in_8(&bcsr_data->usb_ctrl);
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val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
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out_8(&bcsr_data->usb_ctrl, val);
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return 0;
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}
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int usb_board_stop(void)
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{
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struct board_bcsr *bcsr_data =
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(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
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u8 val;
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/* Disable USB host & USB-OTG */
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val = in_8(&bcsr_data->usb_ctrl);
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val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
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out_8(&bcsr_data->usb_ctrl, val);
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return 0;
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}
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int usb_board_init_fail(void)
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{
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return usb_board_stop();
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}
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#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
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#if !defined(CONFIG_ARCHES)
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#if !defined(CONFIG_ARCHES)
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static void canyonlands_sata_init(int board_type)
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static void canyonlands_sata_init(int board_type)
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{
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{
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@ -244,11 +288,13 @@ int get_cpu_num(void)
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#if !defined(CONFIG_ARCHES)
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#if !defined(CONFIG_ARCHES)
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int checkboard(void)
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int checkboard(void)
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{
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{
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struct board_bcsr *bcsr_data =
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(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
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char *s = getenv("serial#");
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char *s = getenv("serial#");
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if (pvr_460ex()) {
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if (pvr_460ex()) {
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printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
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printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
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if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
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if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
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gd->board_type = BOARD_CANYONLANDS_PCIE;
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gd->board_type = BOARD_CANYONLANDS_PCIE;
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else
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else
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gd->board_type = BOARD_CANYONLANDS_SATA;
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gd->board_type = BOARD_CANYONLANDS_SATA;
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@ -268,7 +314,7 @@ int checkboard(void)
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break;
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break;
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}
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}
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printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
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printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
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if (s != NULL) {
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if (s != NULL) {
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puts(", serial# ");
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puts(", serial# ");
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@ -77,6 +77,13 @@
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#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
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#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
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#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
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#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
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/*
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* BCSR bits as defined in the Canyonlands board user manual.
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*/
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#define BCSR_USBCTRL_OTG_RST 0x32
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#define BCSR_USBCTRL_HOST_RST 0x01
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#define BCSR_SELECT_PCIE 0x10
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#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
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#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
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/* base address of inbound PCIe window */
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/* base address of inbound PCIe window */
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@ -417,6 +424,7 @@
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#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
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#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_SYS_USB_OHCI_BOARD_INIT
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#endif
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#endif
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/*
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/*
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