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ppc4xx/Canyonlands added USB board callbacks 

Functions added to support board callbacks for USB init. This
isolates USB manipulations such that it is only touched if USB is
used by U-Boot.

Signed-off-by: Dave Mitchell <dmitchell@appliedmicro.com>
Signed-off-by: Rupjyoti Sarmah <rsarmah@appliedmicro.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Rupjyoti Sarmah 2010-07-07 18:14:48 +05:30 committed by Stefan Roese
parent 1f82ff4777
commit 17a6844497
2 changed files with 63 additions and 9 deletions
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64
board/amcc/canyonlands/canyonlands.c
View File

@ -34,7 +34,17 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_BCSR3_PCIE 0x10
struct board_bcsr {
u8 board_id;
u8 cpld_rev;
u8 led_user;
u8 board_status;
u8 reset_ctrl;
u8 flash_ctrl;
u8 eth_ctrl;
u8 usb_ctrl;
u8 irq_ctrl;
};
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
@ -112,6 +122,9 @@ int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
#endif
/*
@ -172,14 +185,10 @@ int board_early_init_f(void)
#if !defined(CONFIG_ARCHES)
/* Enable ethernet and take out of reset */
out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
out_8(&bcsr_data->eth_ctrl, 0) ;
/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
/* Enable USB host & USB-OTG */
out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
out_8(&bcsr_data->flash_ctrl, 0) ;
mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
/* Setup PLB4-AHB bridge based on the system address map */
@ -201,6 +210,41 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
u8 val;
/* Enable USB host & USB-OTG */
val = in_8(&bcsr_data->usb_ctrl);
val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
out_8(&bcsr_data->usb_ctrl, val);
return 0;
}
int usb_board_stop(void)
{
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
u8 val;
/* Disable USB host & USB-OTG */
val = in_8(&bcsr_data->usb_ctrl);
val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
out_8(&bcsr_data->usb_ctrl, val);
return 0;
}
int usb_board_init_fail(void)
{
return usb_board_stop();
}
#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
@ -244,11 +288,13 @@ int get_cpu_num(void)
#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
char *s = getenv("serial#");
if (pvr_460ex()) {
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
gd->board_type = BOARD_CANYONLANDS_PCIE;
else
gd->board_type = BOARD_CANYONLANDS_SATA;
@ -268,7 +314,7 @@ int checkboard(void)
break;
}
printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
if (s != NULL) {
puts(", serial# ");

8
include/configs/canyonlands.h
View File

@ -77,6 +77,13 @@
#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
/*
* BCSR bits as defined in the Canyonlands board user manual.
*/
#define BCSR_USBCTRL_OTG_RST 0x32
#define BCSR_USBCTRL_HOST_RST 0x01
#define BCSR_SELECT_PCIE 0x10
#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
/* base address of inbound PCIe window */
@ -417,6 +424,7 @@
#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
#endif
/*