mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support
The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board. Signed-off-by Tony Li <tony.li@freescale.com>
This commit is contained in:
Tony Li
Kim Phillips
parent
35cc4e4823
commit
14778585d1
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@ -0,0 +1,101 @@
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* Tony Li <tony.li@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation;
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include "pq-mds-pib.h"
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int pib_init(void)
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{
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u8 val8;
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u8 orig_i2c_bus;
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/* Switch temporarily to I2C bus #2 */
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orig_i2c_bus = i2c_get_bus_num();
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i2c_set_bus_num(1);
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#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
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/* Assign PIB PMC slot to desired PCI bus */
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val8 = 0;
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i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x23, 0x2, 1, &val8, 1);
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i2c_write(0x23, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x26, 0x6, 1, &val8, 1);
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val8 = 0x34;
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i2c_write(0x26, 0x7, 1, &val8, 1);
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#if defined(CONFIG_MPC832XEMDS)
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val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
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#else
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val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
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#endif
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i2c_write(0x26, 0x2, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x26, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x27, 0x6, 1, &val8, 1);
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i2c_write(0x27, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x27, 0x2, 1, &val8, 1);
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val8 = 0xef;
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i2c_write(0x27, 0x3, 1, &val8, 1);
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eieio();
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#if defined(CONFIG_MPC832XEMDS)
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printf("PCI 32bit bus on PMC2 &PMC3\n");
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#else
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printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
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#endif
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#endif
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#if defined(CONFIG_PQ_MDS_PIB_ATM)
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#if defined(CONFIG_MPC8360EMDS)
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val8 = 0;
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i2c_write(0x20, 0x6, 1, &val8, 1);
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i2c_write(0x20, 0x7, 1, &val8, 1);
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val8 = 0xdf;
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i2c_write(0x20, 0x2, 1, &val8, 1);
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val8 = 0xf7;
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i2c_write(0x20, 0x3, 1, &val8, 1);
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eieio();
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printf("QOC3 ATM card on PMC0\n");
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#elif defined(CONFIG_MPC832XEMDS)
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val = 0;
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i2c_write(0x26, 0x7, 1, &val, 1);
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val = 0xf7;
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i2c_write(0x26, 0x3, 1, &val, 1);
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val = 0;
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i2c_write(0x21, 0x6, 1, &val, 1);
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i2c_write(0x21, 0x7, 1, &val, 1);
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val = 0xdf;
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i2c_write(0x21, 0x2, 1, &val, 1);
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val = 0xef;
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i2c_write(0x21, 0x3, 1, &val, 1);
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eieio();
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printf("QOC3 ATM card on PMC1\n");
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#endif
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#endif
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/* Reset to original I2C bus */
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i2c_set_bus_num(orig_i2c_bus);
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return 0;
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}
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@ -0,0 +1,9 @@
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation;
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*/
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extern int pib_init(void);
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pci.o
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COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -32,6 +32,9 @@
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#elif defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#if defined(CONFIG_PQ_MDS_PIB)
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#include "../freescale/common/pq-mds-pib.h"
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#endif
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* ETH3 */
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@ -88,6 +91,14 @@ int board_early_init_f(void)
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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pib_init();
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#endif
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return 0;
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}
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int fixed_sdram(void);
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long int initdram(int board_type)
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@ -131,7 +131,6 @@ void pci_init_board(void)
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volatile pcictrl83xx_t *pci_ctrl;
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volatile pciconf83xx_t *pci_conf;
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u8 val8, orig_i2c_bus;
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u16 reg16;
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u32 val32;
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u32 dev;
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@ -199,43 +198,6 @@ void pci_init_board(void)
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PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
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PIWAR_IWS_2G;
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/*
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* Assign PIB PMC slot to desired PCI bus
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*/
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/* Switch temporarily to I2C bus #2 */
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orig_i2c_bus = i2c_get_bus_num();
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i2c_set_bus_num(1);
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val8 = 0;
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i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x23, 0x2, 1, &val8, 1);
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i2c_write(0x23, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x26, 0x6, 1, &val8, 1);
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val8 = 0x34;
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i2c_write(0x26, 0x7, 1, &val8, 1);
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val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
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i2c_write(0x26, 0x2, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x26, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x27, 0x6, 1, &val8, 1);
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i2c_write(0x27, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x27, 0x2, 1, &val8, 1);
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val8 = 0xef;
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i2c_write(0x27, 0x3, 1, &val8, 1);
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asm("eieio");
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/* Reset to original I2C bus */
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i2c_set_bus_num(orig_i2c_bus);
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/*
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* Release PCI RST Output signal
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*/
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@ -292,8 +254,6 @@ void pci_init_board(void)
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pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
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printf("PCI 32bit bus on PMC2 & PMC3\n");
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/*
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* Hose scan.
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*/
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pci.o
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COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -30,6 +30,9 @@
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#elif defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#if defined(CONFIG_PQ_MDS_PIB)
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#include "../freescale/common/pq-mds-pib.h"
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#endif
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* GETH1 */
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@ -106,6 +109,14 @@ int board_early_init_f(void)
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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pib_init();
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#endif
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return 0;
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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@ -131,7 +131,6 @@ void pci_init_board(void)
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volatile pcictrl83xx_t *pci_ctrl;
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volatile pciconf83xx_t *pci_conf;
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u8 val8, orig_i2c_bus;
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u16 reg16;
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u32 val32;
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u32 dev;
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@ -199,43 +198,6 @@ void pci_init_board(void)
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PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
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PIWAR_IWS_2G;
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/*
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* Assign PIB PMC slot to desired PCI bus
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*/
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/* Switch temporarily to I2C bus #2 */
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orig_i2c_bus = i2c_get_bus_num();
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i2c_set_bus_num(1);
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val8 = 0;
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i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x23, 0x2, 1, &val8, 1);
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i2c_write(0x23, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x26, 0x6, 1, &val8, 1);
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val8 = 0x34;
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i2c_write(0x26, 0x7, 1, &val8, 1);
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val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */
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i2c_write(0x26, 0x2, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x26, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x27, 0x6, 1, &val8, 1);
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i2c_write(0x27, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x27, 0x2, 1, &val8, 1);
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val8 = 0xef;
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i2c_write(0x27, 0x3, 1, &val8, 1);
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asm("eieio");
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/* Reset to original I2C bus */
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i2c_set_bus_num(orig_i2c_bus);
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/*
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* Release PCI RST Output signal
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*/
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@ -292,8 +254,6 @@ void pci_init_board(void)
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pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
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printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
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/*
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* Hose scan.
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*/
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@ -30,6 +30,8 @@
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#define CONFIG_MPC83XX 1 /* MPC83xx family */
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#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
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#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
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#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
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#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
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/*
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* System Clock Setup
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@ -87,6 +89,7 @@
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#define CFG_SICRL 0x00000000
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CONFIG_BOARD_EARLY_INIT_R
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/*
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* IMMR new address
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@ -32,6 +32,8 @@
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#define CONFIG_MPC83XX 1 /* MPC83XX family */
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#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
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#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
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#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
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#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
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/*
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* System Clock Setup
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@ -88,6 +90,7 @@
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#define CFG_SICRL 0x40000000
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CONFIG_BOARD_EARLY_INIT_R
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/*
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* IMMR new address
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@ -309,13 +312,13 @@
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/*
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* CS4 on Local Bus, to PIB
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*/
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#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
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#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
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#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
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/*
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* CS5 on Local Bus, to PIB
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*/
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#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
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#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
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#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
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/*
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