Initial revision
This commit is contained in:
wdenk
parent
82e299bf89
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121cb96d51
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/*
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* This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
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* copyright notice:
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*
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* General Purpose functions for the global management of the
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* 8260 Communication Processor Module.
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* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
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* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
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* 2.3.99 Updates
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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*/
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#include <common.h>
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#include <asm/cpm_8260.h>
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/*
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* because we have stack and init data in dual port ram
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* we must reduce the size
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*/
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#undef CPM_DATAONLY_SIZE
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#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
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void
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m8260_cpm_reset(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile ulong count;
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/* Reclaim the DP memory for our use.
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*/
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gd->dp_alloc_base = CPM_DATAONLY_BASE;
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gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
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/*
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* Reset CPM
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*/
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immr->im_cpm.cp_cpcr = CPM_CR_RST;
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count = 0;
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do { /* Spin until command processed */
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__asm__ __volatile__ ("eieio");
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} while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000);
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#ifdef CONFIG_HARD_I2C
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*((unsigned short*)(&immr->im_dprambase[PROFF_I2C_BASE])) = 0;
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#endif
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}
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/* Allocate some memory from the dual ported ram.
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* To help protocols with object alignment restrictions, we do that
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* if they ask.
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*/
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uint
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m8260_cpm_dpalloc(uint size, uint align)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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uint retloc;
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uint align_mask, off;
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uint savebase;
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align_mask = align - 1;
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savebase = gd->dp_alloc_base;
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if ((off = (gd->dp_alloc_base & align_mask)) != 0)
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gd->dp_alloc_base += (align - off);
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if ((off = size & align_mask) != 0)
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size += align - off;
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if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
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gd->dp_alloc_base = savebase;
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panic("m8260_cpm_dpalloc: ran out of dual port ram!");
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}
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retloc = gd->dp_alloc_base;
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gd->dp_alloc_base += size;
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memset((void *)&immr->im_dprambase[retloc], 0, size);
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return(retloc);
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}
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/* We also own one page of host buffer space for the allocation of
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* UART "fifos" and the like.
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*/
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uint
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m8260_cpm_hostalloc(uint size, uint align)
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{
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/* the host might not even have RAM yet - just use dual port RAM */
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return (m8260_cpm_dpalloc(size, align));
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}
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/* Set a baud rate generator. This needs lots of work. There are
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* eight BRGs, which can be connected to the CPM channels or output
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* as clocks. The BRGs are in two different block of internal
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* memory mapped space.
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* The baud rate clock is the system clock divided by something.
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* It was set up long ago during the initial boot phase and is
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* is given to us.
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* Baud rate clocks are zero-based in the driver code (as that maps
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* to port numbers). Documentation uses 1-based numbering.
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*/
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#define BRG_INT_CLK gd->brg_clk
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#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
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/* This function is used by UARTS, or anything else that uses a 16x
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* oversampled clock.
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*/
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void
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m8260_cpm_setbrg(uint brg, uint rate)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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if (brg < 4) {
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bp = (uint *)&immr->im_brgc1;
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}
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else {
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bp = (uint *)&immr->im_brgc5;
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brg -= 4;
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}
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bp += brg;
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*bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
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}
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/* This function is used to set high speed synchronous baud rate
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* clocks.
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*/
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void
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m8260_cpm_fastbrg(uint brg, uint rate, int div16)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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if (brg < 4) {
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bp = (uint *)&immr->im_brgc1;
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}
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else {
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bp = (uint *)&immr->im_brgc5;
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brg -= 4;
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}
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bp += brg;
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*bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
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if (div16)
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*bp |= CPM_BRG_DIV16;
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}
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/* This function is used to set baud rate generators using an external
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* clock source and 16x oversampling.
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*/
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void
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m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile uint *bp;
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if (brg < 4) {
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bp = (uint *)&immr->im_brgc1;
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}
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else {
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bp = (uint *)&immr->im_brgc5;
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brg -= 4;
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}
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bp += brg;
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*bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
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if (pinsel == 0)
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*bp |= CPM_BRG_EXTC_CLK3_9;
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else
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*bp |= CPM_BRG_EXTC_CLK5_15;
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}
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#ifdef CONFIG_POST
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void post_word_store (ulong a)
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{
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volatile ulong *save_addr =
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(volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
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*save_addr = a;
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}
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ulong post_word_load (void)
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{
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volatile ulong *save_addr =
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(volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
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return *save_addr;
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}
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#endif /* CONFIG_POST */
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@ -0,0 +1,740 @@
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/*
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* MPC8260 Communication Processor Module.
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* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
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*
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* This file contains structures and information for the communication
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* processor channels found in the dual port RAM or parameter RAM.
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* All CPM control and status is available through the MPC8260 internal
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* memory map. See immap.h for details.
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*/
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#ifndef __CPM_82XX__
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#define __CPM_82XX__
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#include <asm/immap_8260.h>
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/* CPM Command register.
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*/
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#define CPM_CR_RST ((uint)0x80000000)
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#define CPM_CR_PAGE ((uint)0x7c000000)
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#define CPM_CR_SBLOCK ((uint)0x03e00000)
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#define CPM_CR_FLG ((uint)0x00010000)
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#define CPM_CR_MCN ((uint)0x00003fc0)
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#define CPM_CR_OPCODE ((uint)0x0000000f)
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/* Device sub-block and page codes.
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*/
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#define CPM_CR_SCC1_SBLOCK (0x04)
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#define CPM_CR_SCC2_SBLOCK (0x05)
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#define CPM_CR_SCC3_SBLOCK (0x06)
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#define CPM_CR_SCC4_SBLOCK (0x07)
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#define CPM_CR_SMC1_SBLOCK (0x08)
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#define CPM_CR_SMC2_SBLOCK (0x09)
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#define CPM_CR_SPI_SBLOCK (0x0a)
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#define CPM_CR_I2C_SBLOCK (0x0b)
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#define CPM_CR_TIMER_SBLOCK (0x0f)
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#define CPM_CR_RAND_SBLOCK (0x0e)
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#define CPM_CR_FCC1_SBLOCK (0x10)
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#define CPM_CR_FCC2_SBLOCK (0x11)
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#define CPM_CR_FCC3_SBLOCK (0x12)
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#define CPM_CR_IDMA1_SBLOCK (0x14)
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#define CPM_CR_IDMA2_SBLOCK (0x15)
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#define CPM_CR_IDMA3_SBLOCK (0x16)
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#define CPM_CR_IDMA4_SBLOCK (0x17)
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#define CPM_CR_MCC1_SBLOCK (0x1c)
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#define CPM_CR_SCC1_PAGE (0x00)
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#define CPM_CR_SCC2_PAGE (0x01)
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#define CPM_CR_SCC3_PAGE (0x02)
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#define CPM_CR_SCC4_PAGE (0x03)
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#define CPM_CR_SMC1_PAGE (0x07)
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#define CPM_CR_SMC2_PAGE (0x08)
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#define CPM_CR_SPI_PAGE (0x09)
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#define CPM_CR_I2C_PAGE (0x0a)
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#define CPM_CR_TIMER_PAGE (0x0a)
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#define CPM_CR_RAND_PAGE (0x0a)
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#define CPM_CR_FCC1_PAGE (0x04)
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#define CPM_CR_FCC2_PAGE (0x05)
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#define CPM_CR_FCC3_PAGE (0x06)
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#define CPM_CR_IDMA1_PAGE (0x07)
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#define CPM_CR_IDMA2_PAGE (0x08)
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#define CPM_CR_IDMA3_PAGE (0x09)
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#define CPM_CR_IDMA4_PAGE (0x0a)
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#define CPM_CR_MCC1_PAGE (0x07)
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#define CPM_CR_MCC2_PAGE (0x08)
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/* Some opcodes (there are more...later)
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*/
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#define CPM_CR_INIT_TRX ((ushort)0x0000)
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#define CPM_CR_INIT_RX ((ushort)0x0001)
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#define CPM_CR_INIT_TX ((ushort)0x0002)
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#define CPM_CR_HUNT_MODE ((ushort)0x0003)
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#define CPM_CR_STOP_TX ((ushort)0x0004)
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#define CPM_CR_RESTART_TX ((ushort)0x0006)
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#define CPM_CR_SET_GADDR ((ushort)0x0008)
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#define mk_cr_cmd(PG, SBC, MCN, OP) \
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((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
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/* Dual Port RAM addresses. The first 16K is available for almost
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* any CPM use, so we put the BDs there. The first 128 bytes are
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* used for SMC1 and SMC2 parameter RAM, so we start allocating
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* BDs above that. All of this must change when we start
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* downloading RAM microcode.
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*/
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#define CPM_DATAONLY_BASE ((uint)128)
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#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
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#define CPM_DP_NOSPACE ((uint)0x7fffffff)
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#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
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/* The number of pages of host memory we allocate for CPM. This is
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* done early in kernel initialization to get physically contiguous
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* pages.
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*/
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#define NUM_CPM_HOST_PAGES 2
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/* Export the base address of the communication processor registers
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* and dual port ram.
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*/
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extern cpm8260_t *cpmp; /* Pointer to comm processor */
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uint m8260_cpm_dpalloc(uint size, uint align);
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uint m8260_cpm_hostalloc(uint size, uint align);
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void m8260_cpm_setbrg(uint brg, uint rate);
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void m8260_cpm_fastbrg(uint brg, uint rate, int div16);
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void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
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/* Buffer descriptors used by many of the CPM protocols.
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*/
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typedef struct cpm_buf_desc {
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ushort cbd_sc; /* Status and Control */
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ushort cbd_datlen; /* Data length in buffer */
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uint cbd_bufaddr; /* Buffer address in host memory */
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} cbd_t;
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#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
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#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
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#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
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#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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#define BD_SC_FR ((ushort)0x0010) /* Framing error */
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#define BD_SC_PR ((ushort)0x0008) /* Parity error */
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#define BD_SC_OV ((ushort)0x0002) /* Overrun */
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#define BD_SC_CD ((ushort)0x0001) /* ?? */
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/* Function code bits, usually generic to devices.
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*/
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#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
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#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
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#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
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#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
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#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
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/* Parameter RAM offsets from the base.
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*/
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#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
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#define PROFF_SCC1 ((uint)0x8000)
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#define PROFF_SCC2 ((uint)0x8100)
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#define PROFF_SCC3 ((uint)0x8200)
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#define PROFF_SCC4 ((uint)0x8300)
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#define PROFF_FCC1 ((uint)0x8400)
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#define PROFF_FCC2 ((uint)0x8500)
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#define PROFF_FCC3 ((uint)0x8600)
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#define PROFF_MCC1 ((uint)0x8700)
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#define PROFF_SMC1_BASE ((uint)0x87fc)
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#define PROFF_IDMA1_BASE ((uint)0x87fe)
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#define PROFF_MCC2 ((uint)0x8800)
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#define PROFF_SMC2_BASE ((uint)0x88fc)
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#define PROFF_IDMA2_BASE ((uint)0x88fe)
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#define PROFF_SPI_BASE ((uint)0x89fc)
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#define PROFF_IDMA3_BASE ((uint)0x89fe)
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#define PROFF_TIMERS ((uint)0x8ae0)
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#define PROFF_REVNUM ((uint)0x8af0)
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#define PROFF_RAND ((uint)0x8af8)
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#define PROFF_I2C_BASE ((uint)0x8afc)
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#define PROFF_IDMA4_BASE ((uint)0x8afe)
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/* The SMCs are relocated to any of the first eight DPRAM pages.
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* We will fix these at the first locations of DPRAM, until we
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* get some microcode patches :-).
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* The parameter ram space for the SMCs is fifty-some bytes, and
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* they are required to start on a 64 byte boundary.
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*/
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#define PROFF_SMC1 (0)
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#define PROFF_SMC2 (64)
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/* Define enough so I can at least use the serial port as a UART.
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*/
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typedef struct smc_uart {
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ushort smc_rbase; /* Rx Buffer descriptor base address */
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ushort smc_tbase; /* Tx Buffer descriptor base address */
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u_char smc_rfcr; /* Rx function code */
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u_char smc_tfcr; /* Tx function code */
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ushort smc_mrblr; /* Max receive buffer length */
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uint smc_rstate; /* Internal */
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uint smc_idp; /* Internal */
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ushort smc_rbptr; /* Internal */
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ushort smc_ibc; /* Internal */
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uint smc_rxtmp; /* Internal */
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uint smc_tstate; /* Internal */
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uint smc_tdp; /* Internal */
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ushort smc_tbptr; /* Internal */
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ushort smc_tbc; /* Internal */
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uint smc_txtmp; /* Internal */
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ushort smc_maxidl; /* Maximum idle characters */
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ushort smc_tmpidl; /* Temporary idle counter */
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ushort smc_brklen; /* Last received break length */
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ushort smc_brkec; /* rcv'd break condition counter */
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ushort smc_brkcr; /* xmt break count register */
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ushort smc_rmask; /* Temporary bit mask */
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uint smc_stmp; /* SDMA Temp */
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} smc_uart_t;
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/* SMC uart mode register (Internal memory map).
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*/
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#define SMCMR_REN ((ushort)0x0001)
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#define SMCMR_TEN ((ushort)0x0002)
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#define SMCMR_DM ((ushort)0x000c)
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#define SMCMR_SM_GCI ((ushort)0x0000)
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#define SMCMR_SM_UART ((ushort)0x0020)
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#define SMCMR_SM_TRANS ((ushort)0x0030)
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#define SMCMR_SM_MASK ((ushort)0x0030)
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#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
|
||||
#define SMCMR_REVD SMCMR_PM_EVEN
|
||||
#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
|
||||
#define SMCMR_BS SMCMR_PEN
|
||||
#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
|
||||
#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
|
||||
#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
|
||||
|
||||
/* SMC Event and Mask register.
|
||||
*/
|
||||
#define SMCM_TXE ((unsigned char)0x10)
|
||||
#define SMCM_BSY ((unsigned char)0x04)
|
||||
#define SMCM_TX ((unsigned char)0x02)
|
||||
#define SMCM_RX ((unsigned char)0x01)
|
||||
|
||||
/* Baud rate generators.
|
||||
*/
|
||||
#define CPM_BRG_RST ((uint)0x00020000)
|
||||
#define CPM_BRG_EN ((uint)0x00010000)
|
||||
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
|
||||
#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
|
||||
#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
|
||||
#define CPM_BRG_ATB ((uint)0x00002000)
|
||||
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
|
||||
#define CPM_BRG_DIV16 ((uint)0x00000001)
|
||||
|
||||
/* SCCs.
|
||||
*/
|
||||
#define SCC_GSMRH_IRP ((uint)0x00040000)
|
||||
#define SCC_GSMRH_GDE ((uint)0x00010000)
|
||||
#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
|
||||
#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
|
||||
#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
|
||||
#define SCC_GSMRH_REVD ((uint)0x00002000)
|
||||
#define SCC_GSMRH_TRX ((uint)0x00001000)
|
||||
#define SCC_GSMRH_TTX ((uint)0x00000800)
|
||||
#define SCC_GSMRH_CDP ((uint)0x00000400)
|
||||
#define SCC_GSMRH_CTSP ((uint)0x00000200)
|
||||
#define SCC_GSMRH_CDS ((uint)0x00000100)
|
||||
#define SCC_GSMRH_CTSS ((uint)0x00000080)
|
||||
#define SCC_GSMRH_TFL ((uint)0x00000040)
|
||||
#define SCC_GSMRH_RFW ((uint)0x00000020)
|
||||
#define SCC_GSMRH_TXSY ((uint)0x00000010)
|
||||
#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
|
||||
#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
|
||||
#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
|
||||
#define SCC_GSMRH_RTSM ((uint)0x00000002)
|
||||
#define SCC_GSMRH_RSYN ((uint)0x00000001)
|
||||
|
||||
#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
|
||||
#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
|
||||
#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
|
||||
#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
|
||||
#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
|
||||
#define SCC_GSMRL_TCI ((uint)0x10000000)
|
||||
#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
|
||||
#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
|
||||
#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
|
||||
#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
|
||||
#define SCC_GSMRL_RINV ((uint)0x02000000)
|
||||
#define SCC_GSMRL_TINV ((uint)0x01000000)
|
||||
#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
|
||||
#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
|
||||
#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
|
||||
#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
|
||||
#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
|
||||
#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
|
||||
#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
|
||||
#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
|
||||
#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
|
||||
#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
|
||||
#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
|
||||
#define SCC_GSMRL_TEND ((uint)0x00040000)
|
||||
#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
|
||||
#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
|
||||
#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
|
||||
#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
|
||||
#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
|
||||
#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
|
||||
#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
|
||||
#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
|
||||
#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
|
||||
#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
|
||||
#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
|
||||
#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
|
||||
#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
|
||||
#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
|
||||
#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
|
||||
#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
|
||||
#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
|
||||
#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
|
||||
#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
|
||||
#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
|
||||
#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
|
||||
#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
|
||||
#define SCC_GSMRL_ENR ((uint)0x00000020)
|
||||
#define SCC_GSMRL_ENT ((uint)0x00000010)
|
||||
#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
|
||||
#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
|
||||
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
|
||||
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
|
||||
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
|
||||
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
|
||||
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
|
||||
#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
|
||||
#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
|
||||
#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
|
||||
|
||||
#define SCC_TODR_TOD ((ushort)0x8000)
|
||||
|
||||
/* SCC Event and Mask register.
|
||||
*/
|
||||
#define SCCM_TXE ((unsigned char)0x10)
|
||||
#define SCCM_BSY ((unsigned char)0x04)
|
||||
#define SCCM_TX ((unsigned char)0x02)
|
||||
#define SCCM_RX ((unsigned char)0x01)
|
||||
|
||||
typedef struct scc_param {
|
||||
ushort scc_rbase; /* Rx Buffer descriptor base address */
|
||||
ushort scc_tbase; /* Tx Buffer descriptor base address */
|
||||
u_char scc_rfcr; /* Rx function code */
|
||||
u_char scc_tfcr; /* Tx function code */
|
||||
ushort scc_mrblr; /* Max receive buffer length */
|
||||
uint scc_rstate; /* Internal */
|
||||
uint scc_idp; /* Internal */
|
||||
ushort scc_rbptr; /* Internal */
|
||||
ushort scc_ibc; /* Internal */
|
||||
uint scc_rxtmp; /* Internal */
|
||||
uint scc_tstate; /* Internal */
|
||||
uint scc_tdp; /* Internal */
|
||||
ushort scc_tbptr; /* Internal */
|
||||
ushort scc_tbc; /* Internal */
|
||||
uint scc_txtmp; /* Internal */
|
||||
uint scc_rcrc; /* Internal */
|
||||
uint scc_tcrc; /* Internal */
|
||||
} sccp_t;
|
||||
|
||||
/* CPM Ethernet through SCC1.
|
||||
*/
|
||||
typedef struct scc_enet {
|
||||
sccp_t sen_genscc;
|
||||
uint sen_cpres; /* Preset CRC */
|
||||
uint sen_cmask; /* Constant mask for CRC */
|
||||
uint sen_crcec; /* CRC Error counter */
|
||||
uint sen_alec; /* alignment error counter */
|
||||
uint sen_disfc; /* discard frame counter */
|
||||
ushort sen_pads; /* Tx short frame pad character */
|
||||
ushort sen_retlim; /* Retry limit threshold */
|
||||
ushort sen_retcnt; /* Retry limit counter */
|
||||
ushort sen_maxflr; /* maximum frame length register */
|
||||
ushort sen_minflr; /* minimum frame length register */
|
||||
ushort sen_maxd1; /* maximum DMA1 length */
|
||||
ushort sen_maxd2; /* maximum DMA2 length */
|
||||
ushort sen_maxd; /* Rx max DMA */
|
||||
ushort sen_dmacnt; /* Rx DMA counter */
|
||||
ushort sen_maxb; /* Max BD byte count */
|
||||
ushort sen_gaddr1; /* Group address filter */
|
||||
ushort sen_gaddr2;
|
||||
ushort sen_gaddr3;
|
||||
ushort sen_gaddr4;
|
||||
uint sen_tbuf0data0; /* Save area 0 - current frame */
|
||||
uint sen_tbuf0data1; /* Save area 1 - current frame */
|
||||
uint sen_tbuf0rba; /* Internal */
|
||||
uint sen_tbuf0crc; /* Internal */
|
||||
ushort sen_tbuf0bcnt; /* Internal */
|
||||
ushort sen_paddrh; /* physical address (MSB) */
|
||||
ushort sen_paddrm;
|
||||
ushort sen_paddrl; /* physical address (LSB) */
|
||||
ushort sen_pper; /* persistence */
|
||||
ushort sen_rfbdptr; /* Rx first BD pointer */
|
||||
ushort sen_tfbdptr; /* Tx first BD pointer */
|
||||
ushort sen_tlbdptr; /* Tx last BD pointer */
|
||||
uint sen_tbuf1data0; /* Save area 0 - current frame */
|
||||
uint sen_tbuf1data1; /* Save area 1 - current frame */
|
||||
uint sen_tbuf1rba; /* Internal */
|
||||
uint sen_tbuf1crc; /* Internal */
|
||||
ushort sen_tbuf1bcnt; /* Internal */
|
||||
ushort sen_txlen; /* Tx Frame length counter */
|
||||
ushort sen_iaddr1; /* Individual address filter */
|
||||
ushort sen_iaddr2;
|
||||
ushort sen_iaddr3;
|
||||
ushort sen_iaddr4;
|
||||
ushort sen_boffcnt; /* Backoff counter */
|
||||
|
||||
/* NOTE: Some versions of the manual have the following items
|
||||
* incorrectly documented. Below is the proper order.
|
||||
*/
|
||||
ushort sen_taddrh; /* temp address (MSB) */
|
||||
ushort sen_taddrm;
|
||||
ushort sen_taddrl; /* temp address (LSB) */
|
||||
} scc_enet_t;
|
||||
|
||||
|
||||
/* SCC Event register as used by Ethernet.
|
||||
*/
|
||||
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
|
||||
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
|
||||
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
|
||||
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
|
||||
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
|
||||
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
|
||||
|
||||
/* SCC Mode Register (PSMR) as used by Ethernet.
|
||||
*/
|
||||
#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
|
||||
#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
|
||||
#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
|
||||
#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
|
||||
#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
|
||||
#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
|
||||
#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
|
||||
#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
|
||||
#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
|
||||
#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
|
||||
#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
|
||||
#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
|
||||
#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
|
||||
|
||||
/* Buffer descriptor control/status used by Ethernet receive.
|
||||
* Common to SCC and FCC.
|
||||
*/
|
||||
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
|
||||
#define BD_ENET_RX_WRAP ((ushort)0x2000)
|
||||
#define BD_ENET_RX_INTR ((ushort)0x1000)
|
||||
#define BD_ENET_RX_LAST ((ushort)0x0800)
|
||||
#define BD_ENET_RX_FIRST ((ushort)0x0400)
|
||||
#define BD_ENET_RX_MISS ((ushort)0x0100)
|
||||
#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
|
||||
#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
|
||||
#define BD_ENET_RX_LG ((ushort)0x0020)
|
||||
#define BD_ENET_RX_NO ((ushort)0x0010)
|
||||
#define BD_ENET_RX_SH ((ushort)0x0008)
|
||||
#define BD_ENET_RX_CR ((ushort)0x0004)
|
||||
#define BD_ENET_RX_OV ((ushort)0x0002)
|
||||
#define BD_ENET_RX_CL ((ushort)0x0001)
|
||||
#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
|
||||
|
||||
/* Buffer descriptor control/status used by Ethernet transmit.
|
||||
* Common to SCC and FCC.
|
||||
*/
|
||||
#define BD_ENET_TX_READY ((ushort)0x8000)
|
||||
#define BD_ENET_TX_PAD ((ushort)0x4000)
|
||||
#define BD_ENET_TX_WRAP ((ushort)0x2000)
|
||||
#define BD_ENET_TX_INTR ((ushort)0x1000)
|
||||
#define BD_ENET_TX_LAST ((ushort)0x0800)
|
||||
#define BD_ENET_TX_TC ((ushort)0x0400)
|
||||
#define BD_ENET_TX_DEF ((ushort)0x0200)
|
||||
#define BD_ENET_TX_HB ((ushort)0x0100)
|
||||
#define BD_ENET_TX_LC ((ushort)0x0080)
|
||||
#define BD_ENET_TX_RL ((ushort)0x0040)
|
||||
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
|
||||
#define BD_ENET_TX_UN ((ushort)0x0002)
|
||||
#define BD_ENET_TX_CSL ((ushort)0x0001)
|
||||
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
|
||||
|
||||
/* SCC as UART
|
||||
*/
|
||||
typedef struct scc_uart {
|
||||
sccp_t scc_genscc;
|
||||
uint scc_res1; /* Reserved */
|
||||
uint scc_res2; /* Reserved */
|
||||
ushort scc_maxidl; /* Maximum idle chars */
|
||||
ushort scc_idlc; /* temp idle counter */
|
||||
ushort scc_brkcr; /* Break count register */
|
||||
ushort scc_parec; /* receive parity error counter */
|
||||
ushort scc_frmec; /* receive framing error counter */
|
||||
ushort scc_nosec; /* receive noise counter */
|
||||
ushort scc_brkec; /* receive break condition counter */
|
||||
ushort scc_brkln; /* last received break length */
|
||||
ushort scc_uaddr1; /* UART address character 1 */
|
||||
ushort scc_uaddr2; /* UART address character 2 */
|
||||
ushort scc_rtemp; /* Temp storage */
|
||||
ushort scc_toseq; /* Transmit out of sequence char */
|
||||
ushort scc_char1; /* control character 1 */
|
||||
ushort scc_char2; /* control character 2 */
|
||||
ushort scc_char3; /* control character 3 */
|
||||
ushort scc_char4; /* control character 4 */
|
||||
ushort scc_char5; /* control character 5 */
|
||||
ushort scc_char6; /* control character 6 */
|
||||
ushort scc_char7; /* control character 7 */
|
||||
ushort scc_char8; /* control character 8 */
|
||||
ushort scc_rccm; /* receive control character mask */
|
||||
ushort scc_rccr; /* receive control character register */
|
||||
ushort scc_rlbc; /* receive last break character */
|
||||
} scc_uart_t;
|
||||
|
||||
/* SCC Event and Mask registers when it is used as a UART.
|
||||
*/
|
||||
#define UART_SCCM_GLR ((ushort)0x1000)
|
||||
#define UART_SCCM_GLT ((ushort)0x0800)
|
||||
#define UART_SCCM_AB ((ushort)0x0200)
|
||||
#define UART_SCCM_IDL ((ushort)0x0100)
|
||||
#define UART_SCCM_GRA ((ushort)0x0080)
|
||||
#define UART_SCCM_BRKE ((ushort)0x0040)
|
||||
#define UART_SCCM_BRKS ((ushort)0x0020)
|
||||
#define UART_SCCM_CCR ((ushort)0x0008)
|
||||
#define UART_SCCM_BSY ((ushort)0x0004)
|
||||
#define UART_SCCM_TX ((ushort)0x0002)
|
||||
#define UART_SCCM_RX ((ushort)0x0001)
|
||||
|
||||
/* The SCC PSMR when used as a UART.
|
||||
*/
|
||||
#define SCU_PSMR_FLC ((ushort)0x8000)
|
||||
#define SCU_PSMR_SL ((ushort)0x4000)
|
||||
#define SCU_PSMR_CL ((ushort)0x3000)
|
||||
#define SCU_PSMR_UM ((ushort)0x0c00)
|
||||
#define SCU_PSMR_FRZ ((ushort)0x0200)
|
||||
#define SCU_PSMR_RZS ((ushort)0x0100)
|
||||
#define SCU_PSMR_SYN ((ushort)0x0080)
|
||||
#define SCU_PSMR_DRT ((ushort)0x0040)
|
||||
#define SCU_PSMR_PEN ((ushort)0x0010)
|
||||
#define SCU_PSMR_RPM ((ushort)0x000c)
|
||||
#define SCU_PSMR_REVP ((ushort)0x0008)
|
||||
#define SCU_PSMR_TPM ((ushort)0x0003)
|
||||
#define SCU_PSMR_TEVP ((ushort)0x0003)
|
||||
|
||||
/* CPM Transparent mode SCC.
|
||||
*/
|
||||
typedef struct scc_trans {
|
||||
sccp_t st_genscc;
|
||||
uint st_cpres; /* Preset CRC */
|
||||
uint st_cmask; /* Constant mask for CRC */
|
||||
} scc_trans_t;
|
||||
|
||||
#define BD_SCC_TX_LAST ((ushort)0x0800)
|
||||
|
||||
/* How about some FCCs.....
|
||||
*/
|
||||
#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
|
||||
#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
|
||||
#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
|
||||
#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
|
||||
#define FCC_GFMR_TCI ((uint)0x20000000)
|
||||
#define FCC_GFMR_TRX ((uint)0x10000000)
|
||||
#define FCC_GFMR_TTX ((uint)0x08000000)
|
||||
#define FCC_GFMR_TTX ((uint)0x08000000)
|
||||
#define FCC_GFMR_CDP ((uint)0x04000000)
|
||||
#define FCC_GFMR_CTSP ((uint)0x02000000)
|
||||
#define FCC_GFMR_CDS ((uint)0x01000000)
|
||||
#define FCC_GFMR_CTSS ((uint)0x00800000)
|
||||
#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
|
||||
#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
|
||||
#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
|
||||
#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
|
||||
#define FCC_GFMR_RTSM ((uint)0x00002000)
|
||||
#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
|
||||
#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
|
||||
#define FCC_GFMR_REVD ((uint)0x00000400)
|
||||
#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
|
||||
#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
|
||||
#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
|
||||
#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
|
||||
#define FCC_GFMR_ENR ((uint)0x00000020)
|
||||
#define FCC_GFMR_ENT ((uint)0x00000010)
|
||||
#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
|
||||
#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
|
||||
#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
|
||||
|
||||
/* Generic FCC parameter ram.
|
||||
*/
|
||||
typedef struct fcc_param {
|
||||
ushort fcc_riptr; /* Rx Internal temp pointer */
|
||||
ushort fcc_tiptr; /* Tx Internal temp pointer */
|
||||
ushort fcc_res1;
|
||||
ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
|
||||
uint fcc_rstate; /* Upper byte is Func code, must be set */
|
||||
uint fcc_rbase; /* Receive BD base */
|
||||
ushort fcc_rbdstat; /* RxBD status */
|
||||
ushort fcc_rbdlen; /* RxBD down counter */
|
||||
uint fcc_rdptr; /* RxBD internal data pointer */
|
||||
uint fcc_tstate; /* Upper byte is Func code, must be set */
|
||||
uint fcc_tbase; /* Transmit BD base */
|
||||
ushort fcc_tbdstat; /* TxBD status */
|
||||
ushort fcc_tbdlen; /* TxBD down counter */
|
||||
uint fcc_tdptr; /* TxBD internal data pointer */
|
||||
uint fcc_rbptr; /* Rx BD Internal buf pointer */
|
||||
uint fcc_tbptr; /* Tx BD Internal buf pointer */
|
||||
uint fcc_rcrc; /* Rx temp CRC */
|
||||
uint fcc_res2;
|
||||
uint fcc_tcrc; /* Tx temp CRC */
|
||||
} fccp_t;
|
||||
|
||||
|
||||
/* Ethernet controller through FCC.
|
||||
*/
|
||||
typedef struct fcc_enet {
|
||||
fccp_t fen_genfcc;
|
||||
uint fen_statbuf; /* Internal status buffer */
|
||||
uint fen_camptr; /* CAM address */
|
||||
uint fen_cmask; /* Constant mask for CRC */
|
||||
uint fen_cpres; /* Preset CRC */
|
||||
uint fen_crcec; /* CRC Error counter */
|
||||
uint fen_alec; /* alignment error counter */
|
||||
uint fen_disfc; /* discard frame counter */
|
||||
ushort fen_retlim; /* Retry limit */
|
||||
ushort fen_retcnt; /* Retry counter */
|
||||
ushort fen_pper; /* Persistence */
|
||||
ushort fen_boffcnt; /* backoff counter */
|
||||
uint fen_gaddrh; /* Group address filter, high 32-bits */
|
||||
uint fen_gaddrl; /* Group address filter, low 32-bits */
|
||||
ushort fen_tfcstat; /* out of sequence TxBD */
|
||||
ushort fen_tfclen;
|
||||
uint fen_tfcptr;
|
||||
ushort fen_mflr; /* Maximum frame length (1518) */
|
||||
ushort fen_paddrh; /* MAC address */
|
||||
ushort fen_paddrm;
|
||||
ushort fen_paddrl;
|
||||
ushort fen_ibdcount; /* Internal BD counter */
|
||||
ushort fen_idbstart; /* Internal BD start pointer */
|
||||
ushort fen_ibdend; /* Internal BD end pointer */
|
||||
ushort fen_txlen; /* Internal Tx frame length counter */
|
||||
uint fen_ibdbase[8]; /* Internal use */
|
||||
uint fen_iaddrh; /* Individual address filter */
|
||||
uint fen_iaddrl;
|
||||
ushort fen_minflr; /* Minimum frame length (64) */
|
||||
ushort fen_taddrh; /* Filter transfer MAC address */
|
||||
ushort fen_taddrm;
|
||||
ushort fen_taddrl;
|
||||
ushort fen_padptr; /* Pointer to pad byte buffer */
|
||||
ushort fen_cftype; /* control frame type */
|
||||
ushort fen_cfrange; /* control frame range */
|
||||
ushort fen_maxb; /* maximum BD count */
|
||||
ushort fen_maxd1; /* Max DMA1 length (1520) */
|
||||
ushort fen_maxd2; /* Max DMA2 length (1520) */
|
||||
ushort fen_maxd; /* internal max DMA count */
|
||||
ushort fen_dmacnt; /* internal DMA counter */
|
||||
uint fen_octc; /* Total octect counter */
|
||||
uint fen_colc; /* Total collision counter */
|
||||
uint fen_broc; /* Total broadcast packet counter */
|
||||
uint fen_mulc; /* Total multicast packet count */
|
||||
uint fen_uspc; /* Total packets < 64 bytes */
|
||||
uint fen_frgc; /* Total packets < 64 bytes with errors */
|
||||
uint fen_ospc; /* Total packets > 1518 */
|
||||
uint fen_jbrc; /* Total packets > 1518 with errors */
|
||||
uint fen_p64c; /* Total packets == 64 bytes */
|
||||
uint fen_p65c; /* Total packets 64 < bytes <= 127 */
|
||||
uint fen_p128c; /* Total packets 127 < bytes <= 255 */
|
||||
uint fen_p256c; /* Total packets 256 < bytes <= 511 */
|
||||
uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
|
||||
uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
|
||||
uint fen_cambuf; /* Internal CAM buffer poiner */
|
||||
ushort fen_rfthr; /* Received frames threshold */
|
||||
ushort fen_rfcnt; /* Received frames count */
|
||||
} fcc_enet_t;
|
||||
|
||||
/* FCC Event/Mask register as used by Ethernet.
|
||||
*/
|
||||
#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
|
||||
#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
|
||||
#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
|
||||
#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
|
||||
#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
|
||||
#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
|
||||
#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
|
||||
#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
|
||||
|
||||
/* FCC Mode Register (FPSMR) as used by Ethernet.
|
||||
*/
|
||||
#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
|
||||
#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
|
||||
#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
|
||||
#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
|
||||
#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
|
||||
#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
|
||||
#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
|
||||
#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
|
||||
#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
|
||||
#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
|
||||
#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
|
||||
#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
|
||||
#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
|
||||
|
||||
/* IIC parameter RAM.
|
||||
*/
|
||||
typedef struct iic {
|
||||
ushort iic_rbase; /* Rx Buffer descriptor base address */
|
||||
ushort iic_tbase; /* Tx Buffer descriptor base address */
|
||||
u_char iic_rfcr; /* Rx function code */
|
||||
u_char iic_tfcr; /* Tx function code */
|
||||
ushort iic_mrblr; /* Max receive buffer length */
|
||||
uint iic_rstate; /* Internal */
|
||||
uint iic_rdp; /* Internal */
|
||||
ushort iic_rbptr; /* Internal */
|
||||
ushort iic_rbc; /* Internal */
|
||||
uint iic_rxtmp; /* Internal */
|
||||
uint iic_tstate; /* Internal */
|
||||
uint iic_tdp; /* Internal */
|
||||
ushort iic_tbptr; /* Internal */
|
||||
ushort iic_tbc; /* Internal */
|
||||
uint iic_txtmp; /* Internal */
|
||||
} iic_t;
|
||||
|
||||
/* SPI parameter RAM.
|
||||
*/
|
||||
typedef struct spi {
|
||||
ushort spi_rbase; /* Rx Buffer descriptor base address */
|
||||
ushort spi_tbase; /* Tx Buffer descriptor base address */
|
||||
u_char spi_rfcr; /* Rx function code */
|
||||
u_char spi_tfcr; /* Tx function code */
|
||||
ushort spi_mrblr; /* Max receive buffer length */
|
||||
uint spi_rstate; /* Internal */
|
||||
uint spi_rdp; /* Internal */
|
||||
ushort spi_rbptr; /* Internal */
|
||||
ushort spi_rbc; /* Internal */
|
||||
uint spi_rxtmp; /* Internal */
|
||||
uint spi_tstate; /* Internal */
|
||||
uint spi_tdp; /* Internal */
|
||||
ushort spi_tbptr; /* Internal */
|
||||
ushort spi_tbc; /* Internal */
|
||||
uint spi_txtmp; /* Internal */
|
||||
uint spi_res; /* Tx temp. */
|
||||
uint spi_res1[4]; /* SDMA temp. */
|
||||
} spi_t;
|
||||
|
||||
/* SPI Mode register.
|
||||
*/
|
||||
#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
|
||||
#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
|
||||
#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
|
||||
#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
|
||||
#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
|
||||
#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
|
||||
#define SPMODE_EN ((ushort)0x0100) /* Enable */
|
||||
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
|
||||
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
|
||||
|
||||
#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
|
||||
#define SPMODE_PM(x) ((x) &0xF)
|
||||
|
||||
#define SPI_EB ((u_char)0x10) /* big endian byte order */
|
||||
|
||||
#define BD_IIC_START ((ushort)0x0400)
|
||||
|
||||
#endif /* __CPM_82XX__ */
|
||||
|
|
@ -0,0 +1,583 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
/*
|
||||
* UART test
|
||||
*
|
||||
* The Serial Management Controllers (SMC) and the Serial Communication
|
||||
* Controllers (SCC) listed in ctlr_list array below are tested in
|
||||
* the loopback UART mode.
|
||||
* The controllers are configured accordingly and several characters
|
||||
* are transmitted. The configurable test parameters are:
|
||||
* MIN_PACKET_LENGTH - minimum size of packet to transmit
|
||||
* MAX_PACKET_LENGTH - maximum size of packet to transmit
|
||||
* TEST_NUM - number of tests
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
|
||||
#include <post.h>
|
||||
#if defined(CONFIG_8xx)
|
||||
#include <commproc.h>
|
||||
#elif defined(CONFIG_MPC8260)
|
||||
#include <asm/cpm_8260.h>
|
||||
#else
|
||||
#error "Apparently a bad configuration, please fix."
|
||||
#endif
|
||||
#include <command.h>
|
||||
#include <net.h>
|
||||
|
||||
#if CONFIG_POST & CFG_POST_UART
|
||||
|
||||
#define CTLR_SMC 0
|
||||
#define CTLR_SCC 1
|
||||
|
||||
/* The list of controllers to test */
|
||||
#if defined(CONFIG_MPC823)
|
||||
static int ctlr_list[][2] =
|
||||
{ {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
|
||||
#else
|
||||
static int ctlr_list[][2] = { };
|
||||
#endif
|
||||
|
||||
#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
|
||||
|
||||
static struct {
|
||||
void (*init) (int index);
|
||||
void (*putc) (int index, const char c);
|
||||
int (*getc) (int index);
|
||||
} ctlr_proc[2];
|
||||
|
||||
static char *ctlr_name[2] = { "SMC", "SCC" };
|
||||
|
||||
static int used_by_uart[2] = { -1, -1 };
|
||||
static int used_by_ether[2] = { -1, -1 };
|
||||
|
||||
static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
|
||||
static int proff_scc[] =
|
||||
{ PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
|
||||
|
||||
/*
|
||||
* SMC callbacks
|
||||
*/
|
||||
|
||||
static void smc_init (int smc_index)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
|
||||
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
volatile smc_t *sp;
|
||||
volatile smc_uart_t *up;
|
||||
volatile cbd_t *tbdf, *rbdf;
|
||||
volatile cpm8xx_t *cp = &(im->im_cpm);
|
||||
uint dpaddr;
|
||||
|
||||
/* initialize pointers to SMC */
|
||||
|
||||
sp = (smc_t *) & (cp->cp_smc[smc_index]);
|
||||
up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
|
||||
|
||||
/* Disable transmitter/receiver.
|
||||
*/
|
||||
sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
|
||||
/* Enable SDMA.
|
||||
*/
|
||||
im->im_siu_conf.sc_sdcr = 1;
|
||||
|
||||
/* clear error conditions */
|
||||
#ifdef CFG_SDSR
|
||||
im->im_sdma.sdma_sdsr = CFG_SDSR;
|
||||
#else
|
||||
im->im_sdma.sdma_sdsr = 0x83;
|
||||
#endif
|
||||
|
||||
/* clear SDMA interrupt mask */
|
||||
#ifdef CFG_SDMR
|
||||
im->im_sdma.sdma_sdmr = CFG_SDMR;
|
||||
#else
|
||||
im->im_sdma.sdma_sdmr = 0x00;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FADS)
|
||||
/* Enable RS232 */
|
||||
*((uint *) BCSR1) &=
|
||||
~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
|
||||
/* Enable Monitor Port Transceiver */
|
||||
*((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
|
||||
#endif
|
||||
|
||||
/* Set the physical address of the host memory buffers in
|
||||
* the buffer descriptors.
|
||||
*/
|
||||
|
||||
#ifdef CFG_ALLOC_DPRAM
|
||||
dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
|
||||
#else
|
||||
dpaddr = CPM_POST_BASE;
|
||||
#endif
|
||||
|
||||
/* Allocate space for two buffer descriptors in the DP ram.
|
||||
* For now, this address seems OK, but it may have to
|
||||
* change with newer versions of the firmware.
|
||||
* damm: allocating space after the two buffers for rx/tx data
|
||||
*/
|
||||
|
||||
rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
|
||||
rbdf->cbd_bufaddr = (uint) (rbdf + 2);
|
||||
rbdf->cbd_sc = 0;
|
||||
tbdf = rbdf + 1;
|
||||
tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
|
||||
tbdf->cbd_sc = 0;
|
||||
|
||||
/* Set up the uart parameters in the parameter ram.
|
||||
*/
|
||||
up->smc_rbase = dpaddr;
|
||||
up->smc_tbase = dpaddr + sizeof (cbd_t);
|
||||
up->smc_rfcr = SMC_EB;
|
||||
up->smc_tfcr = SMC_EB;
|
||||
|
||||
#if defined(CONFIG_MBX)
|
||||
board_serial_init ();
|
||||
#endif
|
||||
|
||||
/* Set UART mode, 8 bit, no parity, one stop.
|
||||
* Enable receive and transmit.
|
||||
* Set local loopback mode.
|
||||
*/
|
||||
sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
|
||||
|
||||
/* Mask all interrupts and remove anything pending.
|
||||
*/
|
||||
sp->smc_smcm = 0;
|
||||
sp->smc_smce = 0xff;
|
||||
|
||||
/* Set up the baud rate generator.
|
||||
*/
|
||||
cp->cp_simode = 0x00000000;
|
||||
|
||||
cp->cp_brgc1 =
|
||||
(((gd->cpu_clk / 16 / gd->baudrate) -
|
||||
1) << 1) | CPM_BRG_EN;
|
||||
|
||||
/* Make the first buffer the only buffer.
|
||||
*/
|
||||
tbdf->cbd_sc |= BD_SC_WRAP;
|
||||
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
|
||||
|
||||
/* Single character receive.
|
||||
*/
|
||||
up->smc_mrblr = 1;
|
||||
up->smc_maxidl = 0;
|
||||
|
||||
/* Initialize Tx/Rx parameters.
|
||||
*/
|
||||
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
|
||||
;
|
||||
|
||||
cp->cp_cpcr =
|
||||
mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
|
||||
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
|
||||
;
|
||||
|
||||
/* Enable transmitter/receiver.
|
||||
*/
|
||||
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
|
||||
}
|
||||
|
||||
static void smc_putc (int smc_index, const char c)
|
||||
{
|
||||
volatile cbd_t *tbdf;
|
||||
volatile char *buf;
|
||||
volatile smc_uart_t *up;
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
||||
|
||||
up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
|
||||
|
||||
tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
|
||||
|
||||
/* Wait for last character to go.
|
||||
*/
|
||||
|
||||
buf = (char *) tbdf->cbd_bufaddr;
|
||||
#if 0
|
||||
__asm__ ("eieio");
|
||||
while (tbdf->cbd_sc & BD_SC_READY)
|
||||
__asm__ ("eieio");
|
||||
#endif
|
||||
|
||||
*buf = c;
|
||||
tbdf->cbd_datlen = 1;
|
||||
tbdf->cbd_sc |= BD_SC_READY;
|
||||
__asm__ ("eieio");
|
||||
#if 1
|
||||
while (tbdf->cbd_sc & BD_SC_READY)
|
||||
__asm__ ("eieio");
|
||||
#endif
|
||||
}
|
||||
|
||||
static int smc_getc (int smc_index)
|
||||
{
|
||||
volatile cbd_t *rbdf;
|
||||
volatile unsigned char *buf;
|
||||
volatile smc_uart_t *up;
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
||||
unsigned char c;
|
||||
int i;
|
||||
|
||||
up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
|
||||
|
||||
rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
|
||||
|
||||
/* Wait for character to show up.
|
||||
*/
|
||||
buf = (unsigned char *) rbdf->cbd_bufaddr;
|
||||
#if 0
|
||||
while (rbdf->cbd_sc & BD_SC_EMPTY);
|
||||
#else
|
||||
for (i = 100; i > 0; i--) {
|
||||
if (!(rbdf->cbd_sc & BD_SC_EMPTY))
|
||||
break;
|
||||
udelay (1000);
|
||||
}
|
||||
|
||||
if (i == 0)
|
||||
return -1;
|
||||
#endif
|
||||
c = *buf;
|
||||
rbdf->cbd_sc |= BD_SC_EMPTY;
|
||||
|
||||
return (c);
|
||||
}
|
||||
|
||||
/*
|
||||
* SCC callbacks
|
||||
*/
|
||||
|
||||
static void scc_init (int scc_index)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static int cpm_cr_ch[] = {
|
||||
CPM_CR_CH_SCC1,
|
||||
CPM_CR_CH_SCC2,
|
||||
CPM_CR_CH_SCC3,
|
||||
CPM_CR_CH_SCC4,
|
||||
};
|
||||
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
volatile scc_t *sp;
|
||||
volatile scc_uart_t *up;
|
||||
volatile cbd_t *tbdf, *rbdf;
|
||||
volatile cpm8xx_t *cp = &(im->im_cpm);
|
||||
uint dpaddr;
|
||||
|
||||
/* initialize pointers to SCC */
|
||||
|
||||
sp = (scc_t *) & (cp->cp_scc[scc_index]);
|
||||
up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
|
||||
|
||||
/* Disable transmitter/receiver.
|
||||
*/
|
||||
sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
|
||||
|
||||
/* Allocate space for two buffer descriptors in the DP ram.
|
||||
*/
|
||||
|
||||
#ifdef CFG_ALLOC_DPRAM
|
||||
dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
|
||||
#else
|
||||
dpaddr = CPM_POST_BASE;
|
||||
#endif
|
||||
|
||||
/* Enable SDMA.
|
||||
*/
|
||||
im->im_siu_conf.sc_sdcr = 0x0001;
|
||||
|
||||
/* Set the physical address of the host memory buffers in
|
||||
* the buffer descriptors.
|
||||
*/
|
||||
|
||||
rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
|
||||
rbdf->cbd_bufaddr = (uint) (rbdf + 2);
|
||||
rbdf->cbd_sc = 0;
|
||||
tbdf = rbdf + 1;
|
||||
tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
|
||||
tbdf->cbd_sc = 0;
|
||||
|
||||
/* Set up the baud rate generator.
|
||||
*/
|
||||
cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
|
||||
/* no |= needed, since BRG1 is 000 */
|
||||
|
||||
cp->cp_brgc1 =
|
||||
(((gd->cpu_clk / 16 / gd->baudrate) -
|
||||
1) << 1) | CPM_BRG_EN;
|
||||
|
||||
/* Set up the uart parameters in the parameter ram.
|
||||
*/
|
||||
up->scc_genscc.scc_rbase = dpaddr;
|
||||
up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
|
||||
|
||||
/* Initialize Tx/Rx parameters.
|
||||
*/
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
|
||||
;
|
||||
cp->cp_cpcr =
|
||||
mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
|
||||
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
|
||||
;
|
||||
|
||||
up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
|
||||
up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
|
||||
|
||||
up->scc_genscc.scc_mrblr = 1; /* Single character receive */
|
||||
up->scc_maxidl = 0; /* disable max idle */
|
||||
up->scc_brkcr = 1; /* send one break character on stop TX */
|
||||
up->scc_parec = 0;
|
||||
up->scc_frmec = 0;
|
||||
up->scc_nosec = 0;
|
||||
up->scc_brkec = 0;
|
||||
up->scc_uaddr1 = 0;
|
||||
up->scc_uaddr2 = 0;
|
||||
up->scc_toseq = 0;
|
||||
up->scc_char1 = 0x8000;
|
||||
up->scc_char2 = 0x8000;
|
||||
up->scc_char3 = 0x8000;
|
||||
up->scc_char4 = 0x8000;
|
||||
up->scc_char5 = 0x8000;
|
||||
up->scc_char6 = 0x8000;
|
||||
up->scc_char7 = 0x8000;
|
||||
up->scc_char8 = 0x8000;
|
||||
up->scc_rccm = 0xc0ff;
|
||||
|
||||
/* Set low latency / small fifo.
|
||||
*/
|
||||
sp->scc_gsmrh = SCC_GSMRH_RFW;
|
||||
|
||||
/* Set UART mode
|
||||
*/
|
||||
sp->scc_gsmrl &= ~0xF;
|
||||
sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
|
||||
|
||||
/* Set local loopback mode.
|
||||
*/
|
||||
sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
|
||||
sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
|
||||
|
||||
/* Set clock divider 16 on Tx and Rx
|
||||
*/
|
||||
sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
|
||||
|
||||
sp->scc_psmr |= SCU_PSMR_CL;
|
||||
|
||||
/* Mask all interrupts and remove anything pending.
|
||||
*/
|
||||
sp->scc_sccm = 0;
|
||||
sp->scc_scce = 0xffff;
|
||||
sp->scc_dsr = 0x7e7e;
|
||||
sp->scc_psmr = 0x3000;
|
||||
|
||||
/* Make the first buffer the only buffer.
|
||||
*/
|
||||
tbdf->cbd_sc |= BD_SC_WRAP;
|
||||
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
|
||||
|
||||
/* Enable transmitter/receiver.
|
||||
*/
|
||||
sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
}
|
||||
|
||||
static void scc_putc (int scc_index, const char c)
|
||||
{
|
||||
volatile cbd_t *tbdf;
|
||||
volatile char *buf;
|
||||
volatile scc_uart_t *up;
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
||||
|
||||
up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
|
||||
|
||||
tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
|
||||
|
||||
/* Wait for last character to go.
|
||||
*/
|
||||
|
||||
buf = (char *) tbdf->cbd_bufaddr;
|
||||
#if 0
|
||||
__asm__ ("eieio");
|
||||
while (tbdf->cbd_sc & BD_SC_READY)
|
||||
__asm__ ("eieio");
|
||||
#endif
|
||||
|
||||
*buf = c;
|
||||
tbdf->cbd_datlen = 1;
|
||||
tbdf->cbd_sc |= BD_SC_READY;
|
||||
__asm__ ("eieio");
|
||||
#if 1
|
||||
while (tbdf->cbd_sc & BD_SC_READY)
|
||||
__asm__ ("eieio");
|
||||
#endif
|
||||
}
|
||||
|
||||
static int scc_getc (int scc_index)
|
||||
{
|
||||
volatile cbd_t *rbdf;
|
||||
volatile unsigned char *buf;
|
||||
volatile scc_uart_t *up;
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
||||
unsigned char c;
|
||||
int i;
|
||||
|
||||
up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
|
||||
|
||||
rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
|
||||
|
||||
/* Wait for character to show up.
|
||||
*/
|
||||
buf = (unsigned char *) rbdf->cbd_bufaddr;
|
||||
#if 0
|
||||
while (rbdf->cbd_sc & BD_SC_EMPTY);
|
||||
#else
|
||||
for (i = 100; i > 0; i--) {
|
||||
if (!(rbdf->cbd_sc & BD_SC_EMPTY))
|
||||
break;
|
||||
udelay (1000);
|
||||
}
|
||||
|
||||
if (i == 0)
|
||||
return -1;
|
||||
#endif
|
||||
c = *buf;
|
||||
rbdf->cbd_sc |= BD_SC_EMPTY;
|
||||
|
||||
return (c);
|
||||
}
|
||||
|
||||
/*
|
||||
* Test routines
|
||||
*/
|
||||
|
||||
static int test_ctlr (int ctlr, int index)
|
||||
{
|
||||
int res = -1;
|
||||
char test_str[] = "*** UART Test String ***\r\n";
|
||||
int i;
|
||||
|
||||
#if !defined(CONFIG_8xx_CONS_NONE)
|
||||
if (used_by_uart[ctlr] == index) {
|
||||
while (ctlr_proc[ctlr].getc (index) != -1);
|
||||
}
|
||||
#endif
|
||||
|
||||
ctlr_proc[ctlr].init (index);
|
||||
|
||||
for (i = 0; i < sizeof (test_str) - 1; i++) {
|
||||
ctlr_proc[ctlr].putc (index, test_str[i]);
|
||||
if (ctlr_proc[ctlr].getc (index) != test_str[i])
|
||||
goto Done;
|
||||
}
|
||||
|
||||
res = 0;
|
||||
|
||||
Done:
|
||||
|
||||
#if !defined(CONFIG_8xx_CONS_NONE)
|
||||
if (used_by_uart[ctlr] == index) {
|
||||
serial_init ();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(SCC_ENET)
|
||||
if (used_by_ether[ctlr] == index) {
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
eth_init (gd->bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (res != 0) {
|
||||
post_log ("uart %s%d test failed\n",
|
||||
ctlr_name[ctlr], index + 1);
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
int uart_post_test (int flags)
|
||||
{
|
||||
int res = 0;
|
||||
int i;
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SMC1)
|
||||
used_by_uart[CTLR_SMC] = 0;
|
||||
#elif defined(CONFIG_8xx_CONS_SMC2)
|
||||
used_by_uart[CTLR_SMC] = 1;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC1)
|
||||
used_by_uart[CTLR_SCC] = 0;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC2)
|
||||
used_by_uart[CTLR_SCC] = 1;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC3)
|
||||
used_by_uart[CTLR_SCC] = 2;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC4)
|
||||
used_by_uart[CTLR_SCC] = 3;
|
||||
#endif
|
||||
|
||||
#if defined(SCC_ENET)
|
||||
used_by_ether[CTLR_SCC] = SCC_ENET;
|
||||
#endif
|
||||
|
||||
ctlr_proc[CTLR_SMC].init = smc_init;
|
||||
ctlr_proc[CTLR_SMC].putc = smc_putc;
|
||||
ctlr_proc[CTLR_SMC].getc = smc_getc;
|
||||
|
||||
ctlr_proc[CTLR_SCC].init = scc_init;
|
||||
ctlr_proc[CTLR_SCC].putc = scc_putc;
|
||||
ctlr_proc[CTLR_SCC].getc = scc_getc;
|
||||
|
||||
for (i = 0; i < CTRL_LIST_SIZE; i++) {
|
||||
if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
|
||||
res = -1;
|
||||
}
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_POST & CFG_POST_UART */
|
||||
|
||||
#endif /* CONFIG_POST */
|
||||
Loading…
Reference in New Issue