imx27lite: add support for imx27lite board from LogicPD
This patch adds support for i.MX27-LITEKIT development board from LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND flash, FEC ethernet controller integrated into i.MX27. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Acked-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Ilya Yanok
Jean-Christophe PLAGNIOL-VILLARD
parent
50b5fff558
commit
10bc241dfc
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@ -543,6 +543,7 @@ George G. Davis <gdavis@mvista.com>
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gcplus SA1100
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Wolfgang Denk <wd@denx.de>
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imx27lite i.MX27
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qong i.MX31
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Thomas Elste <info@elste.org>
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1
MAKEALL
1
MAKEALL
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@ -520,6 +520,7 @@ LIST_ARM9=" \
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cp926ejs \
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cp946es \
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cp966 \
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imx27lite \
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lpd7a400 \
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mv88f6281gtw_ge \
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mx1ads \
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3
Makefile
3
Makefile
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@ -2938,6 +2938,9 @@ davinci_sonata_config : unconfig
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davinci_dm355evm_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs dm355evm davinci davinci
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imx27lite_config: unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
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lpd7a400_config \
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lpd7a404_config: unconfig
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@$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
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@ -0,0 +1,51 @@
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := imx27lite.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1 @@
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TEXT_BASE = 0xA7F00000
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@ -0,0 +1,73 @@
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
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* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init (void)
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{
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struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
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gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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#ifdef CONFIG_MXC_UART
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mx27_uart_init_pins();
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#endif
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#ifdef CONFIG_FEC_MXC
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mx27_fec_init_pins();
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imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
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writel(readl(®s->port[PORTC].dr) | (1 << 31),
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®s->port[PORTC].dr);
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#endif
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#ifdef CONFIG_MXC_MMC
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mx27_sd2_init_pins();
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#endif
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return 0;
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}
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int dram_init (void)
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{
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#if CONFIG_NR_DRAM_BANKS > 0
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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#endif
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#if CONFIG_NR_DRAM_BANKS > 1
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
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PHYS_SDRAM_2_SIZE);
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#endif
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return 0;
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}
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int checkboard(void)
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{
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printf("LogicPD imx27lite\n");
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return 0;
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}
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@ -0,0 +1,170 @@
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/*
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* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
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* Applications Processor Reference Manual, Rev. 0.2".
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*
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* (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
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* (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/asm-offsets.h>
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SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
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SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
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SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
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SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
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SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
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ESDCTL_ROW13 | ESDCTL_COL10)
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SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
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ESDCTL_ROW13 | ESDCTL_COL10)
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SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
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ESDCTL_ROW13 | ESDCTL_COL10)
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SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
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.macro init_aipi
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/*
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* setup AIPI1 and AIPI2
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*/
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write32 AIPI1_PSR0, AIPI1_PSR0_VAL
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write32 AIPI1_PSR1, AIPI1_PSR1_VAL
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write32 AIPI2_PSR0, AIPI2_PSR0_VAL
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write32 AIPI2_PSR1, AIPI2_PSR1_VAL
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.endm /* init_aipi */
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.macro init_clock
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ldr r0, =CSCR
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/* disable MPLL/SPLL first */
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ldr r1, [r0]
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bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
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str r1, [r0]
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write32 MPCTL0, MPCTL0_VAL
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write32 SPCTL0, SPCTL0_VAL
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write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
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/*
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* add some delay here
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*/
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wait_timer 0x1000
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/* peripheral clock divider */
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write32 PCDR0, PCDR0_VAL
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write32 PCDR1, PCDR1_VAL
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/* Configure PCCR0 and PCCR1 */
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write32 PCCR0, PCCR0_VAL
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write32 PCCR1, PCCR1_VAL
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.endm /* init_clock */
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.macro sdram_init
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ldr r0, SOC_ESDCTL_BASE_W
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mov r2, #PHYS_SDRAM_1
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/* Do initial reset */
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mov r1, #ESDMISC_MDDR_DL_RST
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str r1, [r0, #ESDMISC_ROF]
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/* Hold for more than 200ns */
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wait_timer 0x10000
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/* Activate LPDDR iface */
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mov r1, #ESDMISC_MDDREN
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str r1, [r0, #ESDMISC_ROF]
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/* Check The chip version TO1 or TO2 */
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ldr r1, SOC_SI_ID_REG_W
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ldr r1, [r1]
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ands r1, r1, #0xF0000000
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/* add Latency on CAS only for TO2 */
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ldreq r1, SDRAM_ESDCFG_T2_W
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ldrne r1, SDRAM_ESDCFG_T1_W
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str r1, [r0, #ESDCFG0_ROF]
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/* Run initialization sequence */
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ldr r1, SDRAM_PRECHARGE_CMD_W
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str r1, [r0, #ESDCTL0_ROF]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, SDRAM_AUTOREF_CMD_W
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str r1, [r0, #ESDCTL0_ROF]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, SDRAM_LOADMODE_CMD_W
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str r1, [r0, #ESDCTL0_ROF]
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ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
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add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
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ldrb r1, [r3]
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ldr r1, SDRAM_NORMAL_CMD_W
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str r1, [r0, #ESDCTL0_ROF]
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#if (CONFIG_NR_DRAM_BANKS > 1)
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/* 2nd sdram */
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mov r2, #PHYS_SDRAM_2
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/* Check The chip version TO1 or TO2 */
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ldr r1, SOC_SI_ID_REG_W
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ldr r1, [r1]
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ands r1, r1, #0xF0000000
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/* add Latency on CAS only for TO2 */
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ldreq r1, SDRAM_ESDCFG_T2_W
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ldrne r1, SDRAM_ESDCFG_T1_W
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str r1, [r0, #ESDCFG1_ROF]
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/* Run initialization sequence */
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ldr r1, SDRAM_PRECHARGE_CMD_W
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str r1, [r0, #ESDCTL1_ROF]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, SDRAM_AUTOREF_CMD_W
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str r1, [r0, #ESDCTL1_ROF]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, SDRAM_LOADMODE_CMD_W
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str r1, [r0, #ESDCTL1_ROF]
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ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
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add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
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ldrb r1, [r3]
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ldr r1, SDRAM_NORMAL_CMD_W
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str r1, [r0, #ESDCTL1_ROF]
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#endif /* CONFIG_NR_DRAM_BANKS > 1 */
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.endm /* sdram_init */
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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init_aipi
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init_clock
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sdram_init
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mov pc,r10
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@ -264,3 +264,68 @@ void imx_gpio_mode(int gpio_mode)
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®s->port[port].iconfb2);
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}
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}
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#ifdef CONFIG_MXC_UART
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void mx27_uart_init_pins(void)
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{
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int i;
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unsigned int mode[] = {
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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};
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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}
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#endif /* CONFIG_MXC_UART */
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#ifdef CONFIG_FEC_MXC
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void mx27_fec_init_pins(void)
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{
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int i;
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unsigned int mode[] = {
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC | GPIO_PUEN,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_CLR,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN,
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};
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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}
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#endif /* CONFIG_FEC_MXC */
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#ifdef CONFIG_MXC_MMC
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void mx27_sd2_init_pins(void)
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{
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int i;
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unsigned int mode[] = {
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PB4_PF_SD2_D0,
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PB5_PF_SD2_D1,
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PB6_PF_SD2_D2,
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PB7_PF_SD2_D3,
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PB8_PF_SD2_CMD,
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PB9_PF_SD2_CLK,
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};
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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}
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#endif /* CONFIG_MXC_MMC */
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@ -28,6 +28,18 @@
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extern void imx_gpio_mode (int gpio_mode);
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#ifdef CONFIG_MXC_UART
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extern void mx27_uart_init_pins(void);
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#endif /* CONFIG_MXC_UART */
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#ifdef CONFIG_FEC_MXC
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extern void mx27_fec_init_pins(void);
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#endif /* CONFIG_FEC_MXC */
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#ifdef CONFIG_MXC_MMC
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extern void mx27_sd2_init_pins(void);
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#endif /* CONFIG_MXC_MMC */
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/* AIPI */
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struct aipi_regs {
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u32 psr0;
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@ -0,0 +1,252 @@
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/*
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* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
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*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC Configuration
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*/
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */
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#define CONFIG_MX27
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#define CONFIG_IMX27LITE
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#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/*
|
||||
* Lowlevel configuration
|
||||
*/
|
||||
#define SDRAM_ESDCFG_REGISTER_VAL(cas) \
|
||||
(ESDCFG_TRC(10) | \
|
||||
ESDCFG_TRCD(3) | \
|
||||
ESDCFG_TCAS(cas) | \
|
||||
ESDCFG_TRRD(1) | \
|
||||
ESDCFG_TRAS(5) | \
|
||||
ESDCFG_TWR | \
|
||||
ESDCFG_TMRD(2) | \
|
||||
ESDCFG_TRP(2) | \
|
||||
ESDCFG_TXP(3))
|
||||
|
||||
#define SDRAM_ESDCTL_REGISTER_VAL \
|
||||
(ESDCTL_PRCT(0) | \
|
||||
ESDCTL_BL | \
|
||||
ESDCTL_PWDT(0) | \
|
||||
ESDCTL_SREFR(3) | \
|
||||
ESDCTL_DSIZ_32 | \
|
||||
ESDCTL_COL10 | \
|
||||
ESDCTL_ROW13 | \
|
||||
ESDCTL_SDE)
|
||||
|
||||
#define SDRAM_ALL_VAL 0xf00
|
||||
|
||||
#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
|
||||
#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
|
||||
|
||||
#define MPCTL0_VAL 0x1ef15d5
|
||||
|
||||
#define SPCTL0_VAL 0x043a1c09
|
||||
|
||||
#define CSCR_VAL 0x33f08107
|
||||
|
||||
#define PCDR0_VAL 0x120470c3
|
||||
#define PCDR1_VAL 0x03030303
|
||||
#define PCCR0_VAL 0xffffffff
|
||||
#define PCCR1_VAL 0xfffffffc
|
||||
|
||||
#define AIPI1_PSR0_VAL 0x20040304
|
||||
#define AIPI1_PSR1_VAL 0xdffbfcfb
|
||||
#define AIPI2_PSR0_VAL 0x07ffc200
|
||||
#define AIPI2_PSR1_VAL 0xffffffff
|
||||
|
||||
/*
|
||||
* Memory Info
|
||||
*/
|
||||
/* malloc() len */
|
||||
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
|
||||
/* reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
/* memtest start address */
|
||||
#define CONFIG_SYS_MEMTEST_START 0xA0000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
|
||||
#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
|
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
|
||||
|
||||
/*
|
||||
* Serial Driver info
|
||||
*/
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_SYS_MX27_UART1
|
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Flash & Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
/* Use buffered writes (~10x faster) */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
|
||||
/* Use hardware sector protection */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
|
||||
#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */
|
||||
/* end of flash */
|
||||
#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000)
|
||||
/* CS2 Base address */
|
||||
#define PHYS_FLASH_1 0xc0000000
|
||||
/* Flash Base for U-Boot */
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
/* Flash size 2MB */
|
||||
#define PHYS_FLASH_SIZE 0x200000
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
|
||||
CONFIG_SYS_FLASH_SECT_SZ)
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1f
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
/*
|
||||
* MTD
|
||||
*/
|
||||
#define CONFIG_MTD_DEVICE
|
||||
|
||||
/*
|
||||
* NAND
|
||||
*/
|
||||
#define CONFIG_NAND_MXC
|
||||
#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0xd8000000
|
||||
#define CONFIG_JFFS2_NAND
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
|
||||
/*
|
||||
* SD/MMC
|
||||
*/
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MXC_MMC
|
||||
#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* MTD partitions
|
||||
*/
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
|
||||
#define MTDPARTS_DEFAULT \
|
||||
"mtdparts=" \
|
||||
"physmap-flash.0:" \
|
||||
"256k(U-Boot)," \
|
||||
"1664k(user)," \
|
||||
"64k(env1)," \
|
||||
"64k(env2);" \
|
||||
"mxc_nand.0:" \
|
||||
"128k(IPL-SPL)," \
|
||||
"4m(kernel)," \
|
||||
"22m(rootfs)," \
|
||||
"-(userfs)"
|
||||
|
||||
/*
|
||||
* U-Boot general configuration
|
||||
*/
|
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
/* Print buffer sz */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
|
||||
/*
|
||||
* U-Boot commands
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define xstr(s) str(s)
|
||||
#define str(s) #s
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=ttymxc0,${baudrate}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs}\0" \
|
||||
"u-boot=imx27/u-boot.bin\0" \
|
||||
"kernel_addr_r=a0800000\0" \
|
||||
"hostname=imx27\0" \
|
||||
"bootfile=imx27/uImage\0" \
|
||||
"rootpath=/opt/eldk-4.2-arm/arm\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm\0" \
|
||||
"bootcmd=run net_nfs\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};cp.b ${fileaddr} " \
|
||||
xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
||||
"upd=run load update\0" \
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue