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85xx: Add basic e500mc core support 

Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.

* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2008-10-23 01:47:38 -05:00 committed by Andrew Fleming-AFLEMING
parent a38a5b6edd
commit 0f060c3bf8
4 changed files with 16 additions and 0 deletions
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4
cpu/mpc85xx/cpu.c
View File

@ -134,6 +134,10 @@ int checkcpu (void)
puts("Unknown");
break;
}
if (PVR_MEM(pvr) == 0x03)
puts("MC");
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);

8
cpu/mpc85xx/release.S
View File

@ -24,14 +24,18 @@
__secondary_start_page:
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
#ifndef CONFIG_E500MC
ori r3,r3,HID0_TBEN@l /* enable Timebase */
#endif
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr SPRN_HID1,r3
#endif
/* Enable branch prediction */
li r3,0x201
@ -64,7 +68,11 @@ __secondary_start_page:
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
#ifdef CONFIG_E500MC
rlwinm r4,r0,27,27,31
#else
mr r4,r0
#endif
slwi r8,r4,5
add r10,r3,r8

2
cpu/mpc85xx/start.S
View File

@ -163,8 +163,10 @@ _start_e500:
ori r0,r0,HID0_TBEN@l /* Enable Timebase */
mtspr HID0,r0
#ifndef CONFIG_E500MC
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr HID1,r0
#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)

2
include/asm-ppc/cache.h
View File

@ -12,6 +12,8 @@
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
#elif defined(CONFIG_E500MC)
#define L1_CACHE_SHIFT 6
#else
#define L1_CACHE_SHIFT 5
#endif