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8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx 

The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Poonam Aggrwal 2009-07-31 12:08:14 +05:30 committed by Kumar Gala
parent 18bacc2027
commit 0e870980a6
22 changed files with 127 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
common/cmd_mp.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -34,9 +34,9 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
cpuid = simple_strtoul(argv[1], NULL, 10);
if (cpuid >= CONFIG_NUM_CPUS) {
if (cpuid >= cpu_numcores()) {
printf ("Core num: %lu is out of range[0..%d]\n",
cpuid, CONFIG_NUM_CPUS - 1);
cpuid, cpu_numcores() - 1);
return 1;
}

21
cpu/mpc85xx/cpu.c
View File

@ -54,24 +54,23 @@ int checkcpu (void)
int i;
svr = get_svr();
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
#ifdef CONFIG_MPC8536
major &= 0x7; /* the msb of this nibble is a mfg code */
#endif
minor = SVR_MIN(svr);
#if (CONFIG_NUM_CPUS > 1)
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
printf("CPU%d: ", pic->whoami);
#else
puts("CPU: ");
#endif
if (cpu_numcores() > 1) {
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
printf("CPU%d: ", pic->whoami);
} else {
puts("CPU: ");
}
cpu = identify_cpu(ver);
if (cpu) {
cpu = gd->cpu;
if (cpu->name) {
puts(cpu->name);
if (IS_E_PROCESSOR(svr))
puts("E");
} else {
@ -104,7 +103,7 @@ int checkcpu (void)
get_sys_info(&sysinfo);
puts("Clock Configuration:");
for (i = 0; i < CONFIG_NUM_CPUS; i++) {
for (i = 0; i < cpu_numcores(); i++) {
if (!(i & 3))
printf ("\n ");
printf("CPU%d:%-4s MHz, ",

6
cpu/mpc85xx/mp.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008 Freescale Semiconductor.
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -157,7 +157,7 @@ static void pq3_mp_up(unsigned long bootpg)
out_be32(&gur->devdisr, devdisr);
/* release the hounds */
up = ((1 << CONFIG_NUM_CPUS) - 1);
up = ((1 << cpu_numcores()) - 1);
bpcr = in_be32(&ecm->eebpcr);
bpcr |= (up << 24);
out_be32(&ecm->eebpcr, bpcr);
@ -167,7 +167,7 @@ static void pq3_mp_up(unsigned long bootpg)
/* wait for everyone */
while (timeout) {
int i;
for (i = 0; i < CONFIG_NUM_CPUS; i++) {
for (i = 0; i < cpu_numcores(); i++) {
if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
cpu_up_mask |= (1 << i);
};

25
cpu/mpc85xx/release.S
View File

@ -1,3 +1,26 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <mpc85xx.h>
#include <version.h>
@ -203,7 +226,7 @@ __secondary_start_page:
.align L1_CACHE_SHIFT
.globl __spin_table
__spin_table:
.space CONFIG_NUM_CPUS*ENTRY_SIZE
.space CONFIG_MAX_CPUS*ENTRY_SIZE
/* Fill in the empty space. The actual reset vector is
* the last word of the page */

4
cpu/mpc85xx/speed.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2004, 2007-2009 Freescale Semiconductor Inc.
* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
@ -51,7 +51,7 @@ void get_sys_info (sys_info_t * sysInfo)
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
half_freqSystemBus = sysInfo->freqSystemBus/2;
for (i = 0; i < CONFIG_NUM_CPUS; i++) {
for (i = 0; i < cpu_numcores(); i++) {
e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
}

10
cpu/mpc86xx/cpu.c
View File

@ -30,6 +30,8 @@
#include <mpc86xx.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Default board reset function
*/
@ -61,12 +63,12 @@ checkcpu(void)
puts("CPU: ");
cpu = identify_cpu(ver);
if (cpu) {
cpu = gd->cpu;
if (cpu->name)
puts(cpu->name);
} else {
else
puts("Unknown");
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
puts("Core: ");

4
cpu/mpc86xx/cpu_init.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright 2004,2009 Freescale Semiconductor, Inc.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@ -129,7 +129,7 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
#if (CONFIG_NUM_CPUS > 1)
#if defined(CONFIG_MP)
setup_mp();
#endif
return 0;

93
cpu/mpc8xxx/cpu.c
View File

@ -35,41 +35,41 @@ DECLARE_GLOBAL_DATA_PTR;
struct cpu_type cpu_type_list [] = {
#if defined(CONFIG_MPC85xx)
CPU_TYPE_ENTRY(8533, 8533),
CPU_TYPE_ENTRY(8533, 8533_E),
CPU_TYPE_ENTRY(8535, 8535),
CPU_TYPE_ENTRY(8535, 8535_E),
CPU_TYPE_ENTRY(8536, 8536),
CPU_TYPE_ENTRY(8536, 8536_E),
CPU_TYPE_ENTRY(8540, 8540),
CPU_TYPE_ENTRY(8541, 8541),
CPU_TYPE_ENTRY(8541, 8541_E),
CPU_TYPE_ENTRY(8543, 8543),
CPU_TYPE_ENTRY(8543, 8543_E),
CPU_TYPE_ENTRY(8544, 8544),
CPU_TYPE_ENTRY(8544, 8544_E),
CPU_TYPE_ENTRY(8545, 8545),
CPU_TYPE_ENTRY(8545, 8545_E),
CPU_TYPE_ENTRY(8547, 8547_E),
CPU_TYPE_ENTRY(8548, 8548),
CPU_TYPE_ENTRY(8548, 8548_E),
CPU_TYPE_ENTRY(8555, 8555),
CPU_TYPE_ENTRY(8555, 8555_E),
CPU_TYPE_ENTRY(8560, 8560),
CPU_TYPE_ENTRY(8567, 8567),
CPU_TYPE_ENTRY(8567, 8567_E),
CPU_TYPE_ENTRY(8568, 8568),
CPU_TYPE_ENTRY(8568, 8568_E),
CPU_TYPE_ENTRY(8569, 8569),
CPU_TYPE_ENTRY(8569, 8569_E),
CPU_TYPE_ENTRY(8572, 8572),
CPU_TYPE_ENTRY(8572, 8572_E),
CPU_TYPE_ENTRY(P2020, P2020),
CPU_TYPE_ENTRY(P2020, P2020_E),
CPU_TYPE_ENTRY(8533, 8533, 1),
CPU_TYPE_ENTRY(8533, 8533_E, 1),
CPU_TYPE_ENTRY(8535, 8535, 1),
CPU_TYPE_ENTRY(8535, 8535_E, 1),
CPU_TYPE_ENTRY(8536, 8536, 1),
CPU_TYPE_ENTRY(8536, 8536_E, 1),
CPU_TYPE_ENTRY(8540, 8540, 1),
CPU_TYPE_ENTRY(8541, 8541, 1),
CPU_TYPE_ENTRY(8541, 8541_E, 1),
CPU_TYPE_ENTRY(8543, 8543, 1),
CPU_TYPE_ENTRY(8543, 8543_E, 1),
CPU_TYPE_ENTRY(8544, 8544, 1),
CPU_TYPE_ENTRY(8544, 8544_E, 1),
CPU_TYPE_ENTRY(8545, 8545, 1),
CPU_TYPE_ENTRY(8545, 8545_E, 1),
CPU_TYPE_ENTRY(8547, 8547_E, 1),
CPU_TYPE_ENTRY(8548, 8548, 1),
CPU_TYPE_ENTRY(8548, 8548_E, 1),
CPU_TYPE_ENTRY(8555, 8555, 1),
CPU_TYPE_ENTRY(8555, 8555_E, 1),
CPU_TYPE_ENTRY(8560, 8560, 1),
CPU_TYPE_ENTRY(8567, 8567, 1),
CPU_TYPE_ENTRY(8567, 8567_E, 1),
CPU_TYPE_ENTRY(8568, 8568, 1),
CPU_TYPE_ENTRY(8568, 8568_E, 1),
CPU_TYPE_ENTRY(8569, 8569, 1),
CPU_TYPE_ENTRY(8569, 8569_E, 1),
CPU_TYPE_ENTRY(8572, 8572, 2),
CPU_TYPE_ENTRY(8572, 8572_E, 2),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610),
CPU_TYPE_ENTRY(8641, 8641),
CPU_TYPE_ENTRY(8641D, 8641D),
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
CPU_TYPE_ENTRY(8641D, 8641D, 2),
#endif
};
@ -84,6 +84,31 @@ struct cpu_type *identify_cpu(u32 ver)
return NULL;
}
int cpu_numcores() {
struct cpu_type *cpu;
cpu = gd->cpu;
return cpu->num_cores;
}
int probecpu (void)
{
uint svr;
uint ver;
svr = get_svr();
ver = SVR_SOC_VER(svr);
gd->cpu = identify_cpu(ver);
#ifndef CONFIG_MP
if (cpu_numcores() > 1) {
puts("Unicore software on multiprocessor system!!\n"
"To enable mutlticore build define CONFIG_MP\n");
}
#endif
return 0;
}
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()

7
include/asm-ppc/config.h
View File

@ -38,4 +38,11 @@
#endif
#endif
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) \
|| defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2
#else
#define CONFIG_MAX_CPUS 1
#endif
#endif /* _ASM_CONFIG_H_ */

1
include/asm-ppc/global_data.h
View File

@ -91,6 +91,7 @@ typedef struct global_data {
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 lbc_clk;
void *cpu;
#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 i2c1_clk;

5
include/asm-ppc/processor.h
View File

@ -1065,13 +1065,14 @@ n:
struct cpu_type {
char name[15];
u32 soc_ver;
u32 num_cores;
};
struct cpu_type *identify_cpu(u32 ver);
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define CPU_TYPE_ENTRY(n, v) \
{ .name = #n, .soc_ver = SVR_##v, }
#define CPU_TYPE_ENTRY(n, v, nc) \
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), }
#else
#if defined(CONFIG_MPC83xx)
#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}

2
include/common.h
View File

@ -441,6 +441,8 @@ void ppcDWstore(unsigned int *addr, unsigned int *value);
#endif
/* $(CPU)/cpu.c */
int cpu_numcores (void);
int probecpu (void);
int checkcpu (void);
int checkicache (void);
int checkdcache (void);

1
include/configs/MPC8572DS.h
View File

@ -34,7 +34,6 @@
#define CONFIG_MPC8572 1
#define CONFIG_MPC8572DS 1
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */

1
include/configs/MPC8610HPCD.h
View File

@ -17,7 +17,6 @@
#define CONFIG_MPC86xx 1 /* MPC86xx */
#define CONFIG_MPC8610 1 /* MPC8610 specific */
#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */

1
include/configs/MPC8641HPCN.h
View File

@ -37,7 +37,6 @@
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
#define CONFIG_ADDR_MAP 1 /* Use addr map */

1
include/configs/P2020DS.h
View File

@ -34,7 +34,6 @@
#define CONFIG_P2020 1
#define CONFIG_P2020DS 1
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */

1
include/configs/XPEDITE5170.h
View File

@ -34,7 +34,6 @@
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */

1
include/configs/XPEDITE5370.h
View File

@ -36,7 +36,6 @@
#define CONFIG_MPC8572 1
#define CONFIG_XPEDITE5370 1
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
#define CONFIG_NUM_CPUS 2 /* 2 Cores */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */

1
include/configs/sbc8641d.h
View File

@ -41,7 +41,6 @@
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#ifdef RUN_DIAG

6
include/e500.h
View File

@ -8,13 +8,9 @@
#ifndef __ASSEMBLY__
#ifndef CONFIG_NUM_CPUS
#define CONFIG_NUM_CPUS 1
#endif
typedef struct
{
unsigned long freqProcessor[CONFIG_NUM_CPUS];
unsigned long freqProcessor[CONFIG_MAX_CPUS];
unsigned long freqSystemBus;
unsigned long freqDDRBus;
unsigned long freqLocalBus;

3
lib_ppc/board.c
View File

@ -291,6 +291,9 @@ init_fnc_t *init_sequence[] = {
board_early_init_f,
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
probecpu,
#endif
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
get_clocks, /* get CPU and bus clocks (etc.) */
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \

2
lib_ppc/bootm.c
View File

@ -172,7 +172,7 @@ void arch_lmb_reserve(struct lmb *lmb)
static void boot_prep_linux(void)
{
#if (CONFIG_NUM_CPUS > 1)
#ifdef CONFIG_MP
/* if we are MP make sure to flush the dcache() to any changes are made
* visibile to all other cores */
flush_dcache();