Cache update and added CFG_UNIFY_CACHE
Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only. Signed-off-by: TsiChung <tcliew@Goku.(none)>
This commit is contained in:
TsiChung
John Rigby
parent
52b017604a
commit
0dca874db6
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@ -113,6 +113,8 @@ void cpu_init_f(void)
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fbcs->cscr5 = CFG_CS5_CTRL;
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fbcs->csmr5 = CFG_CS5_MASK;
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#endif
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icache_enable();
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}
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/*
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@ -120,6 +122,5 @@ void cpu_init_f(void)
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*/
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int cpu_init_r(void)
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{
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icache_enable();
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return (0);
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}
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@ -270,8 +270,6 @@ icache_enable:
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movec %d0, %CACR /* Invalidate cache */
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move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
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movec %d0, %ACR0 /* Enable cache */
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move.l #(CFG_CS0_BASE + 0x0000), %d0 /* Setup cache mask */
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movec %d0, %ACR1 /* Enable cache */
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move.l #0x80000200, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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@ -284,11 +282,11 @@ icache_enable:
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.globl icache_disable
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icache_disable:
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move.l #0x00000100, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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move.l #0x01000000, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Disable cache */
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clr.l %d0 /* Setup cache mask */
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movec %d0, %ACR0 /* Enable cache */
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movec %d0, %ACR1 /* Enable cache */
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movec %d0, %ACR0
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movec %d0, %ACR1
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move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
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moveq #0, %d0
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@ -303,7 +301,7 @@ icache_status:
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.globl icache_invalid
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icache_invalid:
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move.l #0x01000000, %d0 /* Setup cache mask */
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move.l #0x81000200, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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rts
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@ -150,23 +150,15 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
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* Wait for ready
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*/
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j = 0;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
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(j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("TX not ready\n");
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}
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
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info->txbd[info->txIdx].cbd_datlen = length;
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info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
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@ -174,21 +166,19 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
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/* Activate transmit Buffer Descriptor polling */
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fecp->tdar = 0x01000000; /* Descriptor polling active */
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j = 0;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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#ifdef CFG_UNIFY_CACHE
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icache_invalid();
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#endif
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j = 0;
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while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
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(j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("TX timeout\n");
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}
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#ifdef ET_DEBUG
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printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
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__FILE__, __LINE__, __FUNCTION__, j,
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@ -196,10 +186,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
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(info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
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#endif
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/* return only status bits */ ;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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/* return only status bits */
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rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
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info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
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@ -213,6 +200,9 @@ int fec_recv(struct eth_device *dev)
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int length;
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for (;;) {
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#ifdef CFG_UNIFY_CACHE
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icache_invalid();
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#endif
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/* section 16.9.23.2 */
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if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
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length = -1;
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@ -47,18 +47,20 @@
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#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_CACHE | \
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CFG_CMD_DATE | \
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CFG_CMD_ELF | \
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CFG_CMD_FLASH | \
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(CFG_CMD_LOADB | CFG_CMD_LOADS) | \
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CFG_CMD_MEMORY | \
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CFG_CMD_MISC | \
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO \
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)
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CFG_CMD_CACHE | \
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CFG_CMD_DATE | \
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CFG_CMD_ELF | \
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CFG_CMD_FLASH | \
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(CFG_CMD_LOADB | CFG_CMD_LOADS) | \
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CFG_CMD_MEMORY | \
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CFG_CMD_MISC | \
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO \
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)
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#define CFG_UNIFY_CACHE
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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