85xx: Convert MPC8541/MPC8555/MPC8548 CDS to new TLB setup
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
219a81b98d
commit
0db37dc2ee
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@ -29,14 +29,12 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o law.o \
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COBJS := $(BOARD).o law.o tlb.o \
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../common/cadmus.o \
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../common/eeprom.o \
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../common/ft_board.o \
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../common/via.o
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SOBJS := init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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@ -1,192 +0,0 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright 2002,2003, Motorola Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc85xx.h>
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/*
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* TLB0 and TLB1 Entries
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*
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* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
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* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
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* these TLB entries are established.
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*
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* The TLB entries for DDR are dynamically setup in spd_sdram()
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* and use TLB1 Entries 8 through 15 as needed according to the
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* size of DDR memory.
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*
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* MAS0: tlbsel, esel, nv
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* MAS1: valid, iprot, tid, ts, tsize
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* MAS2: epn, x0, x1, w, i, m, g, e
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* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
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*/
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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.section .bootpg, "ax"
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.globl tlb1_entry
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tlb1_entry:
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entry_start
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/*
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* Number of TLB0 and TLB1 entries in the following table
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*/
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.long 13
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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/*
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* TLB0 4K Non-cacheable, guarded
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* 0xff700000 4K Initial CCSRBAR mapping
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*
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* This ends up at a TLB0 Index==0 entry, and must not collide
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* with other TLB0 Entries.
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*/
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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#else
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#error("Update the number of table entries in tlb1_entry")
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#endif
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/*
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* TLB0 16K Cacheable, non-guarded
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* 0xd001_0000 16K Temporary Global data for initialization
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*
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* Use four 4K TLB0 entries. These entries must be cacheable
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* as they provide the bootstrap memory before the memory
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* controler and real memory have been configured.
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*
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* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
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* and must not collide with other TLB0 entries.
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*/
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 0: 16M Non-cacheable, guarded
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* 0xff000000 16M FLASH
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* Out of reset this entry is only 4K.
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*/
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.long FSL_BOOKE_MAS0(1, 0, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
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.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 1: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM First half
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*/
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.long FSL_BOOKE_MAS0(1, 1, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 2: 256M Non-cacheable, guarded
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* 0x90000000 256M PCI1 MEM Second half
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*/
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.long FSL_BOOKE_MAS0(1, 2, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 3: 256M Non-cacheable, guarded
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* 0xa0000000 256M PCI2 MEM First half
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*/
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.long FSL_BOOKE_MAS0(1, 3, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 4: 256M Non-cacheable, guarded
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* 0xb0000000 256M PCI2 MEM Second half
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*/
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.long FSL_BOOKE_MAS0(1, 4, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 5: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe200_0000 16M PCI1 IO
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* 0xe300_0000 16M PCI2 IO
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*/
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.long FSL_BOOKE_MAS0(1, 5, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 6: 64M Cacheable, non-guarded
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* 0xf000_0000 64M LBC SDRAM
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*/
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.long FSL_BOOKE_MAS0(1, 6, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
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.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 7: 1M Non-cacheable, guarded
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* 0xf8000000 1M CADMUS registers
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*/
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.long FSL_BOOKE_MAS0(1, 7, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
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.long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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entry_end
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@ -0,0 +1,112 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/*
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* TLB 0: 16M Non-cacheable, guarded
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* 0xff000000 16M FLASH
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_16M, 1),
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/*
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* TLB 1: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM First half
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*/
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SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 2: 256M Non-cacheable, guarded
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* 0x90000000 256M PCI1 MEM Second half
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*/
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SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 3: 256M Non-cacheable, guarded
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* 0xa0000000 256M PCI2 MEM First half
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*/
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SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 4: 256M Non-cacheable, guarded
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* 0xb0000000 256M PCI2 MEM Second half
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*/
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SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 5: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe200_0000 16M PCI1 IO
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* 0xe300_0000 16M PCI2 IO
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*/
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SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 6: 64M Cacheable, non-guarded
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* 0xf000_0000 64M LBC SDRAM
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*/
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SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 6, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 7: 1M Non-cacheable, guarded
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* 0xf8000000 1M CADMUS registers
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*/
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SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_1M, 1),
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -34,7 +34,6 @@ SECTIONS
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.bootpg 0xFFFFF000 :
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{
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cpu/mpc85xx/start.o (.bootpg)
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board/freescale/mpc8541cds/init.o (.bootpg)
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} = 0xffff
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/* Read-only sections, merged into text segment: */
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@ -64,7 +63,6 @@ SECTIONS
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.text :
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{
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cpu/mpc85xx/start.o (.text)
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board/freescale/mpc8541cds/init.o (.text)
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cpu/mpc85xx/traps.o (.text)
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cpu/mpc85xx/interrupts.o (.text)
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cpu/mpc85xx/cpu_init.o (.text)
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|
|
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@ -29,14 +29,12 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o law.o \
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COBJS := $(BOARD).o law.o tlb.o \
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../common/cadmus.o \
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../common/eeprom.o \
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../common/ft_board.o \
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../common/via.o
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SOBJS := init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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|
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@ -1,184 +0,0 @@
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/*
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* Copyright 2004, 2007 Freescale Semiconductor.
|
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* Copyright 2002,2003, Motorola Inc.
|
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*
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||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
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|
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <mpc85xx.h>
|
||||
|
||||
/*
|
||||
* TLB0 and TLB1 Entries
|
||||
*
|
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
|
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
|
||||
* these TLB entries are established.
|
||||
*
|
||||
* The TLB entries for DDR are dynamically setup in spd_sdram()
|
||||
* and use TLB1 Entries 8 through 15 as needed according to the
|
||||
* size of DDR memory.
|
||||
*
|
||||
* MAS0: tlbsel, esel, nv
|
||||
* MAS1: valid, iprot, tid, ts, tsize
|
||||
* MAS2: epn, x0, x1, w, i, m, g, e
|
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
|
||||
*/
|
||||
|
||||
#define entry_start \
|
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax"
|
||||
.globl tlb1_entry
|
||||
tlb1_entry:
|
||||
entry_start
|
||||
|
||||
/*
|
||||
* Number of TLB0 and TLB1 entries in the following table
|
||||
*/
|
||||
.long (2f-1f)/16
|
||||
|
||||
1:
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
|
||||
/*
|
||||
* TLB0 4K Non-cacheable, guarded
|
||||
* 0xff700000 4K Initial CCSRBAR mapping
|
||||
*
|
||||
* This ends up at a TLB0 Index==0 entry, and must not collide
|
||||
* with other TLB0 Entries.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
#else
|
||||
#error("Update the number of table entries in tlb1_entry")
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TLB0 16K Cacheable, guarded
|
||||
* Temporary Global data for initialization
|
||||
*
|
||||
* Use four 4K TLB0 entries. These entries must be cacheable
|
||||
* as they provide the bootstrap memory before the memory
|
||||
* controler and real memory have been configured.
|
||||
*
|
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
|
||||
* and must not collide with other TLB0 entries.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded
|
||||
* 0xff000000 16M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
|
||||
.long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 1: 1G Non-cacheable, guarded
|
||||
* 0x80000000 1G PCI1/PCIE 8,9,a,b
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 1, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
|
||||
.long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
#ifdef CFG_RIO_MEM_PHYS
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 2, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 3, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
#endif
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 1M PCI1 IO
|
||||
* 0xe210_0000 1M PCI2 IO
|
||||
* 0xe300_0000 1M PCIe IO
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 5, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded
|
||||
* 0xf000_0000 64M LBC SDRAM
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 6, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
|
||||
.long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 7: 64M Non-cacheable, guarded
|
||||
* 0xf8000000 64M CADMUS registers, relocated L2SRAM
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 7, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
2:
|
||||
entry_end
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded
|
||||
* 0xff000000 16M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/*
|
||||
* TLB 1: 1G Non-cacheable, guarded
|
||||
* 0x80000000 1G PCI1/PCIE 8,9,a,b
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
#ifdef CFG_RIO_MEM_PHYS
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
||||
#endif
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 1M PCI1 IO
|
||||
* 0xe210_0000 1M PCI2 IO
|
||||
* 0xe300_0000 1M PCIe IO
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded
|
||||
* 0xf000_0000 64M LBC SDRAM
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 6, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 7: 64M Non-cacheable, guarded
|
||||
* 0xf8000000 64M CADMUS registers, relocated L2SRAM
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_64M, 1),
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -34,7 +34,6 @@ SECTIONS
|
|||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.bootpg)
|
||||
board/freescale/mpc8548cds/init.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
|
|
@ -64,7 +63,6 @@ SECTIONS
|
|||
.text :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.text)
|
||||
board/freescale/mpc8548cds/init.o (.text)
|
||||
cpu/mpc85xx/traps.o (.text)
|
||||
cpu/mpc85xx/interrupts.o (.text)
|
||||
cpu/mpc85xx/cpu_init.o (.text)
|
||||
|
|
|
|||
|
|
@ -29,14 +29,12 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o law.o \
|
||||
COBJS := $(BOARD).o law.o tlb.o \
|
||||
../common/cadmus.o \
|
||||
../common/eeprom.o \
|
||||
../common/ft_board.o \
|
||||
../common/via.o
|
||||
|
||||
SOBJS := init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
|
|
|||
|
|
@ -1,192 +0,0 @@
|
|||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Copyright 2002,2003, Motorola Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <mpc85xx.h>
|
||||
|
||||
|
||||
/*
|
||||
* TLB0 and TLB1 Entries
|
||||
*
|
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
|
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
|
||||
* these TLB entries are established.
|
||||
*
|
||||
* The TLB entries for DDR are dynamically setup in spd_sdram()
|
||||
* and use TLB1 Entries 8 through 15 as needed according to the
|
||||
* size of DDR memory.
|
||||
*
|
||||
* MAS0: tlbsel, esel, nv
|
||||
* MAS1: valid, iprot, tid, ts, tsize
|
||||
* MAS2: epn, x0, x1, w, i, m, g, e
|
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
|
||||
*/
|
||||
|
||||
#define entry_start \
|
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax"
|
||||
.globl tlb1_entry
|
||||
tlb1_entry:
|
||||
entry_start
|
||||
|
||||
/*
|
||||
* Number of TLB0 and TLB1 entries in the following table
|
||||
*/
|
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
|
||||
/*
|
||||
* TLB0 4K Non-cacheable, guarded
|
||||
* 0xff700000 4K Initial CCSRBAR mapping
|
||||
*
|
||||
* This ends up at a TLB0 Index==0 entry, and must not collide
|
||||
* with other TLB0 Entries.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
#else
|
||||
#error("Update the number of table entries in tlb1_entry")
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TLB0 16K Cacheable, non-guarded
|
||||
* 0xd001_0000 16K Temporary Global data for initialization
|
||||
*
|
||||
* Use four 4K TLB0 entries. These entries must be cacheable
|
||||
* as they provide the bootstrap memory before the memory
|
||||
* controler and real memory have been configured.
|
||||
*
|
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
|
||||
* and must not collide with other TLB0 entries.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded
|
||||
* 0xff000000 16M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
|
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded
|
||||
* 0x80000000 256M PCI1 MEM First half
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 1, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
* 0x90000000 256M PCI1 MEM Second half
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 2, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded
|
||||
* 0xa0000000 256M PCI2 MEM First half
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 3, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded
|
||||
* 0xb0000000 256M PCI2 MEM Second half
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 4, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 16M PCI1 IO
|
||||
* 0xe300_0000 16M PCI2 IO
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 5, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded
|
||||
* 0xf000_0000 64M LBC SDRAM
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 6, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
|
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 7: 1M Non-cacheable, guarded
|
||||
* 0xf8000000 1M CADMUS registers
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 7, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
|
||||
.long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
entry_end
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded
|
||||
* 0xff000000 16M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded
|
||||
* 0x80000000 256M PCI1 MEM First half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
* 0x90000000 256M PCI1 MEM Second half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded
|
||||
* 0xa0000000 256M PCI2 MEM First half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded
|
||||
* 0xb0000000 256M PCI2 MEM Second half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 16M PCI1 IO
|
||||
* 0xe300_0000 16M PCI2 IO
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded
|
||||
* 0xf000_0000 64M LBC SDRAM
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 6, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 7: 1M Non-cacheable, guarded
|
||||
* 0xf8000000 1M CADMUS registers
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_1M, 1),
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -34,7 +34,6 @@ SECTIONS
|
|||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.bootpg)
|
||||
board/freescale/mpc8555cds/init.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
|
|
@ -64,7 +63,6 @@ SECTIONS
|
|||
.text :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.text)
|
||||
board/freescale/mpc8555cds/init.o (.text)
|
||||
cpu/mpc85xx/traps.o (.text)
|
||||
cpu/mpc85xx/interrupts.o (.text)
|
||||
cpu/mpc85xx/cpu_init.o (.text)
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@
|
|||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* When initializing flash, if we cannot find the manufacturer ID,
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@
|
|||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
|
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* When initializing flash, if we cannot find the manufacturer ID,
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@
|
|||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* When initializing flash, if we cannot find the manufacturer ID,
|
||||
|
|
|
|||
Loading…
Reference in New Issue