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[PATCH] Add 4xx GPIO functions 

This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-03-24 15:57:09 +01:00
parent 2db633658b
commit 0d974d5297
7 changed files with 61 additions and 147 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
board/amcc/bamboo/bamboo.c
View File

@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <spd_sdram.h>
#include <ppc440.h>
#include "bamboo.h"

10
board/amcc/bamboo/bamboo.h
View File

@ -264,19 +264,9 @@
#define TRUE 1
#define FALSE 0
#define GPIO_GROUP_MAX 2
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
/* For the other GPIO number, you must shift */
#define GPIO0 0
#define GPIO1 1
/*#define MAX_SELECTION_NB CORE_NB */
#define MAX_CORE_SELECT_NB 22

1
board/amcc/katmai/katmai.c
View File

@ -27,6 +27,7 @@
#include <asm/processor.h>
#include <i2c.h>
#include <asm-ppc/io.h>
#include <asm-ppc/gpio.h>
#include "../cpu/ppc4xx/440spe_pcie.h"

2
cpu/ppc4xx/Makefile
View File

@ -29,7 +29,7 @@ START = start.o resetvec.o kgdb.o
SOBJS = dcr.o
COBJS = 405gp_pci.o 4xx_enet.o \
bedbug_405.o commproc.o \
cpu.o cpu_init.o i2c.o interrupts.o \
cpu.o cpu_init.o gpio.o i2c.o interrupts.o \
miiphy.o ndfc.o sdram.o serial.o \
40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \
tlb.o traps.o usb_ohci.o usbdev.o \

115
cpu/ppc4xx/cpu_init.c
View File

@ -25,6 +25,7 @@
#include <watchdog.h>
#include <ppc4xx_enet.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <ppc4xx.h>
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
@ -98,118 +99,6 @@ DECLARE_GLOBAL_DATA_PTR;
# endif
#endif /* CFG_INIT_DCACHE_CS */
#if defined(CFG_440_GPIO_TABLE)
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
{
unsigned char i=0, j=0, reg_offset = 0, gpio_core;
unsigned long gpio_reg, gpio_core_add;
for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
j = 0;
reg_offset = 0;
/* GPIO config of the GPIOs 0 to 31 */
for (i=0; i<GPIO_MAX; i++, j++) {
if (i == GPIO_MAX/2) {
reg_offset = 4;
j = i-16;
}
gpio_core_add = (*gpio_tab)[gpio_core][i].add;
if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
switch ((*gpio_tab)[gpio_core][i].alt_nb) {
case GPIO_SEL:
break;
case GPIO_ALT1:
gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
break;
case GPIO_ALT2:
gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
break;
case GPIO_ALT3:
gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
break;
}
}
if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
switch ((*gpio_tab)[gpio_core][i].alt_nb) {
case GPIO_SEL:
if (gpio_core == GPIO0) {
gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
out32(GPIO0_TCR, gpio_reg);
}
if (gpio_core == GPIO1) {
gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
out32(GPIO1_TCR, gpio_reg);
}
gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
break;
case GPIO_ALT1:
gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
break;
case GPIO_ALT2:
gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
break;
case GPIO_ALT3:
gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
& ~(GPIO_MASK >> (j*2));
gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
break;
}
}
}
}
}
#endif /* CFG_440_GPIO_TABLE */
/*
* Breath some life into the CPU...
*
@ -248,7 +137,7 @@ cpu_init_f (void)
#endif /* CONFIG_405EP */
#if defined(CFG_440_GPIO_TABLE)
set_chip_gpio_configuration(&gpio_tab);
gpio_set_chip_configuration();
#endif /* CFG_440_GPIO_TABLE */
/*

56
include/asm-ppc/gpio.h Normal file
View File

@ -0,0 +1,56 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define GPIO_GROUP_MAX 2
#else
#define GPIO_GROUP_MAX 1
#endif
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000
#define GPIO_ALT2_SEL 0x80000000
#define GPIO_ALT3_SEL 0xc0000000
#define GPIO_IN_SEL 0x40000000
#define GPIO_MASK 0xc0000000
#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
#ifndef __ASSEMBLY__
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
typedef struct {
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
} gpio_param_s;
#endif
void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
void gpio_set_chip_configuration(void);

23
include/ppc440.h
View File

@ -3267,29 +3267,6 @@
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#endif
#define GPIO_GROUP_MAX 2
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
/* For the other GPIO number, you must shift */
#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
#ifndef __ASSEMBLY__
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef struct { unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
} gpio_param_s;
#endif /* __ASSEMBLY__ */
/*
* Macros for accessing the indirect EBC registers
*/