Merge branch 'master' of git://git.denx.de/u-boot-imx
Conflicts: board/logicpd/imx31_litekit/config.mk boards.cfg Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
commit
083d506937
|
@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void)
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reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
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MXC_CCM_CACRR_ARM_PODF_OFFSET;
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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return freq / (reg + 1);
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}
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@ -84,14 +84,14 @@ static u32 get_periph_clk(void)
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reg = __raw_readl(&mxc_ccm->cbcdr);
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if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
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return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
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return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
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reg = __raw_readl(&mxc_ccm->cbcmr);
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switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
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MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
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case 0:
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return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
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return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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case 1:
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return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
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return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
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default:
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return 0;
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}
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@ -146,15 +146,15 @@ static u32 get_uart_clk(void)
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MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
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case 0x0:
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freq = decode_pll(mxc_plls[PLL1_CLOCK],
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CONFIG_MX51_HCLK_FREQ);
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CONFIG_SYS_MX5_HCLK);
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break;
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case 0x1:
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freq = decode_pll(mxc_plls[PLL2_CLOCK],
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CONFIG_MX51_HCLK_FREQ);
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CONFIG_SYS_MX5_HCLK);
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break;
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case 0x2:
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freq = decode_pll(mxc_plls[PLL3_CLOCK],
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CONFIG_MX51_HCLK_FREQ);
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CONFIG_SYS_MX5_HCLK);
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break;
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default:
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return 66500000;
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@ -181,7 +181,7 @@ u32 get_lp_apm(void)
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u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
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if (((ccsr >> 9) & 1) == 0)
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ret_val = CONFIG_MX51_HCLK_FREQ;
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ret_val = CONFIG_SYS_MX5_HCLK;
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else
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ret_val = ((32768 * 1024));
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@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void)
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switch (clk_sel) {
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case 0:
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ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
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CONFIG_MX51_HCLK_FREQ) /
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case 1:
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ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
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CONFIG_MX51_HCLK_FREQ) /
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case 2:
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ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
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CONFIG_MX51_HCLK_FREQ) /
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CONFIG_SYS_MX5_HCLK) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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default:
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@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
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return imx_get_cspiclk();
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case MXC_FEC_CLK:
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return decode_pll(mxc_plls[PLL1_CLOCK],
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CONFIG_MX51_HCLK_FREQ);
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CONFIG_SYS_MX5_HCLK);
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default:
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break;
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}
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@ -269,16 +269,16 @@ u32 imx_get_fecclk(void)
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/*
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* Dump some core clockes.
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*/
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int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u32 freq;
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
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printf("mx51 pll1: %dMHz\n", freq / 1000000);
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freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
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printf("mx51 pll2: %dMHz\n", freq / 1000000);
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freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
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printf("mx51 pll3: %dMHz\n", freq / 1000000);
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freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
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printf("pll1: %dMHz\n", freq / 1000000);
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freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
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printf("pll2: %dMHz\n", freq / 1000000);
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freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
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printf("pll3: %dMHz\n", freq / 1000000);
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printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
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printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
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@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
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/***************************************************/
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U_BOOT_CMD(
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clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks,
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"display mx51 clocks\n",
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clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
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"display clocks\n",
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""
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);
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@ -23,7 +23,7 @@
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx51_pins.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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@ -257,20 +257,6 @@ lowlevel_init:
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orr r1, r1, #(1 << 23)
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str r1, [r0, #0x4]
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#ifdef ENABLE_IMPRECISE_ABORT
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mrs r1, spsr /* save old spsr */
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mrs r0, cpsr /* read out the cpsr */
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bic r0, r0, #0x100 /* clear the A bit */
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msr spsr, r0 /* update spsr */
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add lr, pc, #0x8 /* update lr */
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movs pc, lr /* update cpsr */
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nop
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nop
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nop
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nop
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msr spsr, r1 /* restore old spsr */
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#endif
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init_l2cc
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init_aips
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@ -33,28 +33,33 @@
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#include <fsl_esdhc.h>
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#endif
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#if defined(CONFIG_MX51)
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#define CPU_TYPE 0x51000
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#else
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#error "CPU_TYPE not defined"
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#endif
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u32 get_cpu_rev(void)
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{
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int reg;
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int system_rev;
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int system_rev = CPU_TYPE;
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int reg = __raw_readl(ROM_SI_REV);
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reg = __raw_readl(ROM_SI_REV);
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switch (reg) {
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case 0x02:
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system_rev = 0x51000 | CHIP_REV_1_1;
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system_rev |= CHIP_REV_1_1;
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break;
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case 0x10:
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if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
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system_rev = 0x51000 | CHIP_REV_2_5;
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system_rev |= CHIP_REV_2_5;
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else
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system_rev = 0x51000 | CHIP_REV_2_0;
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system_rev |= CHIP_REV_2_0;
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break;
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case 0x20:
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system_rev = 0x51000 | CHIP_REV_3_0;
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system_rev |= CHIP_REV_3_0;
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break;
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return system_rev;
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default:
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system_rev = 0x51000 | CHIP_REV_1_0;
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system_rev |= CHIP_REV_1_0;
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break;
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}
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return system_rev;
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@ -67,9 +72,10 @@ int print_cpuinfo(void)
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u32 cpurev;
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cpurev = get_cpu_rev();
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printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n",
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(cpurev & 0xF0) >> 4,
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(cpurev & 0x0F) >> 4,
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printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
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(cpurev & 0xFF000) >> 12,
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(cpurev & 0x000F0) >> 4,
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(cpurev & 0x0000F) >> 0,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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return 0;
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}
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@ -75,18 +75,18 @@ void reset_timer(void)
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void reset_timer_masked(void)
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{
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ulong val = __raw_readl(&cur_gpt->counter);
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lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
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lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
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timestamp = 0;
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}
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ulong get_timer_masked(void)
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{
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ulong val = __raw_readl(&cur_gpt->counter);
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val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
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val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
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if (val >= lastinc)
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timestamp += (val - lastinc);
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else
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timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
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timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
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- lastinc) + val;
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lastinc = val;
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return timestamp;
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@ -106,7 +106,7 @@ void set_timer(ulong t)
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void __udelay(unsigned long usec)
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{
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unsigned long now, start, tmo;
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tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
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tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
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if (!tmo)
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tmo = 1;
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@ -20,13 +20,13 @@
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* MA 02111-1307 USA
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*/
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#ifndef __MACH_MX51_IOMUX_H__
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#define __MACH_MX51_IOMUX_H__
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#ifndef __MACH_MX5_IOMUX_H__
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#define __MACH_MX5_IOMUX_H__
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx51_pins.h>
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#include <asm/arch/mx5x_pins.h>
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typedef unsigned int iomux_pin_name_t;
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|
@ -190,4 +190,4 @@ void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
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unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
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void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
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#endif /* __MACH_MX51_IOMUX_H__ */
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#endif /* __MACH_MX5_IOMUX_H__ */
|
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@ -20,8 +20,8 @@
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
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#define __ASM_ARCH_MXC_MX51_PINS_H__
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#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
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#define __ASM_ARCH_MX5_MX5X_PINS_H__
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|
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#ifndef __ASSEMBLY__
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|
@ -415,4 +415,4 @@ enum iomux_pins {
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};
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|
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
|
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#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
|
|
@ -23,7 +23,7 @@
|
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#include <common.h>
|
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#include <asm/io.h>
|
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#include <asm/arch/imx-regs.h>
|
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#include <asm/arch/mx51_pins.h>
|
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#include <asm/arch/mx5x_pins.h>
|
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#include <asm/arch/iomux.h>
|
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#include <asm/errno.h>
|
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#include <asm/arch/sys_proto.h>
|
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|
|
|
@ -1 +1 @@
|
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CONFIG_SYS_TEXT_BASE = 0x87f00000
|
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CONFIG_SYS_TEXT_BASE = 0xa0000000
|
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|
|
|
@ -31,12 +31,18 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
int dram_init (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
dram_init_banksize (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
}
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx51_pins.h>
|
||||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <mxc_gpio.h>
|
||||
|
|
|
@ -46,8 +46,8 @@ pm9263 arm arm926ejs - ronetix at91
|
|||
suen3 arm arm926ejs km_arm keymile kirkwood
|
||||
rd6281a arm arm926ejs - Marvell kirkwood
|
||||
jadecpu arm arm926ejs jadecpu syteco mb86r0x
|
||||
mx51evk arm armv7 mx51evk freescale mx51
|
||||
vision2 arm armv7 vision2 ttcontrol mx51
|
||||
mx51evk arm armv7 mx51evk freescale mx5
|
||||
vision2 arm armv7 vision2 ttcontrol mx5
|
||||
actux1 arm ixp
|
||||
actux2 arm ixp
|
||||
actux3 arm ixp
|
||||
|
|
|
@ -117,6 +117,8 @@ int ehci_hcd_init(void)
|
|||
|
||||
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -147,6 +147,13 @@
|
|||
#define PHYS_SDRAM_1 CSD0_BASE
|
||||
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
|
||||
|
||||
#undef CONFIG_SYS_ARM_WITHOUT_RELOC
|
||||
#define CONFIG_SYS_SDRAM_BASE CSD0_BASE
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_END IRAM_SIZE
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
|
|
@ -30,8 +30,8 @@
|
|||
#define CONFIG_MX51 /* in a mx51 */
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
|
||||
#define CONFIG_MX51_CLK32 32768
|
||||
#define CONFIG_SYS_MX5_HCLK 24000000
|
||||
#define CONFIG_SYS_MX5_CLK32 32768
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
|
|
|
@ -102,6 +102,7 @@
|
|||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#endif /* CONFIG_CMD_USB */
|
||||
|
||||
|
@ -124,25 +125,16 @@
|
|||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_DATE
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
/*
|
||||
* You can compile in a MAC address and your custom net settings by using
|
||||
* the following syntax.
|
||||
*
|
||||
* #define CONFIG_ETHADDR xx:xx:xx:xx:xx:xx
|
||||
* #define CONFIG_SERVERIP <server ip>
|
||||
* #define CONFIG_IPADDR <board ip>
|
||||
* #define CONFIG_GATEWAYIP <gateway ip>
|
||||
* #define CONFIG_NETMASK <your netmask>
|
||||
*/
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
|
@ -164,7 +156,7 @@
|
|||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs}\0" \
|
||||
"uboot_addr=A0000000\0" \
|
||||
"kernel_addr=A00A0000\0" \
|
||||
"kernel_addr=A00C0000\0" \
|
||||
"ramdisk_addr=A0300000\0" \
|
||||
"u-boot=qong/u-boot.bin\0" \
|
||||
"kernel_addr_r=80800000\0" \
|
||||
|
@ -296,10 +288,14 @@ extern int qong_nand_rdy(void *chip);
|
|||
#define CONFIG_LZO
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define CONFIG_FLASH_CFI_MTD
|
||||
#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
|
||||
#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
|
||||
"nand0=gen_nand"
|
||||
#define MTDPARTS_DEFAULT \
|
||||
"mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \
|
||||
"128k(env2),2432k(kernel),13m(ramdisk),-(user)"
|
||||
"mtdparts=physmap-flash.0:" \
|
||||
"512k(U-Boot),128k(env1),128k(env2)," \
|
||||
"2304k(kernel),13m(ramdisk),-(user);" \
|
||||
"gen_nand:" \
|
||||
"128m(nand)"
|
||||
|
||||
/* additions for new relocation code, must be added to all boards */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
|
|
|
@ -29,8 +29,8 @@
|
|||
#define CONFIG_MX51 /* in a mx51 */
|
||||
#define CONFIG_L2_OFF
|
||||
|
||||
#define CONFIG_MX51_HCLK_FREQ 24000000
|
||||
#define CONFIG_MX51_CLK32 32768
|
||||
#define CONFIG_SYS_MX5_HCLK 24000000
|
||||
#define CONFIG_SYS_MX5_CLK32 32768
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
|
|
Loading…
Reference in New Issue