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* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200 

Patch by Anders Larsen, 29 Apr 2005

* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005
  (8e2be51de8)
This commit is contained in:
Wolfgang Denk 2005-10-05 01:51:29 +02:00
parent 29ca46c445
commit 080bdb7f3a
20 changed files with 160 additions and 575 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
CHANGELOG
View File

@ -2,6 +2,12 @@
Changes for U-Boot 1.1.4:
======================================================================
* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005
(8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5)
* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200
Patch by Anders Larsen, 29 Apr 2005
* Fix device partition intialization for SystemACE disks.
Patch by Stephen Williams, 28 Apr 2005

2
board/at91rm9200dk/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := at91rm9200dk.o at45.o dm9161.o flash.o
OBJS := at91rm9200dk.o at45.o flash.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)

26
board/at91rm9200dk/at91rm9200dk.c
View File

@ -24,6 +24,8 @@
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <dm9161.h>
/* ------------------------------------------------------------------------- */
/*
@ -61,6 +63,30 @@ int dram_init (void)
return 0;
}
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */
/*
* Disk On Chip (NAND) Millenium initialization.
* The NAND lives in the CS2* space

2
board/cmc_pu2/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := cmc_pu2.o at45.o dm9161.o flash.o load_sernum_ethaddr.o
OBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)

26
board/cmc_pu2/cmc_pu2.c
View File

@ -30,6 +30,8 @@
#include <common.h>
#include <asm/mach-types.h>
#include <asm/arch/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <dm9161.h>
/* ------------------------------------------------------------------------- */
/*
@ -152,3 +154,27 @@ int hw_detect (void)
return ((pio->PIO_PDSR & AT91C_PIO_PB13)
? CMC_HP_BASIC : CMC_BASIC);
}
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

243
board/cmc_pu2/dm9161.c
View File

@ -1,243 +0,0 @@
/*
* (C) Copyright 2003
* Author : Hamid Ikdoumi (Atmel)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <at91rm9200_net.h>
#include <net.h>
#include <dm9161.h>
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/*
* Name:
* dm9161_IsPhyConnected
* Description:
* Reads the 2 PHY ID registers
* Arguments:
* p_mac - pointer to AT91S_EMAC struct
* Return value:
* TRUE - if id read successfully
* FALSE- if error
*/
static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
at91rm9200_EmacDisableMDIO (p_mac);
if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
return TRUE;
return FALSE;
}
/*
* Name:
* dm9161_GetLinkSpeed
* Description:
* Link parallel detection status of MAC is checked and set in the
* MAC configuration registers
* Arguments:
* p_mac - pointer to MAC
* Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
{
unsigned short stat1, stat2;
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
return FALSE;
if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
return FALSE;
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
return FALSE;
if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
/*set Emac for 100BaseTX and Full Duplex */
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
return TRUE;
}
if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
/*set MII for 10BaseT and Full Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_FD;
return TRUE;
}
if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
/*set MII for 100BaseTX and Half Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_SPD;
return TRUE;
}
if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
/*set MII for 10BaseT and Half Duplex */
p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
return TRUE;
}
return FALSE;
}
/*
* Name:
* dm9161_InitPhy
* Description:
* MAC starts checking its link by using parallel detection and
* Autonegotiation and the same is set in the MAC configuration registers
* Arguments:
* p_mac - pointer to struct AT91S_EMAC
* Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
{
UCHAR ret = TRUE;
unsigned short IntValue;
at91rm9200_EmacEnableMDIO (p_mac);
if (!dm9161_GetLinkSpeed (p_mac)) {
/* Try another time */
ret = dm9161_GetLinkSpeed (p_mac);
}
/* Disable PHY Interrupts */
at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
/* clear FDX, SPD, Link, INTR masks */
IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
DM9161_LINK_MASK | DM9161_INTR_MASK);
at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
at91rm9200_EmacDisableMDIO (p_mac);
return (ret);
}
/*
* Name:
* dm9161_AutoNegotiate
* Description:
* MAC Autonegotiates with the partner status of same is set in the
* MAC configuration registers
* Arguments:
* dev - pointer to struct net_device
* Return value:
* TRUE - if link status set successfully
* FALSE - if link status not set
*/
static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
{
unsigned short value;
unsigned short PhyAnar;
unsigned short PhyAnalpar;
/* Set dm9161 control register */
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
return FALSE;
value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
value |= DM9161_ISOLATE; /* Electrically isolate PHY */
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
return FALSE;
/* Set the Auto_negotiation Advertisement Register */
/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
return FALSE;
/* Read the Control Register */
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
return FALSE;
value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
return FALSE;
/* Restart Auto_negotiation */
value |= DM9161_RESTART_AUTONEG;
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
return FALSE;
/*check AutoNegotiate complete */
udelay (10000);
at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
if (!(value & DM9161_AUTONEG_COMP))
return FALSE;
/* Get the AutoNeg Link partner base page */
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
return FALSE;
if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
/*set MII for 100BaseTX and Full Duplex */
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
return TRUE;
}
if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
/*set MII for 10BaseT and Full Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_FD;
return TRUE;
}
return FALSE;
}
/*
* Name:
* at91rm92000_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

2
board/kb9202/Makefile
View File

@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := kb9202.o lxt972.o
OBJS := kb9202.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)

33
board/kb9202/kb9202.c
View File

@ -23,11 +23,13 @@
*/
/*
* Adatped for KwikByte KB920x board from at91rm9200dk.c: 22APR2005
* Adapted for KwikByte KB920x board from at91rm9200dk.c: 22APR2005
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <lxt971a.h>
/* ------------------------------------------------------------------------- */
/*
@ -64,3 +66,32 @@ int dram_init (void)
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac);
UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac);
UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac);
UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status);
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = lxt972_InitPhy;
p_phyops->IsPhyConnected = lxt972_IsPhyConnected;
p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed;
p_phyops->AutoNegotiate = lxt972_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

2
board/mp2usb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := mp2usb.o dm9161.o flash.o
OBJS := mp2usb.o flash.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)

243
board/mp2usb/dm9161.c
View File

@ -1,243 +0,0 @@
/*
* (C) Copyright 2003
* Author : Hamid Ikdoumi (Atmel)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <at91rm9200_net.h>
#include <net.h>
#include <dm9161.h>
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/*
* Name:
* dm9161_IsPhyConnected
* Description:
* Reads the 2 PHY ID registers
* Arguments:
* p_mac - pointer to AT91S_EMAC struct
* Return value:
* TRUE - if id read successfully
* FALSE- if error
*/
static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
at91rm9200_EmacDisableMDIO (p_mac);
if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
return TRUE;
return FALSE;
}
/*
* Name:
* dm9161_GetLinkSpeed
* Description:
* Link parallel detection status of MAC is checked and set in the
* MAC configuration registers
* Arguments:
* p_mac - pointer to MAC
* Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
{
unsigned short stat1, stat2;
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
return FALSE;
if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
return FALSE;
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
return FALSE;
if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
/*set Emac for 100BaseTX and Full Duplex */
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
return TRUE;
}
if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
/*set MII for 10BaseT and Full Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_FD;
return TRUE;
}
if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
/*set MII for 100BaseTX and Half Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_SPD;
return TRUE;
}
if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
/*set MII for 10BaseT and Half Duplex */
p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
return TRUE;
}
return FALSE;
}
/*
* Name:
* dm9161_InitPhy
* Description:
* MAC starts checking its link by using parallel detection and
* Autonegotiation and the same is set in the MAC configuration registers
* Arguments:
* p_mac - pointer to struct AT91S_EMAC
* Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
{
UCHAR ret = TRUE;
unsigned short IntValue;
at91rm9200_EmacEnableMDIO (p_mac);
if (!dm9161_GetLinkSpeed (p_mac)) {
/* Try another time */
ret = dm9161_GetLinkSpeed (p_mac);
}
/* Disable PHY Interrupts */
at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
/* clear FDX, SPD, Link, INTR masks */
IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
DM9161_LINK_MASK | DM9161_INTR_MASK);
at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
at91rm9200_EmacDisableMDIO (p_mac);
return (ret);
}
/*
* Name:
* dm9161_AutoNegotiate
* Description:
* MAC Autonegotiates with the partner status of same is set in the
* MAC configuration registers
* Arguments:
* dev - pointer to struct net_device
* Return value:
* TRUE - if link status set successfully
* FALSE - if link status not set
*/
static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
{
unsigned short value;
unsigned short PhyAnar;
unsigned short PhyAnalpar;
/* Set dm9161 control register */
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
return FALSE;
value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
value |= DM9161_ISOLATE; /* Electrically isolate PHY */
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
return FALSE;
/* Set the Auto_negotiation Advertisement Register */
/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
return FALSE;
/* Read the Control Register */
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
return FALSE;
value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
return FALSE;
/* Restart Auto_negotiation */
value |= DM9161_RESTART_AUTONEG;
if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
return FALSE;
/*check AutoNegotiate complete */
udelay (10000);
at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
if (!(value & DM9161_AUTONEG_COMP))
return FALSE;
/* Get the AutoNeg Link partner base page */
if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
return FALSE;
if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
/*set MII for 100BaseTX and Full Duplex */
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
return TRUE;
}
if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
/*set MII for 10BaseT and Full Duplex */
p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
| AT91C_EMAC_FD;
return TRUE;
}
return FALSE;
}
/*
* Name:
* at91rm92000_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

15
board/mp2usb/flash.c
View File

@ -237,7 +237,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
int prot, sect;
ulong type, start, last;
int rcode = 0;
int cflag, iflag;
@ -284,10 +284,8 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
/* Disable interrupts which might cause a timeout here */
/* flag = disable_interrupts (); */
iflag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
@ -314,8 +312,8 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
}
*addr = INTEL_CLEAR; /* clear status register cmd. */
*addr = INTEL_RESET; /* resest to read mode */
*addr = (FPWV)INTEL_CLEAR; /* clear status register cmd. */
*addr = (FPWV)INTEL_RESET; /* resest to read mode */
printf (" done\n");
}
@ -425,7 +423,6 @@ static int write_data (flash_info_t *info, ulong dest, FPW data)
FPWV *addr = (FPWV *) dest;
ulong status;
int cflag, iflag;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@ -441,10 +438,8 @@ static int write_data (flash_info_t *info, ulong dest, FPW data)
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
/* Disable interrupts which might cause a timeout here */
/*flag = disable_interrupts (); */
iflag = disable_interrupts ();
*addr = (FPW) INTEL_PROG; /* write setup */
*addr = data;

26
board/mp2usb/mp2usb.c
View File

@ -27,6 +27,8 @@
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <dm9161.h>
#include <asm/mach-types.h>
/* ------------------------------------------------------------------------- */
@ -60,3 +62,27 @@ int dram_init (void)
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_DRIVER_ETHER
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

2
cpu/arm920t/at91rm9200/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(SOC).a
OBJS = ether.o i2c.o interrupts.o serial.o usb_ohci.o
OBJS = dm9161.o ether.o i2c.o interrupts.o lxt972.o serial.o usb_ohci.o
SOBJS = lowlevel_init.o
all: .depend $(LIB)

27
board/at91rm9200dk/dm9161.c → cpu/arm920t/at91rm9200/dm9161.c
View File

@ -40,7 +40,7 @@
* TRUE - if id read successfully
* FALSE- if error
*/
static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
@ -68,7 +68,7 @@ static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
{
unsigned short stat1, stat2;
@ -124,7 +124,7 @@ static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
{
UCHAR ret = TRUE;
unsigned short IntValue;
@ -160,7 +160,7 @@ static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
* TRUE - if link status set successfully
* FALSE - if link status not set
*/
static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
{
unsigned short value;
unsigned short PhyAnar;
@ -219,25 +219,6 @@ static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
return FALSE;
}
/*
* Name:
* at91rm92000_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

2
cpu/arm920t/at91rm9200/ether.c
View File

@ -217,7 +217,7 @@ int eth_init (bd_t * bd)
p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
at91rm92000_GetPhyInterface (& PhyOps);
at91rm9200_GetPhyInterface (& PhyOps);
if (!PhyOps.IsPhyConnected (p_mac))
printf ("PHY not connected!!\n\r");

30
board/kb9202/lxt972.c → cpu/arm920t/at91rm9200/lxt972.c
View File

@ -23,9 +23,10 @@
*/
/*
* Adatped for KwikByte KB920x board: 22APR2005
* Adapted for KwikByte KB920x board: 22APR2005
*/
#include <common.h>
#include <at91rm9200_net.h>
#include <net.h>
#include <lxt971a.h>
@ -45,7 +46,7 @@
* TRUE - if id read successfully
* FALSE- if error
*/
static unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
@ -72,7 +73,7 @@ static unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
static UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac)
UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac)
{
unsigned short stat1;
@ -131,7 +132,7 @@ static UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac)
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
static UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
{
UCHAR ret = TRUE;
@ -163,7 +164,7 @@ static UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
* TRUE - if link status set successfully
* FALSE - if link status not set
*/
static UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
{
unsigned short value;
@ -185,25 +186,6 @@ static UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
return (lxt972_GetLinkSpeed (p_mac));
}
/*
* Name:
* at91rm92000_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = lxt972_InitPhy;
p_phyops->IsPhyConnected = lxt972_IsPhyConnected;
p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed;
p_phyops->AutoNegotiate = lxt972_AutoNegotiate;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

4
drivers/cfi_flash.c
View File

@ -188,7 +188,9 @@ static ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
ulong tout, char *prompt);
#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
static flash_info_t *flash_get_info(ulong base);
#endif
#ifdef CFG_FLASH_USE_BUFFER_WRITE
static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
#endif
@ -365,6 +367,7 @@ unsigned long flash_init (void)
/*-----------------------------------------------------------------------
*/
#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
static flash_info_t *flash_get_info(ulong base)
{
int i;
@ -379,6 +382,7 @@ static flash_info_t *flash_get_info(ulong base)
return i == CFG_MAX_FLASH_BANKS ? 0 : info;
}
#endif
/*-----------------------------------------------------------------------
*/

34
include/asm-arm/arch-at91rm9200/AT91RM9200.h
View File

@ -43,8 +43,7 @@ typedef struct _AT91S_TC
AT91_REG TC_IER; /* Interrupt Enable Register */
AT91_REG TC_IDR; /* Interrupt Disable Register */
AT91_REG TC_IMR; /* Interrupt Mask Register */
}
AT91S_TC, *AT91PS_TC;
} AT91S_TC, *AT91PS_TC;
#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
@ -93,8 +92,7 @@ typedef struct _AT91S_USART
AT91_REG US_TNCR; /* Transmit Next Counter Register */
AT91_REG US_PTCR; /* PDC Transfer Control Register */
AT91_REG US_PTSR; /* PDC Transfer Status Register */
}
AT91S_USART, *AT91PS_USART;
} AT91S_USART, *AT91PS_USART;
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
@ -105,8 +103,7 @@ typedef struct _AT91S_CKGR
AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
AT91_REG CKGR_PLLAR; /* PLL A Register */
AT91_REG CKGR_PLLBR; /* PLL B Register */
}
AT91S_CKGR, *AT91PS_CKGR;
} AT91S_CKGR, *AT91PS_CKGR;
/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */
@ -184,8 +181,7 @@ typedef struct _AT91S_PIO
AT91_REG PIO_OWER; /* Output Write Enable Register */
AT91_REG PIO_OWDR; /* Output Write Disable Register */
AT91_REG PIO_OWSR; /* Output Write Status Register */
}
AT91S_PIO, *AT91PS_PIO;
} AT91S_PIO, *AT91PS_PIO;
/******************************************************************************/
@ -217,8 +213,7 @@ typedef struct _AT91S_DBGU
AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
}
AT91S_DBGU, *AT91PS_DBGU;
} AT91S_DBGU, *AT91PS_DBGU;
/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
@ -253,8 +248,7 @@ AT91S_DBGU, *AT91PS_DBGU;
typedef struct _AT91S_SMC2
{
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
}
AT91S_SMC2, *AT91PS_SMC2;
} AT91S_SMC2, *AT91PS_SMC2;
/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
@ -293,8 +287,7 @@ typedef struct _AT91S_PMC
AT91_REG PMC_IDR; /* Interrupt Disable Register */
AT91_REG PMC_SR; /* Status Register */
AT91_REG PMC_IMR; /* Interrupt Mask Register */
}
AT91S_PMC, *AT91PS_PMC;
} AT91S_PMC, *AT91PS_PMC;
/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */
@ -396,8 +389,7 @@ typedef struct _AT91S_EMAC
AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
}
AT91S_EMAC, *AT91PS_EMAC;
} AT91S_EMAC, *AT91PS_EMAC;
/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */
#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
@ -505,8 +497,7 @@ typedef struct _AT91S_SPI
AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
}
AT91S_SPI, *AT91PS_SPI;
} AT91S_SPI, *AT91PS_SPI;
/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */
@ -579,8 +570,7 @@ typedef struct _AT91S_PDC
AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
}
AT91S_PDC, *AT91PS_PDC;
} AT91S_PDC, *AT91PS_PDC;
/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */
@ -702,6 +692,10 @@ AT91S_PDC, *AT91PS_PDC;
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */

2
include/at91rm9200_net.h
View File

@ -52,6 +52,6 @@ void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops);
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops);
#endif /* AT91RM9200_ETHERNET */

8
include/dm9161.h
View File

@ -124,7 +124,7 @@
/****************** function prototypes **********************/
static unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
static unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
static unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
static unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);
unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);