Blackfin: update anomaly lists
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
50ca954028
commit
0656ef2ba2
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@ -2,12 +2,12 @@
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* File: include/asm-blackfin/mach-bf527/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
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* - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -23,20 +23,66 @@
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (1)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (1)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (1)
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (1)
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/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (1)
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/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
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#define ANOMALY_05000342 (1)
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
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/* USB Calibration Value Is Not Initialized */
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#define ANOMALY_05000346 (1)
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/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (1)
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/* Security Features Are Not Functional */
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#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (1)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* New Feature: Higher Default CCLK Rate */
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#define ANOMALY_05000368 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* Authentication Fails To Initiate */
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#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
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/* Data Read From L3 Memory by USB DMA May be Corrupted */
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#define ANOMALY_05000380 (1)
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/* USB Full-speed Mode not Fully Tested */
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#define ANOMALY_05000381 (1)
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/* New Feature: Boot from OTP Memory */
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#define ANOMALY_05000385 (1)
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/* New Feature: bfrom_SysControl() Routine */
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#define ANOMALY_05000386 (1)
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/* New Feature: Programmable Preboot Settings */
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#define ANOMALY_05000387 (1)
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/* Reset Vector Must Not Be in SDRAM Memory Space */
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#define ANOMALY_05000389 (1)
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/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
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#define ANOMALY_05000392 (1)
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/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000393 (1)
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/* New Feature: Log Buffer Functionality */
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#define ANOMALY_05000394 (1)
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/* New Feature: Hook Routine Functionality */
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#define ANOMALY_05000395 (1)
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/* New Feature: Header Indirect Bit */
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#define ANOMALY_05000396 (1)
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/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
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#define ANOMALY_05000397 (1)
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/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
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#define ANOMALY_05000398 (1)
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/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
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#define ANOMALY_05000399 (1)
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/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
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#define ANOMALY_05000401 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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@ -49,7 +95,10 @@
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000363 (0)
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#endif
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@ -2,12 +2,12 @@
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* File: include/asm-blackfin/mach-bf533/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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* - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -164,6 +164,8 @@
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#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
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/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
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#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
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#define ANOMALY_05000315 (1)
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/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
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#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* UART Break Signal Issues */
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#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* PPI Does Not Start Properly In Specific Mode */
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#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* These anomalies have been "phased" out of analog.com anomaly sheets and are
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* here to show running on older silicon just isn't feasible.
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#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
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/* Internal Voltage Regulator may not start up */
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#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#endif
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@ -2,12 +2,12 @@
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* File: include/asm-blackfin/mach-bf537/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
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* - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define ANOMALY_05000322 (1)
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
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/* New Feature: UART Remains Enabled after UART Boot */
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#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (1)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
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#define ANOMALY_05000359 (1)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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@ -148,5 +158,7 @@
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000363 (0)
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#endif
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* File: include/asm-blackfin/mach-bf548/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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* - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
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/* Synchronous Burst Flash Boot Mode Is Not Functional */
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#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
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/* Host DMA Boot Mode Is Not Functional */
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/* Host DMA Boot Modes Are Not Functional */
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#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
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/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
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#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
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#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
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/* USB Calibration Value Is Not Intialized */
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#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
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/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
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/* Data Lost when Core Reads SDH Data FIFO */
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#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
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/* PLL Status Register Is Inaccurate */
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#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
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/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
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#define ANOMALY_05000353 (1)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
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/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
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#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* External Memory Read Access Hangs Core With PLL Bypass */
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#define ANOMALY_05000360 (1)
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
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#define ANOMALY_05000365 (1)
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/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
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#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
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/* Addressing Conflict between Boot ROM and Asynchronous Memory */
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#define ANOMALY_05000369 (1)
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/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
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#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (__SILICON_REVISION__ < 1)
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#define ANOMALY_05000371 (1)
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/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
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#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
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/* Mobile DDR Operation Not Functional */
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#define ANOMALY_05000377 (1)
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/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
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#define ANOMALY_05000378 (1)
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/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
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#define ANOMALY_05000379 (1)
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/* 8-Bit NAND Flash Boot Mode Not Functional */
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#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
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/* Some ATAPI Modes Are Not Functional */
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#define ANOMALY_05000383 (1)
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/* Boot from OTP Memory Not Functional */
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#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
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/* bfrom_SysControl() Firmware Routine Not Functional */
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#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
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/* Programmable Preboot Settings Not Functional */
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#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
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/* CRC32 Checksum Support Not Functional */
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#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
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/* Reset Vector Must Not Be in SDRAM Memory Space */
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#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
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/* Changed Meaning of BCODE Field in SYSCR Register */
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#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
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/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
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#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
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/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
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/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
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/* Log Buffer Not Functional */
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#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
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/* Hook Routine Not Functional */
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#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
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/* Header Indirect Bit Not Functional */
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#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
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/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
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#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
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/* Lockbox SESR Disallows Certain User Interrupts */
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#define ANOMALY_05000404 (1)
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/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
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#define ANOMALY_05000405 (1)
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/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
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#define ANOMALY_05000406 (1)
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/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
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#define ANOMALY_05000407 (1)
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/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
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#define ANOMALY_05000408 (1)
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/* Lockbox firmware leaves MDMA0 channel enabled */
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#define ANOMALY_05000409 (1)
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/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
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#define ANOMALY_05000411 (1)
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/* FIFO Boot Mode Is Not Functional */
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#define ANOMALY_05000412 (1)
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/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
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#define ANOMALY_05000413 (1)
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/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
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#define ANOMALY_05000414 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000363 (0)
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#endif
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@ -2,12 +2,12 @@
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* File: include/asm-blackfin/mach-bf561/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2007 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
* - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
|
@ -256,15 +256,20 @@
|
|||
#define ANOMALY_05000357 (1)
|
||||
/* Conflicting Column Address Widths Causes SDRAM Errors */
|
||||
#define ANOMALY_05000362 (1)
|
||||
/* UART Break Signal Issues */
|
||||
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue