ppc4xx: Update Sequoia/Rainier bootstrap command
As suggested by David Mitchell, here an update for the Sequoia/Rainier bootstrap command. Signed-off-by: Stefan Roese <sr@denx.de>
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Stefan Roese
parent
f31b0aecb5
commit
02ba7022f6
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@ -26,76 +26,185 @@
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#include <command.h>
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#include <i2c.h>
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static u8 boot_533_nor[] = {
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0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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/*
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* There are 2 versions of production Sequoia & Rainier platforms.
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* The primary difference is the reference clock. Those with
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* 33333333 reference clocks will also have 667MHz rated
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* processors. Not enough differences to have unique clock
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* settings.
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*
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* NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
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* values are independent of the rest of the clock settings.
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*
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* All Sequoias & Rainiers select from two possible EEPROMs in Boot
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* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
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* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
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* the only value affected for a 66MHz PCI and simply needs a +0x10.
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*/
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#define NAND_COMPATIBLE 0x01
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#define NOR_COMPATIBLE 0x02
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/* check with Stefan on CFG_I2C_EEPROM_ADDR */
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#define I2C_EEPROM_ADDR 0x52
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static char *config_labels[] = {
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"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
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"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
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"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
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"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
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"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
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"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
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"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
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"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
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NULL
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};
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static u8 boot_533_nand[] = {
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0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10,
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
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static u8 boot_configs[][17] = {
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{
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(NOR_COMPATIBLE),
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0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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},
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{
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(NAND_COMPATIBLE | NOR_COMPATIBLE),
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0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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},
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{
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(NOR_COMPATIBLE),
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0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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},
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{
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(NOR_COMPATIBLE),
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0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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},
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{
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(NAND_COMPATIBLE | NOR_COMPATIBLE),
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0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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},
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{
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(NAND_COMPATIBLE | NOR_COMPATIBLE),
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0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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},
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{
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(NOR_COMPATIBLE),
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0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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},
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{
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(NAND_COMPATIBLE | NOR_COMPATIBLE),
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0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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},
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{
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0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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}
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};
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static u8 boot_667_nor[] = {
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0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
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};
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static u8 boot_667_nand[] = {
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0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10,
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
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/*
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* Bytes 6,8,9,11 change for NAND boot
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*/
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static u8 nand_boot[] = {
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0xd0, 0xa0, 0x68, 0x58
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};
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static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u8 chip;
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u8 *buf;
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int cpu_freq;
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u8 *buf, bNAND;
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int x, y, nbytes, selcfg;
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extern char console_buffer[];
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if (argc < 3) {
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if (argc < 2) {
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printf("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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cpu_freq = simple_strtol(argv[1], NULL, 10);
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if (!((cpu_freq == 533) || (cpu_freq == 667))) {
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printf("Unsupported cpu-frequency - only 533 and 667 supported\n");
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return 1;
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}
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/* use 0x52 as I2C EEPROM address for now */
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chip = 0x52;
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if ((strcmp(argv[2], "nor") != 0) &&
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(strcmp(argv[2], "nand") != 0)) {
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if ((strcmp(argv[1], "nor") != 0) &&
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(strcmp(argv[1], "nand") != 0)) {
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printf("Unsupported boot-device - only nor|nand support\n");
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return 1;
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}
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if (strcmp(argv[2], "nand") == 0) {
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switch (cpu_freq) {
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default:
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case 533:
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buf = boot_533_nand;
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break;
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case 667:
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buf = boot_667_nand;
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break;
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/* set the nand flag based on provided input */
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if ((strcmp(argv[1], "nand") == 0))
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bNAND = 1;
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else
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bNAND = 0;
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printf("Available configurations: \n\n");
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if (bNAND) {
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for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
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/* filter on nand compatible */
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if (boot_configs[x][0] & NAND_COMPATIBLE) {
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printf(" %d - %s\n", (y+1), config_labels[x]);
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y++;
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}
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}
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} else {
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switch (cpu_freq) {
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default:
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case 533:
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buf = boot_533_nor;
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break;
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case 667:
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buf = boot_667_nor;
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break;
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for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
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/* filter on nor compatible */
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if (boot_configs[x][0] & NOR_COMPATIBLE) {
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printf(" %d - %s\n", (y+1), config_labels[x]);
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y++;
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}
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}
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}
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if (i2c_write(chip, 0, 1, buf, 16) != 0)
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printf("Error writing to EEPROM at address 0x%x\n", chip);
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do {
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nbytes = readline(" Selection [1-x / quit]: ");
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if (nbytes) {
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if (strcmp(console_buffer, "quit") == 0)
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return 0;
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selcfg = simple_strtol(console_buffer, NULL, 10);
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if ((selcfg < 1) || (selcfg > y))
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nbytes = 0;
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}
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} while (nbytes == 0);
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y = (selcfg - 1);
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for (x = 0; boot_configs[x][0] != 0; x++) {
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if (bNAND) {
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if (boot_configs[x][0] & NAND_COMPATIBLE) {
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if (y > 0)
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y--;
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else if (y < 1)
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break;
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}
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} else {
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if (boot_configs[x][0] & NOR_COMPATIBLE) {
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if (y > 0)
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y--;
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else if (y < 1)
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break;
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}
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}
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}
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buf = &boot_configs[x][1];
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if (bNAND) {
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buf[6] = nand_boot[0];
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buf[8] = nand_boot[1];
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buf[9] = nand_boot[2];
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buf[11] = nand_boot[3];
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}
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/* check CPLD register +5 for PCI 66MHz flag */
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if (in8(CFG_BCSR_BASE + 5) & 0x01)
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buf[5] += 0x10;
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if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
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printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
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udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
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printf("Done\n");
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@ -105,7 +214,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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}
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U_BOOT_CMD(
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bootstrap, 3, 0, do_bootstrap,
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bootstrap, 2, 0, do_bootstrap,
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"bootstrap - program the I2C bootstrap EEPROM\n",
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"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
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"<nand|nor> - strap to boot from NAND or NOR flash\n"
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);
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