Add support for AT91SAM9260EK
Support for booting from internal DataFlash, external DataFlash card or NAND flash is available. Signed-off-by: Stelian Pop <stelian@popies.net>
This commit is contained in:
Stelian Pop
Jean-Christophe PLAGNIOL-VILLARD
parent
1762f13b4a
commit
0176d43e75
1
MAKEALL
1
MAKEALL
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@ -451,6 +451,7 @@ LIST_ARM7=" \
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LIST_ARM9=" \
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at91cap9adk \
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at91rm9200dk \
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at91sam9260ek \
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cmc_pu2 \
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ap920t \
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ap922_XA10 \
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3
Makefile
3
Makefile
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@ -2308,6 +2308,9 @@ at91cap9adk_config : unconfig
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at91rm9200dk_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
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at91sam9260ek_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
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cmc_pu2_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
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@ -0,0 +1,50 @@
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := at91sam9260ek.o led.o nand.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,236 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop <at> leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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static void at91sam9260ek_serial_hw_init(void)
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{
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#ifdef CONFIG_USART0
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at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
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at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
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#endif
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#ifdef CONFIG_USART1
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at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
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at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
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#endif
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#ifdef CONFIG_USART2
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at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
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at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
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#endif
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#ifdef CONFIG_USART3 /* DBGU */
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at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
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at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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#endif
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}
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#ifdef CONFIG_CMD_NAND
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static void at91sam9260ek_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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/* Configure RDY/BSY */
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at91_set_gpio_input(AT91_PIN_PC13, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(AT91_PIN_PC14, 1);
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}
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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static void at91sam9260ek_spi_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
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at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */
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at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
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at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
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at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
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}
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#endif
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#ifdef CONFIG_MACB
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static void at91sam9260ek_macb_hw_init(void)
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{
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PA17) => PHY normal mode (not Test mode)
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* ERX0 (PA14) => PHY ADDR0
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* ERX1 (PA15) => PHY ADDR1
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* ERX2 (PA25) => PHY ADDR2
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* ERX3 (PA26) => PHY ADDR3
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* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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AT91_RSTC_ERSTL | (0x0D << 8) |
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AT91_RSTC_URSTEN);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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AT91_RSTC_ERSTL | (0x0 << 8) |
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AT91_RSTC_URSTEN);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
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at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
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at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
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at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
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at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
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at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
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at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
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at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
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at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
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at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
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#ifndef CONFIG_RMII
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at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
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at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
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at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
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at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
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at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
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at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
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at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
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at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
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#endif
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}
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of AT91SAM9260EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91sam9260ek_serial_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91sam9260ek_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91sam9260ek_spi_hw_init();
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#endif
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#ifdef CONFIG_MACB
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at91sam9260ek_macb_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_MACB
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init(gd->bd);
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#endif
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}
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#endif
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@ -0,0 +1 @@
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TEXT_BASE = 0x23f00000
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@ -0,0 +1,64 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop <at> leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#define RED_LED AT91_PIN_PA9 /* this is the power led */
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#define GREEN_LED AT91_PIN_PA6 /* this is the user led */
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void red_LED_on(void)
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{
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at91_set_gpio_value(RED_LED, 1);
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}
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void red_LED_off(void)
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{
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at91_set_gpio_value(RED_LED, 0);
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}
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void green_LED_on(void)
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{
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at91_set_gpio_value(GREEN_LED, 0);
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}
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void green_LED_off(void)
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{
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at91_set_gpio_value(GREEN_LED, 1);
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}
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void coloured_LED_init(void)
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{
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
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at91_set_gpio_output(RED_LED, 1);
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at91_set_gpio_output(GREEN_LED, 1);
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at91_set_gpio_value(RED_LED, 0);
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at91_set_gpio_value(GREEN_LED, 1);
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}
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@ -0,0 +1,79 @@
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/*
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* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
*
|
||||
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
|
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*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91_pio.h>
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#ifdef CONFIG_CMD_NAND
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#include <nand.h>
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/*
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* hardware specific access to control-lines
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*/
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#define MASK_ALE (1 << 21) /* our ALE is AD21 */
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#define MASK_CLE (1 << 22) /* our CLE is AD22 */
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static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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struct nand_chip *this = mtd->priv;
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
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|
||||
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
|
||||
switch (cmd) {
|
||||
case NAND_CTL_SETCLE:
|
||||
IO_ADDR_W |= MASK_CLE;
|
||||
break;
|
||||
case NAND_CTL_SETALE:
|
||||
IO_ADDR_W |= MASK_ALE;
|
||||
break;
|
||||
case NAND_CTL_CLRNCE:
|
||||
at91_set_gpio_value(AT91_PIN_PC14, 1);
|
||||
break;
|
||||
case NAND_CTL_SETNCE:
|
||||
at91_set_gpio_value(AT91_PIN_PC14, 0);
|
||||
break;
|
||||
}
|
||||
this->IO_ADDR_W = (void *) IO_ADDR_W;
|
||||
}
|
||||
|
||||
static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return at91_get_gpio_value(AT91_PIN_PC13);
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
nand->eccmode = NAND_ECC_SOFT;
|
||||
nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
|
||||
nand->dev_ready = at91sam9260ek_nand_ready;
|
||||
nand->chip_delay = 20;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm926ejs/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -417,13 +417,13 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
|
|||
|
||||
/* choose RMII or MII mode. This depends on the board */
|
||||
#ifdef CONFIG_RMII
|
||||
#ifdef CONFIG_AT91CAP9ADK
|
||||
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
|
||||
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
|
||||
#else
|
||||
macb_writel(macb, USRIO, 0);
|
||||
#endif
|
||||
#else
|
||||
#ifdef CONFIG_AT91CAP9ADK
|
||||
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
|
||||
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
|
||||
#else
|
||||
macb_writel(macb, USRIO, MACB_BIT(MII));
|
||||
|
|
|
|||
|
|
@ -107,7 +107,6 @@
|
|||
#define AT91_USART1 AT91CAP9_BASE_US1
|
||||
#define AT91_USART2 AT91CAP9_BASE_US2
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* include/asm-arm/arch-at91/at91sam9260.h
|
||||
*
|
||||
* (C) 2006 Andrew Victor
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9260 datasheet revision A (Preliminary).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_H
|
||||
#define AT91SAM9260_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
|
||||
#define AT91SAM9260_ID_US0 6 /* USART 0 */
|
||||
#define AT91SAM9260_ID_US1 7 /* USART 1 */
|
||||
#define AT91SAM9260_ID_US2 8 /* USART 2 */
|
||||
#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
|
||||
#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
|
||||
#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
|
||||
#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
|
||||
#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
|
||||
#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
|
||||
#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
|
||||
#define AT91SAM9260_ID_UHP 20 /* USB Host port */
|
||||
#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
|
||||
#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
|
||||
#define AT91SAM9260_ID_US3 23 /* USART 3 */
|
||||
#define AT91SAM9260_ID_US4 24 /* USART 4 */
|
||||
#define AT91SAM9260_ID_US5 25 /* USART 5 */
|
||||
#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
|
||||
#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
|
||||
#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
|
||||
#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
|
||||
#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9260_BASE_TCB0 0xfffa0000
|
||||
#define AT91SAM9260_BASE_TC0 0xfffa0000
|
||||
#define AT91SAM9260_BASE_TC1 0xfffa0040
|
||||
#define AT91SAM9260_BASE_TC2 0xfffa0080
|
||||
#define AT91SAM9260_BASE_UDP 0xfffa4000
|
||||
#define AT91SAM9260_BASE_MCI 0xfffa8000
|
||||
#define AT91SAM9260_BASE_TWI 0xfffac000
|
||||
#define AT91SAM9260_BASE_US0 0xfffb0000
|
||||
#define AT91SAM9260_BASE_US1 0xfffb4000
|
||||
#define AT91SAM9260_BASE_US2 0xfffb8000
|
||||
#define AT91SAM9260_BASE_SSC 0xfffbc000
|
||||
#define AT91SAM9260_BASE_ISI 0xfffc0000
|
||||
#define AT91SAM9260_BASE_EMAC 0xfffc4000
|
||||
#define AT91SAM9260_BASE_SPI0 0xfffc8000
|
||||
#define AT91SAM9260_BASE_SPI1 0xfffcc000
|
||||
#define AT91SAM9260_BASE_US3 0xfffd0000
|
||||
#define AT91SAM9260_BASE_US4 0xfffd4000
|
||||
#define AT91SAM9260_BASE_US5 0xfffd8000
|
||||
#define AT91SAM9260_BASE_TCB1 0xfffdc000
|
||||
#define AT91SAM9260_BASE_TC3 0xfffdc000
|
||||
#define AT91SAM9260_BASE_TC4 0xfffdc040
|
||||
#define AT91SAM9260_BASE_TC5 0xfffdc080
|
||||
#define AT91SAM9260_BASE_ADC 0xfffe0000
|
||||
#define AT91_BASE_SYS 0xffffe800
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91_USART0 AT91SAM9260_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9260_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9260_BASE_US2
|
||||
#define AT91_USART3 AT91SAM9260_BASE_US3
|
||||
#define AT91_USART4 AT91SAM9260_BASE_US4
|
||||
#define AT91_USART5 AT91SAM9260_BASE_US5
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
|
||||
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
|
||||
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
||||
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
|
||||
|
||||
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
|
||||
|
||||
#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
|
||||
#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* include/asm-arm/arch-at91/at91sam9260_matrix.h
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9260 datasheet revision B.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_MATRIX_H
|
||||
#define AT91SAM9260_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#endif
|
||||
|
|
@ -79,7 +79,6 @@
|
|||
#define AT91_SDRAMC_MD_SDRAM 0
|
||||
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
|
||||
|
||||
|
||||
/* Static Memory Controller (SMC) registers */
|
||||
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
|
||||
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
|
||||
|
|
|
|||
|
|
@ -200,7 +200,6 @@ static unsigned long at91_pios[] = {
|
|||
#endif
|
||||
};
|
||||
|
||||
|
||||
static inline void *pin_to_controller(unsigned pin)
|
||||
{
|
||||
pin -= PIN_BASE;
|
||||
|
|
@ -228,7 +227,6 @@ static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* mux the pin to the "A" internal peripheral role.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -20,6 +20,10 @@
|
|||
#include <asm/arch/at91rm9200.h>
|
||||
#elif defined(CONFIG_AT91SAM9260)
|
||||
#include <asm/arch/at91sam9260.h>
|
||||
#define AT91_BASE_EMAC AT91SAM9260_BASE_EMAC
|
||||
#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
|
||||
#define AT91_ID_UHP AT91SAM9260_ID_UHP
|
||||
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
|
||||
#elif defined(CONFIG_AT91SAM9261)
|
||||
#include <asm/arch/at91sam9261.h>
|
||||
#elif defined(CONFIG_AT91SAM9263)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
*
|
||||
* Configuation settings for the AT91SAM9260EK board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */
|
||||
#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */
|
||||
#define CFG_HZ 1000000 /* 1us resolution */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
|
||||
#define CONFIG_AT91SAM9260EK 1 /* on an AT91SAM9260EK Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
#undef CONFIG_USART2
|
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||
"root=/dev/mtdblock0 rw rootfstype=jffs2"
|
||||
|
||||
/* #define CONFIG_ENV_OVERWRITE 1 */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1
|
||||
#define CONFIG_BOOTP_BOOTPATH 1
|
||||
#define CONFIG_BOOTP_GATEWAY 1
|
||||
#define CONFIG_BOOTP_HOSTNAME 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_AUTOSCRIPT
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_CMD_PING 1
|
||||
#define CONFIG_CMD_DHCP 1
|
||||
#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_CMD_USB 1
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
|
||||
|
||||
/* DataFlash */
|
||||
#define CONFIG_HAS_DATAFLASH 1
|
||||
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
|
||||
#define CFG_MAX_DATAFLASH_BANKS 2
|
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
|
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
|
||||
#define AT91_SPI_CLK 33000000
|
||||
#define DATAFLASH_TCSS (0x1a << 16)
|
||||
#define DATAFLASH_TCHS (0x1 << 24)
|
||||
|
||||
/* NAND flash */
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define CFG_NAND_BASE 0x40000000
|
||||
|
||||
/* NOR flash - no real flash on this board */
|
||||
#define CFG_NO_FLASH 1
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_RMII 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R 1
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define LITTLEENDIAN 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CFG_USB_OHCI_CPU_INIT 1
|
||||
#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
|
||||
#define CFG_USB_OHCI_SLOT_NAME "at91sam9260"
|
||||
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
|
||||
#define CFG_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM
|
||||
#define CFG_MEMTEST_END 0x23e00000
|
||||
|
||||
#undef CFG_USE_DATAFLASH_CS0
|
||||
#define CFG_USE_DATAFLASH_CS1 1
|
||||
#undef CFG_USE_NANDFLASH
|
||||
|
||||
#ifdef CFG_USE_DATAFLASH_CS0
|
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
|
||||
#define CFG_ENV_IS_IN_DATAFLASH 1
|
||||
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
|
||||
#define CFG_ENV_OFFSET 0x4200
|
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
|
||||
#define CFG_ENV_SIZE 0x4200
|
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm"
|
||||
|
||||
#elif CFG_USE_DATAFLASH_CS1
|
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash on CS1 */
|
||||
#define CFG_ENV_IS_IN_DATAFLASH 1
|
||||
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
|
||||
#define CFG_ENV_OFFSET 0x4200
|
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET)
|
||||
#define CFG_ENV_SIZE 0x4200
|
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm"
|
||||
|
||||
#else /* CFG_USE_NANDFLASH */
|
||||
|
||||
/* bootstrap + u-boot + env + linux in nandflash */
|
||||
#define CFG_ENV_IS_IN_NAND 1
|
||||
#define CFG_ENV_OFFSET 0x60000
|
||||
#define CFG_ENV_OFFSET_REDUND 0x80000
|
||||
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
|
||||
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CFG_PROMPT "U-Boot> "
|
||||
#define CFG_CBSIZE 256
|
||||
#define CFG_MAXARGS 16
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
|
||||
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue