267 lines
5.3 KiB
C
267 lines
5.3 KiB
C
/* Driver for Calypso IRQ controller */
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/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <debug.h>
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#include <memory.h>
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#include <arm.h>
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#include <calypso/irq.h>
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#define BASE_ADDR_IRQ 0xfffffa00
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enum irq_reg {
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IT_REG1 = 0x00,
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IT_REG2 = 0x02,
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MASK_IT_REG1 = 0x08,
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MASK_IT_REG2 = 0x0a,
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IRQ_NUM = 0x10,
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FIQ_NUM = 0x12,
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IRQ_CTRL = 0x14,
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};
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#define ILR_IRQ(x) (0x20 + (x*2))
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#define IRQ_REG(x) ((void *)BASE_ADDR_IRQ + (x))
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#define NR_IRQS 32
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static uint8_t default_irq_prio[] = {
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[IRQ_WATCHDOG] = 0xff,
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[IRQ_TIMER1] = 0xff,
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[IRQ_TIMER2] = 0xff,
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[IRQ_TSP_RX] = 0,
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[IRQ_TPU_FRAME] = 3,
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[IRQ_TPU_PAGE] = 0xff,
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[IRQ_SIMCARD] = 0xff,
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[IRQ_UART_MODEM] = 8,
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[IRQ_KEYPAD_GPIO] = 4,
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[IRQ_RTC_TIMER] = 9,
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[IRQ_RTC_ALARM_I2C] = 10,
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[IRQ_ULPD_GAUGING] = 2,
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[IRQ_EXTERNAL] = 12,
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[IRQ_SPI] = 0xff,
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[IRQ_DMA] = 0xff,
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[IRQ_API] = 0xff,
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[IRQ_SIM_DETECT] = 0,
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[IRQ_EXTERNAL_FIQ] = 7,
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[IRQ_UART_IRDA] = 2,
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[IRQ_ULPD_GSM_TIMER] = 1,
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[IRQ_GEA] = 0xff,
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};
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static irq_handler *irq_handlers[NR_IRQS];
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static void _irq_enable(enum irq_nr nr, int enable)
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{
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uint16_t *reg = IRQ_REG(MASK_IT_REG1);
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uint16_t val;
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if (nr > 15) {
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reg = IRQ_REG(MASK_IT_REG2);
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nr -= 16;
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}
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val = readw(reg);
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if (enable)
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val &= ~(1 << nr);
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else
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val |= (1 << nr);
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writew(val, reg);
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}
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void irq_enable(enum irq_nr nr)
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{
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_irq_enable(nr, 1);
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}
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void irq_disable(enum irq_nr nr)
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{
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_irq_enable(nr, 0);
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}
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void irq_config(enum irq_nr nr, int fiq, int edge, int8_t prio)
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{
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uint16_t val;
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if (prio == -1)
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prio = default_irq_prio[nr];
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if (prio > 31)
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prio = 31;
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val = prio << 2;
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if (edge)
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val |= 0x02;
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if (fiq)
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val |= 0x01;
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writew(val, IRQ_REG(ILR_IRQ(nr)));
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}
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/* Entry point for interrupts */
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void irq(void)
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{
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uint8_t num, tmp;
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irq_handler *handler;
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#if 1
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/* Hardware interrupt detection mode */
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num = readb(IRQ_REG(IRQ_NUM)) & 0x1f;
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printd("i%02x\n", num);
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handler = irq_handlers[num];
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if (handler)
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handler(num);
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#else
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/* Software interrupt detection mode */
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{
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uint16_t it_reg, mask_reg;
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uint32_t irqs;
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it_reg = readw(IRQ_REG(IT_REG1));
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mask_reg = readw(IRQ_REG(MASK_IT_REG1));
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irqs = it_reg & ~mask_reg;
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it_reg = readw(IRQ_REG(IT_REG2));
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mask_reg = readw(IRQ_REG(MASK_IT_REG2));
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irqs |= (it_reg & ~mask_reg) << 16;
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for (num = 0; num < 32; num++) {
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if (irqs & (1 << num)) {
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printd("i%d\n", num);
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handler = irq_handlers[num];
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if (handler)
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handler(num);
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/* clear this interrupt */
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if (num < 16)
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writew(~(1 << num), IRQ_REG(IT_REG1));
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else
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writew(~(1 << (num-16)), IRQ_REG(IT_REG2));
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}
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}
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dputchar('\n');
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}
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#endif
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/* Start new IRQ agreement */
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tmp = readb(IRQ_REG(IRQ_CTRL));
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tmp |= 0x01;
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writeb(tmp, IRQ_REG(IRQ_CTRL));
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}
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/* Entry point for FIQs */
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void fiq(void)
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{
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uint8_t num, tmp;
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irq_handler *handler;
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num = readb(IRQ_REG(FIQ_NUM)) & 0x1f;
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if (num) {
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printd("f%02x\n", num);
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}
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handler = irq_handlers[num];
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if (handler)
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handler(num);
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/* Start new FIQ agreement */
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tmp = readb(IRQ_REG(IRQ_CTRL));
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tmp |= 0x02;
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writeb(tmp, IRQ_REG(IRQ_CTRL));
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}
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void irq_register_handler(enum irq_nr nr, irq_handler *handler)
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{
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if (nr > NR_IRQS)
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return;
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irq_handlers[nr] = handler;
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}
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#define BASE_ADDR_IBOOT_EXC 0x0080001C
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extern uint32_t _exceptions;
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/* Install the exception handlers to where the ROM loader jumps */
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void calypso_exceptions_install(void)
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{
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uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC;
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uint32_t *exceptions_src = &_exceptions;
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int i;
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for (i = 0; i < 7; i++)
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*exceptions_dst++ = *exceptions_src++;
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}
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static void set_default_priorities(void)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++) {
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uint16_t val;
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uint8_t prio = default_irq_prio[i];
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if (prio > 31)
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prio = 31;
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val = readw(IRQ_REG(ILR_IRQ(i)));
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val &= ~(0x1f << 2);
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val |= prio << 2;
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writew(val, IRQ_REG(ILR_IRQ(i)));
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}
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}
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static uint32_t irq_nest_mask;
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/* mask off all interrupts that have a lower priority than irq_nr */
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static void mask_all_lower_prio_irqs(enum irq_nr irq)
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{
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uint8_t our_prio = readb(IRQ_REG(ILR_IRQ(irq))) >> 2;
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int i;
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for (i = 0; i < _NR_IRQ; i++) {
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uint8_t prio;
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if (i == irq)
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continue;
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prio = readb(IRQ_REG(ILR_IRQ(i))) >> 2;
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if (prio >= our_prio)
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irq_nest_mask |= (1 << i);
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}
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}
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void irq_init(void)
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{
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/* set default priorities */
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set_default_priorities();
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/* mask all interrupts off */
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writew(0xffff, IRQ_REG(MASK_IT_REG1));
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writew(0xffff, IRQ_REG(MASK_IT_REG2));
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/* clear all pending interrupts */
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writew(0, IRQ_REG(IT_REG1));
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writew(0, IRQ_REG(IT_REG2));
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/* enable interrupts globally to the ARM core */
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arm_enable_interrupts();
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}
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