203 lines
5.4 KiB
C
203 lines
5.4 KiB
C
/* Driver for Calypso clock management */
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/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <stdint.h>
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#include <stdio.h>
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//#define DEBUG
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#include <debug.h>
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#include <memory.h>
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#include <calypso/clock.h>
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#define REG_DPLL 0xffff9800
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#define DPLL_LOCK (1 << 0)
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#define DPLL_BREAKLN (1 << 1)
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#define DPLL_BYPASS_DIV_SHIFT 2 /* 2 bits */
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#define DPLL_PLL_ENABLE (1 << 4)
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#define DPLL_PLL_DIV_SHIFT 5 /* 2 bits */
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#define DPLL_PLL_MULT_SHIFT 7 /* 5 bits */
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#define DPLL_TEST (1 << 12)
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#define DPLL_IOB (1 << 13) /* Initialize on break */
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#define DPLL_IAI (1 << 14) /* Initialize after Idle */
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#define BASE_ADDR_CLKM 0xfffffd00
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#define CLKM_REG(m) (BASE_ADDR_CLKM+(m))
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enum clkm_reg {
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CNTL_ARM_CLK = 0,
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CNTL_CLK = 2,
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CNTL_RST = 4,
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CNTL_ARM_DIV = 8,
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};
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/* CNTL_ARM_CLK */
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#define ARM_CLK_BIG_SLEEP (1 << 0) /* MCU Master Clock enabled? */
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#define ARM_CLK_CLKIN_SEL0 (1 << 1) /* MCU source clock (0 = DPLL output, 1 = VTCXO or CLKIN */
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#define ARM_CLK_CLKIN_SEL (1 << 2) /* 0 = VTCXO or 1 = CLKIN */
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#define ARM_CLK_MCLK_DIV5 (1 << 3) /* enable 1.5 or 2.5 division factor */
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#define ARM_CLK_MCLK_DIV_SHIFT 4 /* 3 bits */
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#define ARM_CLK_DEEP_POWER_SHIFT 8
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#define ARM_CLK_DEEP_SLEEP 12
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/* CNTL_CLK */
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#define CLK_IRQ_CLK_DIS (1 << 0) /* IRQ clock control (0 always, 1 according ARM_MCLK_EN) */
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#define CLK_BRIDGE_CLK_DIS (1 << 1)
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#define CLK_TIMER_CLK_DIS (1 << 2)
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#define CLK_DPLL_DIS (1 << 3) /* 0: DPLL is not stopped during SLEEP */
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#define CLK_CLKOUT_EN (1 << 4) /* Enable CLKOUT output pins */
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#define CLK_EN_IDLE3_FLG (1 << 5) /* DSP idle flag control (1 =
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* SAM/HOM register forced to HOM when DSP IDLE3) */
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#define CLK_VCLKOUT_DIV2 (1 << 6) /* 1: VCLKOUT-FR is divided by 2 */
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#define CLK_VTCXO_DIV2 (1 << 7) /* 1: VTCXO is dividied by 2 */
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#define BASE_ADDR_MEMIF 0xfffffb00
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#define MEMIF_REG(x) (BASE_ADDR_MEMIF+(x))
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enum memif_reg {
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API_RHEA_CTL = 0x0e,
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EXTRA_CONF = 0x10,
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};
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static void dump_reg16(uint32_t addr, char *name)
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{
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printf("%s=0x%04x\n", name, readw(addr));
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}
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void calypso_clk_dump(void)
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{
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dump_reg16(REG_DPLL, "REG_DPLL");
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dump_reg16(CLKM_REG(CNTL_ARM_CLK), "CNTL_ARM_CLK");
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dump_reg16(CLKM_REG(CNTL_CLK), "CNTL_CLK");
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dump_reg16(CLKM_REG(CNTL_RST), "CNTL_RST");
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dump_reg16(CLKM_REG(CNTL_ARM_DIV), "CNTL_ARM_DIV");
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}
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void calypso_pll_set(uint16_t inp)
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{
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uint8_t mult = inp >> 8;
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uint8_t div = inp & 0xff;
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uint16_t reg = readw(REG_DPLL);
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reg &= ~0x0fe0;
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reg |= (div & 0x3) << DPLL_PLL_DIV_SHIFT;
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reg |= (mult & 0x1f) << DPLL_PLL_MULT_SHIFT;
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reg |= DPLL_PLL_ENABLE;
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writew(reg, REG_DPLL);
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}
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void calypso_reset_set(enum calypso_rst calypso_rst, int active)
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{
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uint8_t reg = readb(CLKM_REG(CNTL_RST));
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if (active)
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reg |= calypso_rst;
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else
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reg &= ~calypso_rst;
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writeb(reg, CLKM_REG(CNTL_RST));
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}
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int calypso_reset_get(enum calypso_rst calypso_rst)
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{
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uint8_t reg = readb(CLKM_REG(CNTL_RST));
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if (reg & calypso_rst)
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return 1;
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else
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return 0;
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}
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void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
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{
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uint16_t cntl_clock = readw(CLKM_REG(CNTL_CLK));
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uint16_t cntl_arm_clk = readw(CLKM_REG(CNTL_ARM_CLK));
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/* First set the vtcxo_div2 */
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cntl_clock &= ~CLK_VCLKOUT_DIV2;
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if (vtcxo_div2)
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cntl_clock |= CLK_VTCXO_DIV2;
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else
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cntl_clock &= ~CLK_VTCXO_DIV2;
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writew(cntl_clock, CLKM_REG(CNTL_CLK));
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/* Then configure the MCLK divider */
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cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0;
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if (mclk_div & 0x80) {
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mclk_div &= ~0x80;
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cntl_arm_clk |= ARM_CLK_MCLK_DIV5;
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} else
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cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5;
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cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT);
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cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT);
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writew(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK));
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/* Then finally set the PLL */
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calypso_pll_set(inp);
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}
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void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
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enum calypso_mem_width width, int we)
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{
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writew((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7),
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BASE_ADDR_MEMIF + bank);
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}
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void calypso_bootrom(int enable)
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{
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uint16_t conf = readw(MEMIF_REG(EXTRA_CONF));
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conf &= ~(3 << 8);
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// XXX: this can't be correct
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if (enable)
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conf |= (1 << 8);
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else
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conf |= (1 << 8);
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writew(conf, MEMIF_REG(EXTRA_CONF));
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}
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void calypso_debugunit(int enable)
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{
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uint16_t conf = readw(MEMIF_REG(EXTRA_CONF));
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if (enable)
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conf &= ~(1 << 11);
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else
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conf |= (1 << 11);
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writew(conf, MEMIF_REG(EXTRA_CONF));
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}
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#define REG_RHEA_CNTL 0xfffff900
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#define REG_API_CNTL 0xfffff902
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#define REG_ARM_RHEA 0xfffff904
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void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
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uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1)
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{
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writew(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL);
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writew(ws_h | (ws_l << 5), REG_API_CNTL);
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writew(w_en0 | (w_en1 << 1), REG_ARM_RHEA);
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}
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