133 lines
3.4 KiB
C
133 lines
3.4 KiB
C
/* Driver for uWire Master Controller inside TI Calypso */
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/* (C) 2010 by Sylvain Munaut <tnt@246tNt.com>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <stdint.h>
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#include <stdio.h>
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//#define DEBUG
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#include <debug.h>
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#include <memory.h>
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#include <uwire.h>
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#include <delay.h>
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#define BASE_ADDR_UWIRE 0xfffe4000
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#define UWIRE_REG(n) (BASE_ADDR_UWIRE+(n))
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enum uwire_regs {
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REG_DATA = 0x00,
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REG_CSR = 0x02,
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REG_SR1 = 0x04,
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REG_SR2 = 0x06,
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REG_SR3 = 0x08,
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};
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#define UWIRE_CSR_BITS_RD(n) (((n) & 0x1f) << 0)
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#define UWIRE_CSR_BITS_WR(n) (((n) & 0x1f) << 5)
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#define UWIRE_CSR_IDX(n) (((n) & 3) << 10)
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#define UWIRE_CSR_CS_CMD (1 << 12)
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#define UWIRE_CSR_START (1 << 13)
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#define UWIRE_CSR_CSRB (1 << 14)
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#define UWIRE_CSR_RDRB (1 << 15)
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#define UWIRE_CSn_EDGE_RD (1 << 0) /* 1=falling 0=rising */
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#define UWIRE_CSn_EDGE_WR (1 << 1) /* 1=falling 0=rising */
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#define UWIRE_CSn_CS_LVL (1 << 2)
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#define UWIRE_CSn_FRQ_DIV2 (0 << 3)
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#define UWIRE_CSn_FRQ_DIV4 (1 << 3)
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#define UWIRE_CSn_FRQ_DIV8 (2 << 3)
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#define UWIRE_CSn_CKH
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#define UWIRE_CSn_SHIFT(n) (((n) & 1) ? 6 : 0)
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#define UWIRE_CSn_REG(n) (((n) & 2) ? REG_SR2 : REG_SR1)
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#define UWIRE_SR3_CLK_EN (1 << 0)
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#define UWIRE_SR3_CLK_DIV2 (0 << 1)
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#define UWIRE_SR3_CLK_DIV4 (1 << 1)
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#define UWIRE_SR3_CLK_DIV7 (2 << 1)
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#define UWIRE_SR3_CLK_DIV10 (3 << 1)
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static inline void _uwire_wait(int mask, int val)
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{
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while ((readw(UWIRE_REG(REG_CSR)) & mask) != val);
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}
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void uwire_init(void)
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{
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writew(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3));
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/* FIXME only init CS0 for now */
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writew(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)),
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UWIRE_REG(UWIRE_CSn_REG(0)));
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writew(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
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_uwire_wait(UWIRE_CSR_CSRB, 0);
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}
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int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
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{
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uint16_t tmp = 0;
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if (bitlen <= 0 || bitlen > 16)
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return -1;
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if (cs < 0 || cs > 4)
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return -1;
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/* FIXME uwire_init always selects CS0 for now */
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printd("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
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/* select the chip */
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writew(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
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_uwire_wait(UWIRE_CSR_CSRB, 0);
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if (dout) {
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if (bitlen <= 8)
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tmp = *(uint8_t *)dout;
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else if (bitlen <= 16)
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tmp = *(uint16_t *)dout;
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tmp <<= 16 - bitlen; /* align to MSB */
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writew(tmp, UWIRE_REG(REG_DATA));
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printd(", data_out=0x%04hx", tmp);
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}
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tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
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(din ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
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UWIRE_CSR_START;
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writew(tmp, UWIRE_REG(REG_CSR));
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_uwire_wait(UWIRE_CSR_CSRB, 0);
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if (din) {
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_uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
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tmp = readw(UWIRE_REG(REG_DATA));
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printd(", data_in=0x%08x", tmp);
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if (bitlen <= 8)
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*(uint8_t *)din = tmp & 0xff;
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else if (bitlen <= 16)
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*(uint16_t *)din = tmp & 0xffff;
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}
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/* unselect the chip */
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writew(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
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_uwire_wait(UWIRE_CSR_CSRB, 0);
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printd(")\n");
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return 0;
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}
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