153 lines
3.3 KiB
C
153 lines
3.3 KiB
C
/* Calypso DBB internal Timer Driver */
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/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <stdio.h>
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#include <memory.h>
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#include <stdint.h>
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#include <defines.h>
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#include <calypso/timer.h>
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#include <calypso/irq.h>
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#define BASE_ADDR_TIMER 0xfffe3800
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#define TIMER2_OFFSET 0x3000
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#define TIMER_REG(n, m) (((n)-1) ? (BASE_ADDR_TIMER + TIMER2_OFFSET + (m)) : (BASE_ADDR_TIMER + (m)))
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enum timer_reg {
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CNTL_TIMER = 0x00,
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LOAD_TIMER = 0x02,
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READ_TIMER = 0x04,
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};
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enum timer_ctl {
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CNTL_START = (1 << 0),
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CNTL_AUTO_RELOAD = (1 << 1),
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CNTL_CLOCK_ENABLE = (1 << 5),
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};
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/* Regular Timers (1 and 2) */
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void hwtimer_enable(int num, int on)
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{
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uint8_t ctl;
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if (num < 1 || num > 2) {
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printf("Unknown timer %u\n", num);
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return;
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}
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ctl = readb(TIMER_REG(num, CNTL_TIMER));
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if (on)
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ctl |= CNTL_START|CNTL_CLOCK_ENABLE;
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else
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ctl &= ~CNTL_START;
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writeb(ctl, TIMER_REG(num, CNTL_TIMER));
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}
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void hwtimer_config(int num, uint8_t pre_scale, int auto_reload)
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{
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uint8_t ctl;
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ctl = (pre_scale & 0x7) << 2;
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if (auto_reload)
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ctl |= CNTL_AUTO_RELOAD;
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writeb(ctl, TIMER_REG(num, CNTL_TIMER));
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}
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void hwtimer_load(int num, uint16_t val)
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{
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writew(val, TIMER_REG(num, LOAD_TIMER));
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}
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uint16_t hwtimer_read(int num)
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{
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uint8_t ctl = readb(TIMER_REG(num, CNTL_TIMER));
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/* somehow a read results in an abort */
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if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE))
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return 0xFFFF;
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return readw(TIMER_REG(num, READ_TIMER));
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}
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void hwtimer_init(void)
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{
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writeb(CNTL_CLOCK_ENABLE, TIMER_REG(1, CNTL_TIMER));
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writeb(CNTL_CLOCK_ENABLE, TIMER_REG(2, CNTL_TIMER));
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}
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/* Watchdog Timer */
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#define BASE_ADDR_WDOG 0xfffff800
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#define WDOG_REG(m) (BASE_ADDR_WDOG + m)
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enum wdog_reg {
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WD_CNTL_TIMER = CNTL_TIMER,
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WD_LOAD_TIMER = LOAD_TIMER,
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WD_READ_TIMER = 0x02,
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WD_MODE = 0x04,
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};
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enum wdog_ctl {
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WD_CTL_START = (1 << 7),
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WD_CTL_AUTO_RELOAD = (1 << 8)
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};
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enum wdog_mode {
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WD_MODE_DIS_ARM = 0xF5,
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WD_MODE_DIS_CONFIRM = 0xA0,
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WD_MODE_ENABLE = (1 << 15)
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};
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#define WD_CTL_PRESCALE(value) (((value)&0x07) << 9)
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static void wdog_irq(__unused enum irq_nr nr)
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{
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puts("=> WATCHDOG\n");
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}
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void wdog_enable(int on)
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{
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if (on) {
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irq_config(IRQ_WATCHDOG, 0, 0, 0);
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irq_register_handler(IRQ_WATCHDOG, &wdog_irq);
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irq_enable(IRQ_WATCHDOG);
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writew(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
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} else {
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writew(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
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writew(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
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}
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}
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void wdog_reset(void)
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{
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#if 0
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// XXX: this is supposed to reset immediately but does not seem to
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writew(0xF5, WDOG_REG(WD_MODE));
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writew(0xFF, WDOG_REG(WD_MODE));
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#else
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// enable watchdog
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writew(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
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// force expiration
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writew(0x0000, WDOG_REG(WD_LOAD_TIMER));
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writew(0x0000, WDOG_REG(WD_LOAD_TIMER));
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#endif
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}
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